JPH0352682U

JPH0352682U -

Info

Publication number: JPH0352682U
Application number: JP11450589U
Authority: JP
Priority date: 1989-09-29
Filing date: 1989-09-29
Publication date: 1991-05-22

Description

[Brief explanation of drawings]

第１図は本考案の一実施例を説明するための試
験用治具のブロツク回路図、第２図は第１図にお
ける各種データおよび信号の波形図、第３図は本
考案のＩＣ試験用治具ユニツトの斜視図である。１……基本クロツク発生回路、２……タイミン
グ発生回路、３……出力データ取り込み回路、４
……出力データ表示回路、５……被試験ＩＣ、６
……ＩＣ試験用治具回路、７……ＩＣ試験用治具
。 Fig. 1 is a block circuit diagram of a test jig for explaining one embodiment of the present invention, Fig. 2 is a waveform diagram of various data and signals in Fig. 1, and Fig. 3 is a test jig for IC testing of the present invention. FIG. 3 is a perspective view of the jig unit. 1... Basic clock generation circuit, 2... Timing generation circuit, 3... Output data acquisition circuit, 4
...Output data display circuit, 5...IC under test, 6
... IC test jig circuit, 7... IC test jig.

Claims

[Scope of utility model registration request]

A test jig for measuring the setup and hold time of a clock data latch IC under test includes a clock generation circuit that generates a basic clock, a timing setting circuit that sets the timing of input data, and a clock generation circuit that generates a basic clock, a timing setting circuit that sets the timing of input data, and a A single unit includes an output data capture circuit that controls the capture of output data of the IC under test using a strobe signal from the timing setting circuit, and an output data display circuit that displays the output from the capture circuit. IC
Jig for setup and hold time testing.