JPH0648441Y2 - Latchiap characteristics tester - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a latch-up characteristic test of an integrated circuit, particularly a complementary MOS integrated circuit (hereinafter abbreviated as C-MOS IC).

2. Description of the Related Art Generally, a C-MOS IC latch-up characteristic test is distinguished depending on whether a device under test is in a static state or a dynamic state. Conventionally, the latch-up characteristic test is performed only in the static state, and the latch-up characteristic test in the dynamic state is not particularly performed.Several representative patterns are selected and the test is performed for each pattern to perform the dynamic test. The tolerable amount of latch-up in the state was estimated.

However, the above-mentioned conventional latch-up characteristic test device can perform only static measurement, and some selected patterns are performed for each measurement pin. It had the drawback of taking a long time.

The present invention has been made in view of the above conventional circumstances,
Therefore, an object of the present invention is to provide a novel latch-up characteristic test device capable of measuring the latch-up characteristic in a short time by solving the above-mentioned drawbacks inherent in the conventional technique.

Means for Solving the Problems In order to achieve the above object, the latch-up characteristic test device according to the present invention has a pulse voltage waveform with variable peak value and pulse width, a driver pattern for driving a device under test. It has a function of separately generating a waveform and a comparator waveform synchronized with these two waveforms, and automatically measuring the latch-up tolerance for each pattern according to a preset function pattern.

Embodiment Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a latch-up characteristic test circuit according to the present invention, and FIG. 2 is a timing chart of waveforms of respective parts of a test apparatus according to the present invention.

In FIG. 1, the driver power supply units 5 to 7 are connected to the input terminal of the device under test 18, and the comparator circuit 11 is connected to the output terminal.
Connect ~ 13. Further, the pulse voltage generating circuit 15 and the pulse wave shaping circuit 16 are connected to the measurement terminal of the device under test 18. First, the pattern control unit 17 sets the reference timing to the driver pattern generation circuit 3 and the comparator pattern generation circuit 4.
And to the pulse voltage generation circuit 15. A pattern signal is input from the driver pattern generation circuit 3 to the driver power supply units 5 to 7 with a delay of td1 from the reference timing according to a preset pattern, and a desired input voltage VIN is applied to the device under test 18. Next, td2 from the reference timing
With a delay of (> td1), a desired pulse waveform voltage is applied to the measurement terminal through the pulse voltage generation circuit 15 and the pulse wave shaping circuit 16. After that, the judgment is repeated for each pattern by the comparator circuits 11 to 13 connected to the output terminal, and the display unit
At 14, the pass / fail judgment result is displayed.

Effect of the Invention As described above, according to the present invention, a faction pattern is set in advance, and the latch-up characteristic test can be automatically performed in synchronization with the pattern, so that a practical latch It is possible to obtain the effect that the up-resistance can be measured in a short time.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a latch-up characteristic test circuit according to the present invention, and FIG. 2 is a timing chart and waveform charts of respective parts. 1 ... Bias power supply, 2 ... Load resistance, 3 ... Driver pattern generation circuit, 4 ... Comparator pattern generation circuit, 5-7 ... Driver power supply section, 8-10 ... Comparator reference voltage generation circuit, 11- 13 …… Comparator circuit, 14
...... Display section, 15 ...... Pulse voltage generation circuit, 16 …… Pulse wave shaping circuit, 17 …… Pattern control section, 18 …… No test element

Claims (1)

[Scope of utility model registration request] 1. A latch-up characteristic test device for an integrated circuit, wherein a driver waveform output from a driver pattern generation circuit is applied to an input terminal of a device under test according to a preset pattern and a pulse voltage generation circuit is applied to a measurement terminal. Pulse voltage waveform that is output in synchronization with the driver waveform is applied, and the output waveform obtained by the comparator connected to the output terminal is judged for each pattern by the timing of the comparator trigger signal synchronized with the driver waveform. Latch-up characteristic test device characterized by the above.