JPS6132536A - Adjusting process of hybrid integrated circuit - Google Patents

Adjusting process of hybrid integrated circuit

Info

Publication number
JPS6132536A
JPS6132536A JP15293484A JP15293484A JPS6132536A JP S6132536 A JPS6132536 A JP S6132536A JP 15293484 A JP15293484 A JP 15293484A JP 15293484 A JP15293484 A JP 15293484A JP S6132536 A JPS6132536 A JP S6132536A
Authority
JP
Japan
Prior art keywords
voltage
adjustment
integrated circuit
hybrid integrated
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15293484A
Other languages
Japanese (ja)
Inventor
Masaki Kamiakutsu
上圷 政記
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15293484A priority Critical patent/JPS6132536A/en
Publication of JPS6132536A publication Critical patent/JPS6132536A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the member of outer terminals exclusively for adjustment by a method wherein a contact to be measured and an outer terminal taking no part in a circuit operation in adjustment are preliminarily connected to each other by a conductive connecting member such as a resistor or a conductor to be disconnected after finishing the adjustment so that the outer terminal may be utilized for normal circuit operation. CONSTITUTION:A contact N to be measured and an output terminal 6 are connected to each other by a resistor R2 while no signal is transmitted to an input terminal 2 and then the DC voltage of output terminal 6 (i.e. the voltage of contact N) and that of outer terminals 3, 4 are measured to adjust resistors RT1- RT4 by means of laser trimming process. After finishing this adjustment, the resistor R2 is disconnected by laser beams etc. so that the output terminals 6 may be utilized for normal circuit operation.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は混成集積回路装置の調整方法に関する。[Detailed description of the invention] [Field of application of the invention] The present invention relates to a method for adjusting a hybrid integrated circuit device.

〔発明の背景〕[Background of the invention]

混成集積回路装置は検査工程等忙おいて、その機能や電
気的特性等が仕様を満足するか否かの試験がなされ、仕
様を満足しないと調整が行なわれる。混成集積回路とも
なると、機能の増加にともなって試験項目も増加するた
め、試験。
Hybrid integrated circuit devices are busy with inspection processes, etc., and are tested to see if their functions, electrical characteristics, etc. satisfy specifications, and if they do not meet specifications, adjustments are made. When it comes to hybrid integrated circuits, the number of test items increases as the functionality increases, so testing is required.

の精度を低下させることなく検査手順や方法の簡素化が
必要となってくる。
There is a need to simplify testing procedures and methods without reducing accuracy.

ところが、従来、検査を容易にする目的で、予め混成集
積回路装置に試験専用の外部端子や配線を設ける方法が
採られているが、混成集積回路装置の大型化やコスト高
を招くので好ましい方法ではない。
However, in the past, a method has been adopted in which external terminals and wiring exclusively for testing have been provided in advance to the hybrid integrated circuit device for the purpose of facilitating inspection, but this method is not preferred as it increases the size and cost of the hybrid integrated circuit device. isn't it.

以下、かかる混成集積回路装置の従来の調整方法の一例
を具体的な回路構成をした混成集積回路装置にもとづい
て説明する。
An example of a conventional adjustment method for such a hybrid integrated circuit device will be described below based on a hybrid integrated circuit device having a specific circuit configuration.

第1図は従来の調整方法により調整される混成集積回路
装置の回路図であって、1はリミッタ回路を内蔵した増
幅器を構成する混成集積回路装置、2は入力端子、3.
4は外部端子、5は電源端子、6は出力端子、AMPl
 、AMP2は増幅回路、C1,C2は内部コンデンサ
、C51c4は外付はコンデンサ、Q+・はNPN型ト
ランジスタ、QzはPNP型トランジスタ、R1は抵抗
、RTl 、RT2 、RT3 、RT4は′調整用の
抵抗である。
FIG. 1 is a circuit diagram of a hybrid integrated circuit device adjusted by a conventional adjustment method, in which 1 is a hybrid integrated circuit device constituting an amplifier with a built-in limiter circuit, 2 is an input terminal, and 3.
4 is an external terminal, 5 is a power supply terminal, 6 is an output terminal, AMPL
, AMP2 is an amplifier circuit, C1, C2 are internal capacitors, C51c4 is an external capacitor, Q+ is an NPN transistor, Qz is a PNP transistor, R1 is a resistor, RTl, RT2, RT3, RT4 are adjustment resistors. It is.

この混成集積回路装置は、入力端子1に所定振幅以上の
信号が供給されると、トランジスタQ1.Q*および抵
抗RT1〜RT44Cよって検知され、クリップされた
信号を出力端子6に出力する。
In this hybrid integrated circuit device, when a signal having a predetermined amplitude or more is supplied to input terminal 1, transistor Q1. Q* and the resistors RT1 to RT44C detect and output the clipped signal to the output terminal 6.

すなわち、第2図に示す所定振幅以上の信号が供給され
ると、トランジスタQ2のベース端子電圧トそのベース
・エミッタ間電圧により上部レベルが振幅制限され、ト
ランジスタQ1のベース端子電圧とそのベース・エミッ
タ間電圧により下部レベルが振幅制限されるため、出力
端子6には第3図に示すクリップ波形の信号が出力され
る。
That is, when a signal with a predetermined amplitude or more shown in FIG. 2 is supplied, the upper level is amplitude limited by the base terminal voltage of transistor Q2 and its base-emitter voltage, and Since the amplitude of the lower level is limited by the voltage between the two, a signal having a clipped waveform shown in FIG. 3 is outputted to the output terminal 6.

なお、上部の電圧レベルv1は抵抗RT3とRT4の分
圧比を変え、下部の電圧レベルVzは抵抗RT1とRT
2の分圧比を変えてトランジスタQ1.Q2のベース端
子電圧を変えることにより調整ができる。
Note that the upper voltage level v1 changes the voltage division ratio of the resistors RT3 and RT4, and the lower voltage level Vz changes the voltage division ratio of the resistors RT1 and RT4.
By changing the voltage division ratio of transistor Q1. Adjustment can be made by changing the base terminal voltage of Q2.

次に、かかる構成の混成集積回路装置において、上部お
よび下部の電圧レベルV1* V2を共に等しい電圧V
oK設定する場合の調整方法を説明する。
Next, in the hybrid integrated circuit device having such a configuration, both the upper and lower voltage levels V1*V2 are set to the same voltage V
The adjustment method when setting OK will be explained.

従来の調整方法の一例として、入力端子1に大振幅の正
弦波信号を供給し、出力端子6から得られる出力信号の
上下の対象性を測定し、適宜、レーザトリミングによっ
て抵抗RT1〜RT4の抵抗値を調整し、電圧レベルを
設定する方法がある。
As an example of a conventional adjustment method, a large amplitude sine wave signal is supplied to the input terminal 1, the vertical symmetry of the output signal obtained from the output terminal 6 is measured, and the resistances of the resistors RT1 to RT4 are adjusted by laser trimming as appropriate. There are ways to adjust values and set voltage levels.

ところが、この方法によると出力信号を高速で測定する
ことのできる測定装置が必要と々る。
However, this method requires a measuring device that can measure the output signal at high speed.

その結果、測定装置が高価になって、混成集積回路装置
の価格の上昇を招き、周波数の高い信号の場合には、測
定装置の性能に応じて、調整精度が低下してしまう。
As a result, the measuring device becomes expensive, leading to an increase in the price of the hybrid integrated circuit device, and in the case of high-frequency signals, the adjustment accuracy decreases depending on the performance of the measuring device.

次に、上記調整方法の問題点を除いた従来の調整方法の
一例を説明する。
Next, an example of a conventional adjustment method that eliminates the problems of the above adjustment method will be described.

第1図において、外部端子3の電圧(すなわちトランジ
スタQ1のべ、−入端子電圧)をVSS外部端子4の電
圧(すなわちトランジスタQ2のベース端子電圧)をv
4、トランジスタQs、(bのエミッタ端子の接続点N
の電圧をVN%  )ランジスタQ1.Q2のベースφ
エミッタ間電圧をVni+(中0.7 Vとするkらば
、上部の電圧レベルV、と下部の電圧レベルV2は次式
で示される。
In FIG. 1, the voltage at external terminal 3 (i.e., the voltage at the base terminal of transistor Q1) is set to VSS, and the voltage at external terminal 4 (i.e., the base terminal voltage of transistor Q2) is set to VSS.
4. Transistor Qs, (connection point N of emitter terminal of b
voltage of VN%) transistor Q1. Base φ of Q2
If the emitter voltage is Vni+ (0.7 V), the upper voltage level V and the lower voltage level V2 are expressed by the following equation.

Vs= (V4 + VBI )  VN  ・・・・
・・・・・・・・・・・(1)■!= VN −(Vs
 −VBB)  ……−−(2)そして、上記式0)の
関係は第4図に示す特性図で示すことができ、上記式(
2)の関係は第5図に示す特性図で示すことができる。
Vs= (V4 + VBI) VN...
・・・・・・・・・・・・(1)■! = VN − (Vs
-VBB)...---(2)The relationship of the above formula 0) can be shown in the characteristic diagram shown in Figure 4, and the above formula (
The relationship 2) can be shown in the characteristic diagram shown in FIG.

以上釦説明したことから、外部端子6.4の電圧と接続
点Nの電圧を測定し、上記の関係式(1) 、 (2)
を用いて電圧レベルv、 t V、が共忙電圧V。
Based on the button explanation above, measure the voltage at external terminal 6.4 and the voltage at connection point N, and use the above relational expressions (1) and (2).
Using , the voltage level v, t V, is the busy voltage V.

となるように抵抗RTi〜RT4をレーザトリミングに
よって調整することができる。この方法によれば、直流
電圧を測定することにより調整できるので、高精度の調
整が容易であり、測定装置も安価となる。
The resistors RTi to RT4 can be adjusted by laser trimming so that According to this method, since adjustment can be performed by measuring the DC voltage, highly accurate adjustment is easy and the measuring device is also inexpensive.

しかしながら、この調整方法を実施するためには予め、
接続点Nに接続する測定用の外部端子を設け、その外部
端子延よって接続点Nの電圧を測定するようkする必要
があることから、混成集積回路装置が大形になったり、
測定にしか使用されない外部端子を設けることから不経
済であった。
However, in order to implement this adjustment method, in advance,
Since it is necessary to provide an external terminal for measurement connected to the connection point N and extend the external terminal to measure the voltage at the connection point N, the hybrid integrated circuit device becomes large and
This was uneconomical because it required external terminals that were only used for measurements.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、測定用外部端子を低減可能とした混成
集積回路の調整方法の提供にある。
An object of the present invention is to provide a method for adjusting a hybrid integrated circuit that allows the number of external terminals for measurement to be reduced.

〔発明の概要〕[Summary of the invention]

との目的を達成するため、本発明は測定すべき接点と、
調整時には回路動作に何んら関与しない外部端子とを、
抵抗体又は導体などの導電性の接続部材により予め接続
し、該外部端子を介して該接i点の測定を行うことによ
り調整し、調整の終了の後は前記接続部材を切断して、
前記外部端子を通常の回路動作に使用するようにした点
を特徴とする。
In order to achieve the object, the present invention includes a contact point to be measured;
When making adjustments, connect external terminals that do not have any influence on circuit operation.
Connect in advance with a conductive connecting member such as a resistor or conductor, adjust by measuring the contact point via the external terminal, and after the adjustment is completed, disconnect the connecting member,
The present invention is characterized in that the external terminal is used for normal circuit operation.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を図面とともに説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第6図は、本発明による混成集積回路装置の調整方法の
一実施例を説明するための回路図であって、R2は抵抗
体であり、第1図に対応する部分には同一符号をつけて
いる。
FIG. 6 is a circuit diagram for explaining an embodiment of the method for adjusting a hybrid integrated circuit device according to the present invention, in which R2 is a resistor, and parts corresponding to those in FIG. 1 are given the same reference numerals. ing.

この実施例では調整時には、出力端子6は回路動作に関
与しないことから使用されないので測定すべき接点Nと
出力端子6とを抵抗体82忙よって接続し、接点Nの測
定を出力端子6によって行゛なりようにしである。
In this embodiment, during adjustment, the output terminal 6 is not used because it is not involved in the circuit operation, so the contact N to be measured and the output terminal 6 are connected through a resistor 82, and the measurement of the contact N is performed using the output terminal 6. ``That's how it is.''

前記従来例(第1図)で説明したように、入力端子2に
は信号を供給せず、出力端子6の直流電圧(すなわち接
点Nの電圧)と外部端子3゜4の直流電圧を測定し、上
記式θ) 、 (2)に基づいて、所定の電圧振幅でク
リップさせるための上部、下部レベルVB + V2を
設定するように、抵抗RT1〜RT4をレーザトリミン
グによって調整する。
As explained in the conventional example (Fig. 1), no signal is supplied to input terminal 2, and the DC voltage at output terminal 6 (that is, the voltage at contact N) and the DC voltage at external terminals 3 and 4 are measured. , the above equation θ), (2), the resistors RT1 to RT4 are adjusted by laser trimming so as to set the upper and lower levels VB + V2 for clipping at a predetermined voltage amplitude.

この調整が終了すると、抵抗体R2をレーザ等で切断し
、出力端子6を通常の回路動作に使用できるようにする
When this adjustment is completed, the resistor R2 is cut by a laser or the like, so that the output terminal 6 can be used for normal circuit operation.

第7図と第8図は、この実施例で用いられた抵抗体R2
の配線パターンを示し、第6図に対応する部分には同一
符号をつけている。
Figures 7 and 8 show the resistor R2 used in this example.
The wiring pattern shown in FIG. 6 is shown, and parts corresponding to those in FIG.

第7図において、測定すべき接点Nと出力端子6との間
が抵抗体R2で接続され、接点Nの電圧は出力端子6に
よって測定ができる。第8図は、調整終了稜忙抵抗体R
2を切断した状態を示し、出力端子6は増幅回路AMP
2からの信号を出力するようになる。
In FIG. 7, the contact N to be measured and the output terminal 6 are connected through a resistor R2, and the voltage at the contact N can be measured by the output terminal 6. Figure 8 shows the adjustment completed ridge resistor R.
2 is disconnected, and the output terminal 6 is the amplifier circuit AMP.
The signal from 2 will be output.

とのように、この実施例では直流電圧を調整すればよく
、簡単な測定手段を用いて、高い精度の回路調整ができ
、この際、直流電圧を測定するための端子として回路動
作に必要な外部端子を用いることができる。
In this example, it is only necessary to adjust the DC voltage, and the circuit can be adjusted with high precision using a simple measuring means. External terminals can be used.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば調整専用の外部端
子の数を少なくして、複雑かつ高価な調整手段を必要と
しない高精度の回路調整を可能とし、よって小形で安価
なかつ精度よく動作する混成集積回路を得ることができ
る。
As explained above, according to the present invention, it is possible to reduce the number of external terminals dedicated to adjustment and perform highly accurate circuit adjustment without requiring complicated and expensive adjustment means. A hybrid integrated circuit can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の調整方法に係る混成集積回路装置を示す
回路図、第2′図は入力信号の波形図、第3図は出力信
号の特性を示す波形図、第4図と第5図はクリップ電圧
レベルの特性を示ス特性図、第6図は本発明による混成
集積回路装量の調整方法の一実施例に係る混成集積回路
装置を示す回路図、第7図は第6図の混成集積回路装置
の配線パターンを示す平面図、第8図は第6図の混成集
積回路装置の調整終了後の配線パターンを示す平面図で
ある。 3.4・・・外部端子、  6・・・出力端子、N・・
・接点、     R2・・・抵抗体。 第1 図 箋2図       第3図 篤今図    第5図 V+v3
Figure 1 is a circuit diagram showing a hybrid integrated circuit device according to the conventional adjustment method, Figure 2' is a waveform diagram of the input signal, Figure 3 is a waveform diagram showing the characteristics of the output signal, and Figures 4 and 5. 6 is a characteristic diagram showing the characteristics of the clip voltage level, FIG. 6 is a circuit diagram showing a hybrid integrated circuit device according to an embodiment of the method for adjusting the amount of hybrid integrated circuit according to the present invention, and FIG. FIG. 8 is a plan view showing the wiring pattern of the hybrid integrated circuit device of FIG. 6 after adjustment. 3.4...External terminal, 6...Output terminal, N...
・Contact, R2...Resistor. 1. Illustration 2. Figure 3. Atsushi. Figure 5. V+v3.

Claims (1)

【特許請求の範囲】[Claims] 1.調整時には回路動作に関与しない外部端子と、調整
時に測定されるべき接点とを接続する導電性の接続部材
を設け、該外部端子によって該接点の電圧測定を行なっ
て調整を行ない、調整の終了後に該接続部材を切断する
ことにより、測定用外部端子が不要となったことを特徴
とする混成集積回路装置の調整方法。
1. During adjustment, a conductive connecting member is provided to connect an external terminal that is not involved in circuit operation and a contact to be measured during adjustment, and the external terminal measures the voltage of the contact to perform adjustment. A method for adjusting a hybrid integrated circuit device, characterized in that by cutting the connecting member, an external terminal for measurement is no longer necessary.
JP15293484A 1984-07-25 1984-07-25 Adjusting process of hybrid integrated circuit Pending JPS6132536A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15293484A JPS6132536A (en) 1984-07-25 1984-07-25 Adjusting process of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15293484A JPS6132536A (en) 1984-07-25 1984-07-25 Adjusting process of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS6132536A true JPS6132536A (en) 1986-02-15

Family

ID=15551336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15293484A Pending JPS6132536A (en) 1984-07-25 1984-07-25 Adjusting process of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS6132536A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01303384A (en) * 1988-05-30 1989-12-07 Tokyo Gas Co Ltd Emergency cutoff valve
JPH0580130A (en) * 1991-09-20 1993-04-02 Nec Corp Semiconductor integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01303384A (en) * 1988-05-30 1989-12-07 Tokyo Gas Co Ltd Emergency cutoff valve
JPH0580130A (en) * 1991-09-20 1993-04-02 Nec Corp Semiconductor integrated circuit

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