JPS63234170A - Characteristic measuring method for analog comparator - Google Patents
Characteristic measuring method for analog comparatorInfo
- Publication number
- JPS63234170A JPS63234170A JP62068401A JP6840187A JPS63234170A JP S63234170 A JPS63234170 A JP S63234170A JP 62068401 A JP62068401 A JP 62068401A JP 6840187 A JP6840187 A JP 6840187A JP S63234170 A JPS63234170 A JP S63234170A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- input
- analog comparator
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 5
- 238000010586 diagram Methods 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はヒステリシス特性を持たせたアナログコンパレ
ータとフリップフロップ回路を一体化内蔵させた集積回
路の入力ヒステリシス幅の測定方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for measuring the input hysteresis width of an integrated circuit in which an analog comparator with hysteresis characteristics and a flip-flop circuit are integrated.
従来の技術
ヒステリシスを持たせたアナログコンパレータの入出力
特性の測定回路例を第４図に、入出力波形図を第５図に
示す。第５図から、アナログコンパレータ単体の入力ヒ
ステリシス幅を求めることができる。An example of a circuit for measuring the input/output characteristics of a conventional analog comparator with hysteresis is shown in FIG. 4, and an input/output waveform diagram is shown in FIG. From FIG. 5, the input hysteresis width of a single analog comparator can be determined.
発明が解決しようとする問題点
しかし、アナログコンパレータとフリップフロップが一
体化された集積回路では、従来の技術では単純には対応
できない。集積回路化された場合は、身然、内部配線さ
れて各ブロック毎の入出力端子は外部へ配線されていな
い場合が多く、結局は同集積回路自身の入力端子、出力
端子を活用してアナログ入力のヒステリシス幅の測定が
必要となる。Problems to be Solved by the Invention However, conventional techniques cannot simply solve the problem with an integrated circuit in which an analog comparator and a flip-flop are integrated. In the case of an integrated circuit, it is natural that the input and output terminals of each block are wired internally and are not wired externally.In the end, analog It is necessary to measure the input hysteresis width.
問題点を解決するための手段
本発明は、上記問題点を解決するもので、アナログコン
パレータの出力側にフリップフロップ回路を結合し、前
記アナログコンパレータの入力部に高い周波数信号と低
い周波数信号との混合信号を印加し、前記フリップフロ
ップ回路の出力信号を同フリップフロップ回路の制御信
号入力部に帰這入力して、前記アナログコンパレータの
入力特性を検知するアナログコンパレータの特性測定方
法である。Means for Solving the Problems The present invention solves the above problems by coupling a flip-flop circuit to the output side of an analog comparator, and connecting a high frequency signal and a low frequency signal to the input section of the analog comparator. This is a method for measuring characteristics of an analog comparator, in which input characteristics of the analog comparator are detected by applying a mixed signal and inputting an output signal of the flip-flop circuit back to a control signal input section of the flip-flop circuit.
作用
本発明によると、低い周波数（正弦波）入力信号源の周
波数ｊＬｓ高い周波数（正弦波）入力信号源の周波数ｊ
Ｈとし、ｉＨ＞ｆしかつ、低い周波数ｆＬの入力信号レ
ベルを被試験アナログコンパレータのオン／オフしきい
値レベルを十分にカバーするように設定することにより
、アナログコンパレータの入力ヒステリシス幅を検知す
ることができる。According to the invention, the frequency of the low frequency (sinusoidal) input signal source jLs The frequency of the high frequency (sinusoidal) input signal source j
The input hysteresis width of the analog comparator is detected by setting the input signal level of low frequency fL to sufficiently cover the on/off threshold level of the analog comparator under test. be able to.
実施例
第１図は本発明の実施例で使用した測定回路であり、ま
ず高い周波数入力信号源６の電圧レベルを零にする。ア
ナログコンパレータ１．モノマルチ回路２およびＲ／Ｓ
フリップフロップ回路３を集積化した被試験回路４の出
力端子Ｃの出力信号をオシロスコープ１１１周波数カウ
ンタ１０で観測、測定すると、第２図のように、低い周
波数入力信号源５の交流入力信号ｆＬと同期し、デジタ
ル出力の周期Ｔは低い周波数信号周波数ＩＬと一致する
。第１図示の被試験回路４の出力パルス信号のパルス幅
ｔｌはディレー回路８の遅延設定時間となる。次に、高
い周波数入力信号源６の電圧レベルを零から次第に増加
させてゆ（と、被試験回路４の出力端子Ｃの出力パルス
周期Ｔが低い周波数入力信号源５０周波数ｆｔから２ｆ
ｔ−３ｆｔ・・・・・・η・ｆＬへ・と変ってゆく。出
力パルス周期Ｔがｆｔから２ｆＬへ変る時の高い周波数
入力信号源６の電圧レベルをオシロスコープ１２で観測
、測定することで、被試験回路４のアナログコンパレー
タ１の入力ヒステリシス幅を知ることができる。アナロ
グ加算器７の加算利得をＯｄＢに設定しておけば、高い
周波数入力信号源６の電圧レベル（ピーク値ｍＶｐ−ｐ
）が入力ヒステリシス幅に換算されることは当然である
。この時の、被試験回路４の出力波形図を第３図に示す
。第３図の第１パルスと第２パルスとの間の時間ｔ２は
モノマルチ回路９のパルス幅時間である。このモノマル
チ回路９のパルス幅は高い周波数ｆＨ周期の３〜５周期
時間が適当である。Embodiment FIG. 1 shows a measuring circuit used in an embodiment of the present invention, in which the voltage level of the high frequency input signal source 6 is first brought to zero. Analog comparator 1. Mono multi circuit 2 and R/S
When the output signal of the output terminal C of the circuit under test 4 in which the flip-flop circuit 3 is integrated is observed and measured by the oscilloscope 111 and the frequency counter 10, as shown in FIG. synchronously, the period T of the digital output coincides with the low frequency signal frequency IL. The pulse width tl of the output pulse signal of the circuit under test 4 shown in FIG. 1 is the delay setting time of the delay circuit 8. Next, the voltage level of the high frequency input signal source 6 is gradually increased from zero (and the output pulse period T of the output terminal C of the circuit under test 4 is increased from the frequency of the low frequency input signal source 50 to 2f).
t-3ft...changes to η・fL. By observing and measuring the voltage level of the high frequency input signal source 6 with the oscilloscope 12 when the output pulse period T changes from ft to 2fL, it is possible to know the input hysteresis width of the analog comparator 1 of the circuit under test 4. If the addition gain of the analog adder 7 is set to OdB, the voltage level of the high frequency input signal source 6 (peak value mVp-p
) is naturally converted into the input hysteresis width. The output waveform diagram of the circuit under test 4 at this time is shown in FIG. The time t2 between the first pulse and the second pulse in FIG. 3 is the pulse width time of the monomulti circuit 9. The pulse width of this monomulti circuit 9 is suitably 3 to 5 cycles of the high frequency fH cycle.
発明の効果
以上述べた手法を用い、２つの交流信号周波数比ｉＨ／
ｉＬを大きくするほど高精度でヒステリシス幅を測定す
ることができる。また、簡易な回路構成で自動計測化も
極めて容易である。Effects of the Invention Using the method described above, two AC signal frequency ratios iH/
The larger iL is, the more accurately the hysteresis width can be measured. Furthermore, automatic measurement is extremely easy due to the simple circuit configuration.
第１図 は本発明実施例におけるヒステリシス幅測定に
用いた試験回路を示すブロック図、第２図はヒステリシ
ス幅に達しない入力信号状態下での入出力信号波形図、
第３図はヒステリシス幅調節、設定時の入出力信号波形
図、第４図はヒステリシスを有するアナログコンパレー
タとフリップフロップ回路等が一体化されたアナログレ
ベル検出回路側のブロック図、第５図はヒステリシスを
有するアナログコンパレータの従来特性図である。
１・・・・・・アナログコンパレータ、２・・・・・・
モノマルチ回路、３・・・・・・Ｒ／Ｓフリップフロッ
プ回路、４・・・・・・被試験集積回路、５・・・・・
・低い周波数入力信号源、６・・・・・・高い周波数入
力信号源、７・・・・・・アナログ加算回路、８・・・
・・・ディレー回路、９・・・・・・モノマルチ回路、
１０・・・・・・周波数カウンタ、１１．１２・・・・
・・オシロスコープ。
代理人の氏名 弁理士 中尾敏男 ほか１名第２図
に−丁一一一一ゆ
第３図
／−−一交飛億号
Ｚ−＊ｔＵ灸ア六ｐグコンノルータ
１４ 図 ３−一一オシ＝スコー
７゛第５図
Ｅ 入カヒステリシヌナ昌FIG. 1 is a block diagram showing a test circuit used for measuring the hysteresis width in the embodiment of the present invention, and FIG. 2 is an input/output signal waveform diagram under an input signal condition that does not reach the hysteresis width.
Figure 3 is a diagram of input/output signal waveforms during hysteresis width adjustment and setting. Figure 4 is a block diagram of an analog level detection circuit that integrates an analog comparator with hysteresis, a flip-flop circuit, etc., and Figure 5 shows hysteresis. FIG. 3 is a conventional characteristic diagram of an analog comparator having the following characteristics. 1...Analog comparator, 2...
Mono multi circuit, 3... R/S flip-flop circuit, 4... Integrated circuit under test, 5...
・Low frequency input signal source, 6... High frequency input signal source, 7... Analog addition circuit, 8...
...Delay circuit, 9...Mono multi circuit,
10... Frequency counter, 11.12...
··oscilloscope. Name of agent: Patent attorney Toshio Nakao and one other person Figure 2-11-1-1 Figure 3/--Ikko Hibigo Z-*tU Moxibustion A6P Gukon Router 14 Figure 3-11Oshi= Squaw 7゛Fig. 5E Entering hysteresis
Claims (1)
を結合し、前記アナログコンパレータの入力部に高い周
波数信号と低い周波数信号との混合信号を印加し、前記
フリップフロップ回路の出力信号を同フリップフロップ
回路の制御信号入力部に帰還入力して、前期アナログコ
ンパレータの入力特性を検知するアナログコンパレータ
の特性測定方法。A flip-flop circuit is coupled to the output side of the analog comparator, a mixed signal of a high frequency signal and a low frequency signal is applied to the input part of the analog comparator, and the output signal of the flip-flop circuit is used as a control signal of the flip-flop circuit. A method for measuring the characteristics of an analog comparator that detects the input characteristics of the earlier analog comparator by inputting feedback to the input section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62068401A JPH0746126B2 (en) | 1987-03-23 | 1987-03-23 | Method for measuring the characteristics of analog comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62068401A JPH0746126B2 (en) | 1987-03-23 | 1987-03-23 | Method for measuring the characteristics of analog comparator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63234170A true JPS63234170A (en) | 1988-09-29 |
| JPH0746126B2 JPH0746126B2 (en) | 1995-05-17 |
Family
ID=13372631
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62068401A Expired - Lifetime JPH0746126B2 (en) | 1987-03-23 | 1987-03-23 | Method for measuring the characteristics of analog comparator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0746126B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7035749B2 (en) | 2001-11-26 | 2006-04-25 | Koninklijke Philips Electronics, N.V. | Test machine for testing an integrated circuit with a comparator |
-
1987
- 1987-03-23 JP JP62068401A patent/JPH0746126B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7035749B2 (en) | 2001-11-26 | 2006-04-25 | Koninklijke Philips Electronics, N.V. | Test machine for testing an integrated circuit with a comparator |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0746126B2 (en) | 1995-05-17 |
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