JPH0171681U - - Google Patents
Info
- Publication number
- JPH0171681U JPH0171681U JP1987166972U JP16697287U JPH0171681U JP H0171681 U JPH0171681 U JP H0171681U JP 1987166972 U JP1987166972 U JP 1987166972U JP 16697287 U JP16697287 U JP 16697287U JP H0171681 U JPH0171681 U JP H0171681U
- Authority
- JP
- Japan
- Prior art keywords
- output
- pattern
- formatter
- pulses
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000630 rising effect Effects 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 7
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第１図はこの考案の一実施例を示すブロツク図
、第２図はこの考案に用いるジツタ除去装置の一
例を説明するためのブロツク図、第３図はこの考
案の変形実施例を示すブロツク図、第４図は従来
のＩＣ試験装置の概要を説明するためのブロツク
図、第５図は従来のＩＣ試験装置の欠点を説明す
るための波形図、第６図はこのタイミング信号発
生器の構造を説明するためのブロツク図、第７図
はタイミング信号発生器の動作を説明するための
波形図、第８図は従来の技術の欠点を説明するた
めの波形図である。
Fig. 1 is a block diagram showing an embodiment of this invention, Fig. 2 is a block diagram illustrating an example of a jitter removal device used in this invention, and Fig. 3 is a block diagram showing a modified embodiment of this invention. , Fig. 4 is a block diagram for explaining the outline of the conventional IC test equipment, Fig. 5 is a waveform diagram for explaining the drawbacks of the conventional IC test equipment, and Fig. 6 is the structure of this timing signal generator. FIG. 7 is a waveform diagram to explain the operation of the timing signal generator, and FIG. 8 is a waveform diagram to explain the drawbacks of the conventional technology.
Claims (1)
し、この複数の遅延素子を切替て使用することに
よつて可変分周器から一定の周期で出力されるパ
ルスを順次遅延時間を累積させて遅延させパルス
の周波数を微細に変化させて設定できるようにし
たタイミング発生器と、 Ｂ このタイミング発生器から出力されるタイミ
ング信号とパターン発生器から出力されるパター
ンデータとによつてパターン信号を生成するフオ
ーマツタと、 Ｃ このフオーマツタから出力されるパターン信
号が与えられ、パターン信号の立上り及び立下り
に同期したパルスに変換するパルサと、 Ｄ このパルサから出力されるパルスによつて被
試験素子に与える信号を生成するピンドライバと
、 Ｅ 上記フオーマツタの出力側に介挿したジツタ
除去装置と、 を具備して成るＩＣ試験装置。[Claims for Utility Model Registration] A. Pulses that are provided with a plurality of delay elements having different delay times and are output at a constant period from a variable frequency divider by switching and using the plurality of delay elements. A timing generator that can be set by sequentially accumulating the delay time and minutely changing the frequency of the pulse, and (B) a timing signal output from this timing generator and pattern data output from a pattern generator. A formatter that generates a pattern signal by C; a pulser that receives the pattern signal output from this formatter and converts it into pulses synchronized with the rising and falling edges of the pattern signal; D pulses output from this pulser An IC testing device comprising: a pin driver that generates a signal to be applied to an element under test by a pin driver; and a jitter removal device inserted on the output side of the formatter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16697287U JP2512950Y2 (en) | 1987-10-30 | 1987-10-30 | IC test equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16697287U JP2512950Y2 (en) | 1987-10-30 | 1987-10-30 | IC test equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0171681U true JPH0171681U (en) | 1989-05-12 |
| JP2512950Y2 JP2512950Y2 (en) | 1996-10-02 |
Family
ID=31454843
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16697287U Expired - Lifetime JP2512950Y2 (en) | 1987-10-30 | 1987-10-30 | IC test equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2512950Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005091108A (en) * | 2003-09-16 | 2005-04-07 | Advantest Corp | Jitter generator and testing apparatus |
-
1987
- 1987-10-30 JP JP16697287U patent/JP2512950Y2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005091108A (en) * | 2003-09-16 | 2005-04-07 | Advantest Corp | Jitter generator and testing apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2512950Y2 (en) | 1996-10-02 |
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