SU1479900A1 - Method for testing logic circuits - Google Patents

Abstract

The invention relates to instrumentation technology and can be used in diagnostic devices for logic circuits. The purpose of the invention is to extend the scope of application of the method to logical circuits with an arbitrary internal structure. The pseudo-random combination generator 1 generates pulses with a duration equal to the delay time of the elements of logic circuits. Amplifier 2 with three states provides pseudo-random combinations to all the outputs of the logic circuit 17. The pulses given by the single vibrator 7 prevent the effects of pseudo-random combinations on the input of the amplifier 3. Amplifier 3 amplifies the pulses delayed by a time longer than the maximum delay time of the logic circuit elements , which are fixed by RS - triggers 4. The conclusions of the logic circuit, according to which delayed pulses are detected, are recognized as output, and the conclusions, according to which there are no such pulses, - as input. 2 Il.

Description

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The invention relates to a control measurement technology and can be used to determine the inputs and outputs of logic circuits, as well as in monitoring and diagnostic devices for monitoring logic circuits with unknown, the arrangement of inputs and outputs.

The purpose of the invention is to expand the scope of the proposed method by allowing the definition of the inputs and outputs of a wide class of logic circuits with an arbitrary internal logic structure.

FIG. 1 shows a block diagram of a device implementing the proposed method; in fig. 2 - timing diagrams explaining the method. Timing diagrams a, e, g, h, and (Fig. 2) clarify the method, and in conjunction with diagrams b, c, d, g clarify the operation of the device that implements the method.

FIG. 2 denotes: a - transient formation of a pulse at the input of an element, (- element activation time, U AMCL - element deactivation time, Vcd in (, (Cm, C Zy - element delay time), e, f, h, and - signals of 2 n pseudo-random combinations, fed to a logic circuit having n outputs (open signals), while the presence on the outputs of 1.3 and n signals delayed relative to the falling edges of the acting pulses (shaded signals on diagrams e, 3, and) These indicate that pins 1.3 and p are outputs.

The method is based on the fact that the signal at the output of any logic element appears and is removed with some delay relative to the input signal, determined by the speed of this element.

Therefore, the fundamental condition for distinguishing the output of a logic element from an input is the presence of a signal at the output of an element delayed relative to the trailing edge of the acting signals.

The method is carried out as follows.

Pseudo-random combinations of signals are formed, the width of which is equal to the number of inputs-outputs of the circuit under study and in turn serves them to the inputs-outputs of the circuit under study.

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five

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five

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The duration of the acting pulses is chosen equal to the maximum delay time of the elements on which the logical scheme is built. At each influencing combination of signals at the outputs of the logical circuit under study, signals detained relative to the falling edges of the acting pulses are recorded. Perform a complete search of pseudo-random combinations.

Consider the output of a logic circuit as its output, if at least with one pseudo-random combination of signals acting on it there is a signal delayed relative to the trailing edge of the acting pulse. Consider the output of the circuit as its input, if no signal is present on any of the possible pseudo-random combinations of signals that is delayed relative to the trailing edge of the acting pulse.

A device implementing the method comprises a generator of 1 pseudo-random combinations, a first n-channel amplifier 2 with three states, a second n-channel amplifier 3 with three states, a group of n RS-flip-flops 4, a generator of 5 clock pulses, and the element I 6, one-shot 7, frequency divider 8, display unit 9, initial reset button 10, control input

11 without inversion of the first amplifier 2

in three states, control input

12 with inversion of the second amplifier 3

with three states, clock input 13 of a pseudo-random combination generator, installation inputs 14-16, respectively, of the generator 1 of pseudo-random combinations, groups of n RS-flip-flops 4 and frequency divider 8, and the logic circuit 17 having n outputs.

The device that implements the method works as follows.

Pressing the button 10 sets the generator 1 of pseudo-random combinations, the group of RS-flip-flops 4, and the divider 8 of the frequency to the zero state (the Start signal on diagram 26). After the button 10 is lowered, the clock pulses (diagram 2d) from the generator of 5 clock pulses through the element 6 receive the clock input 13 of the generator 1 of pseudo-random combinations and to the one-shot 7. With the arrival of each clock pulse the generator 1

pseudo-random combinations form an n-bit (n is the number of outputs

the scheme under study) combination of sigka

and outputs it to the inputs of the first amplifier 2 in three states. A single vibrator 8 forms short strobe pulses (diagram 2d), equal to the maximum switching time of the elements of the circuit under study, arriving at the control inputs 11 and 12, respectively, of the first 2 and second 3 amplifiers with three states. At the same time, signals of a pseudo-random combination present at the inputs of the first amplifier 2 with three states for a short time equal to the pulse width of the strobe appear at its outputs and will affect the logic circuit 17 (gram 2e, 2g, 2z and 2i). At the same time, a strobe pulse prohibits reception of signals by the second amplifier 3 with three states.

At the end of the strobe pulse, the signals from the outputs of the first amplifier 2 are removed, and the second amplifier 3 starts receiving signals that are delayed relative to the falling edge of the strobe pulse, which are the output, Q signals of the logic being studied. These signals are sent to the S-inputs of the corresponding triggers in the group n of RS-flip-flops 4. Thus, if at least one pseudo-random combination of signals a signal delayed relative to the falling edge of the strobe pulse is present at any output, the corresponding trigger will be set to one and the corresponding indicator in the display unit 9 will be lit.

The frequency divider 8 has a division factor of 2P. Thus image-40

After 2 clocks, element 6 also prohibits the output of clock pulses to the generator 1 of pseudo-random combinations, as a result of which the one-oscillator 7 stops the operation of the device (the stop signal in the diagram 2c).

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The signals taken from the outputs of the second amplifier 3 with three states, which are the output signals of the logic circuit under study, can be used directly to monitor and diagnose the circuit.

The main condition for the implementation of the proposed method by the device is the presence in the device of high-speed microcircuits, in which the delay time is several times shorter than that of the microcircuits on which the studied circuit is built.

Claims (1)

Invention Formula A method of controlling logic circuits, which consists in supplying a nominal supply voltage to a logic circuit, impulses are applied to each circuit output, characterized in that, in order to expand the field of application by making it possible to define inputs and outputs of logic circuits with an arbitrary internal circuit. logical structure, the pulse effect is formed in the form of pseudo-random code combinations of pulses, the duration of which is equal to the maximum delay time of the logic circuit, the number of The pseudo-random code combination scans are chosen equal to the number of outputs of the logic circuit, after each pulse action the electrical signals are recorded on the logic circuit's outputs, consider the logic circuit output to be its output, if at one of the possible pulse effects an electrical signal is detected at this output, delayed relative to the rear front of the pulse action, consider the output of the logic circuit as an input, if none of the possible pulse effects at the output Stegeman electrical signal delayed relative to the trailing edge of pulse exposure. Kamb. 1 COMM.1 COMM. Nom. 2-1 Nom8.2 p Phage.2