JPH01152272U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of an IC testing device according to this invention, and FIG. 2 is a block diagram showing a conventional IC testing device.

Claims (1)

[Claim for Utility Model Registration] A timing generator is operated by a start signal from a pattern generator, and multiple timing signals generated from the timing generator are assigned to each channel by a clock selector. Using a timing signal, the pattern from the pattern generator is shaped into a waveform and supplied to the IC element under test, and the output of the IC element under test is compared with the expected value using a comparator to determine whether it is good or bad. In an IC testing apparatus for performing IC testing, a selector for selecting and extracting a timing signal from the timing generator; a variable delay means for delaying the output of the selector and applying it to an input terminal of the clock selector; means for changing the delay amount of the variable delay means in a fixed direction depending on whether the output of the comparator is good or bad each time a test pattern is generated; good,
An IC testing device comprising: a memory into which the delay amount of the variable delay means is written when the output of the comparator is good; and an address pointer that updates an address to be written in the memory when the output of the comparator is good or bad.