JPH0347615B2 - - Google Patents
Info
- Publication number
- JPH0347615B2 JPH0347615B2 JP56009077A JP907781A JPH0347615B2 JP H0347615 B2 JPH0347615 B2 JP H0347615B2 JP 56009077 A JP56009077 A JP 56009077A JP 907781 A JP907781 A JP 907781A JP H0347615 B2 JPH0347615 B2 JP H0347615B2
- Authority
- JP
- Japan
- Prior art keywords
- clock
- clock pulse
- pulse
- supply
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000012544 monitoring process Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 2
- 230000010355 oscillation Effects 0.000 claims description 2
- 238000012545 processing Methods 0.000 claims description 2
- 230000002159 abnormal effect Effects 0.000 claims 1
- 230000005856 abnormality Effects 0.000 claims 1
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 11
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 11
- 238000010586 diagram Methods 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56009077A JPS57123748A (en) | 1981-01-26 | 1981-01-26 | Clock supply system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56009077A JPS57123748A (en) | 1981-01-26 | 1981-01-26 | Clock supply system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57123748A JPS57123748A (en) | 1982-08-02 |
JPH0347615B2 true JPH0347615B2 (ko) | 1991-07-19 |
Family
ID=11710546
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56009077A Granted JPS57123748A (en) | 1981-01-26 | 1981-01-26 | Clock supply system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57123748A (ko) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS636934A (ja) * | 1986-06-26 | 1988-01-12 | Nec Corp | 網同期方式 |
JPH086854A (ja) * | 1993-12-23 | 1996-01-12 | Unisys Corp | アウトボードファイルキャッシュ外部処理コンプレックス |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5028146A (ko) * | 1973-07-19 | 1975-03-22 |
-
1981
- 1981-01-26 JP JP56009077A patent/JPS57123748A/ja active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5028146A (ko) * | 1973-07-19 | 1975-03-22 |
Also Published As
Publication number | Publication date |
---|---|
JPS57123748A (en) | 1982-08-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6204732B1 (en) | Apparatus for clock signal distribution, with transparent switching capability between two clock distribution units | |
US6707828B1 (en) | Synchronization of a network element in a synchronous digital communications network | |
KR100882391B1 (ko) | 심리스 클록 | |
CA2125450C (en) | Method and apparatus for switching of duplexed clock system | |
JPH0347615B2 (ko) | ||
JP4661509B2 (ja) | 伝送装置 | |
KR100328757B1 (ko) | 전송시스템의 클럭신호 전환에 의한 오류방지 장치 | |
EP0800136B1 (en) | Fault tolerant clock signal source for triplicated data processing system | |
KR100406863B1 (ko) | 다중컴퓨터 시스템의 클럭 생성장치 | |
US6999546B2 (en) | System and method for timing references for line interfaces | |
JP3034388B2 (ja) | 位相同期発振器 | |
KR100222406B1 (ko) | 이중화 구조를 가지는 클럭 동기 장치 및 이중화 구현 방법 | |
KR100328761B1 (ko) | 광통신 시스템의 시스템 클럭 유니트 스위칭 장치 | |
US7468991B2 (en) | Methods and devices for synchronizing the timing of logic cards in a packet switching system without data loss | |
KR100343929B1 (ko) | 기준 클럭 감시 장치 | |
JPS6226605B2 (ko) | ||
JPS63228821A (ja) | 位相同期ル−プの保護回路 | |
JPH04291819A (ja) | 位相同期ループ回路及び基準信号選択回路 | |
JP3160904B2 (ja) | 位相同期発振回路装置 | |
JP2000049841A (ja) | 通信システム | |
KR920005924B1 (ko) | 교환기 노드간의 클럭동기회로 | |
JP2001345789A (ja) | 網同期装置用周波数監視回路 | |
JP2972463B2 (ja) | 同期信号供給装置 | |
KR200185362Y1 (ko) | 시스템 클럭 이중화 장치 | |
JPH07177025A (ja) | 二重化位相同期方式 |