JPH0347542B2 - - Google Patents

Info

Publication number
JPH0347542B2
JPH0347542B2 JP59101991A JP10199184A JPH0347542B2 JP H0347542 B2 JPH0347542 B2 JP H0347542B2 JP 59101991 A JP59101991 A JP 59101991A JP 10199184 A JP10199184 A JP 10199184A JP H0347542 B2 JPH0347542 B2 JP H0347542B2
Authority
JP
Japan
Prior art keywords
chb
data
chp
channel
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59101991A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60246457A (ja
Inventor
Takashi Chiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59101991A priority Critical patent/JPS60246457A/ja
Publication of JPS60246457A publication Critical patent/JPS60246457A/ja
Publication of JPH0347542B2 publication Critical patent/JPH0347542B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP59101991A 1984-05-21 1984-05-21 メモリアクセス制御回路 Granted JPS60246457A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59101991A JPS60246457A (ja) 1984-05-21 1984-05-21 メモリアクセス制御回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59101991A JPS60246457A (ja) 1984-05-21 1984-05-21 メモリアクセス制御回路

Publications (2)

Publication Number Publication Date
JPS60246457A JPS60246457A (ja) 1985-12-06
JPH0347542B2 true JPH0347542B2 (enrdf_load_stackoverflow) 1991-07-19

Family

ID=14315297

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59101991A Granted JPS60246457A (ja) 1984-05-21 1984-05-21 メモリアクセス制御回路

Country Status (1)

Country Link
JP (1) JPS60246457A (enrdf_load_stackoverflow)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54128635A (en) * 1978-03-30 1979-10-05 Toshiba Corp Control system for cash memory
JPS563485A (en) * 1979-06-20 1981-01-14 Nec Corp Buffer memory device
JPS6055859B2 (ja) * 1981-06-15 1985-12-06 富士通株式会社 チャネル・バッファ制御方式

Also Published As

Publication number Publication date
JPS60246457A (ja) 1985-12-06

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