JPH0344968A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH0344968A JPH0344968A JP18111289A JP18111289A JPH0344968A JP H0344968 A JPH0344968 A JP H0344968A JP 18111289 A JP18111289 A JP 18111289A JP 18111289 A JP18111289 A JP 18111289A JP H0344968 A JPH0344968 A JP H0344968A
- Authority
- JP
- Japan
- Prior art keywords
- crystal silicon
- film
- silicon film
- layer
- melting point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 32
- 238000002844 melting Methods 0.000 claims abstract description 22
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract 8
- 239000001257 hydrogen Substances 0.000 claims abstract 8
- 239000013078 crystal Substances 0.000 claims abstract 4
- 238000000034 method Methods 0.000 claims description 41
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 32
- 229910052755 nonmetal Inorganic materials 0.000 claims description 22
- 239000007789 gas Substances 0.000 claims description 16
- 239000000126 substance Substances 0.000 claims description 15
- 230000008018 melting Effects 0.000 claims description 14
- 238000010438 heat treatment Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 150000002739 metals Chemical class 0.000 claims description 5
- 238000013459 approach Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052703 rhodium Inorganic materials 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims 2
- 229910052719 titanium Inorganic materials 0.000 claims 2
- 229910004205 SiNX Inorganic materials 0.000 abstract description 9
- 239000012535 impurity Substances 0.000 abstract description 8
- 238000004544 sputter deposition Methods 0.000 abstract description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 28
- 239000010409 thin film Substances 0.000 description 8
- 229910020968 MoSi2 Inorganic materials 0.000 description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- 229910016006 MoSi Inorganic materials 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- XMPZTFVPEKAKFH-UHFFFAOYSA-P ceric ammonium nitrate Chemical compound [NH4+].[NH4+].[Ce+4].[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O XMPZTFVPEKAKFH-UHFFFAOYSA-P 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 241001239379 Calophysus macropterus Species 0.000 description 1
- 229910016024 MoTa Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- JVJQPDTXIALXOG-UHFFFAOYSA-N nitryl fluoride Chemical compound [O-][N+](F)=O JVJQPDTXIALXOG-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置 とりわけ非単結晶シリコン膜を用
いた半導体装置及びその製造方法に関すん
従来の技術
社風 非晶質シリコン（以下ａ−３ｉと略す）を用いた
薄膜トランジスタアレーは低温で大面積化が可能であり
、安定性も優れていることか板 液晶表示用基板、イメ
ージセンサへの応用が積極的に行なわれていも しかも
このａ−３ｉを用いた薄膜トランジスタアレーは多種多
様の構成ができ、作製方法も数限りなく存在すも その
中でも逆スタガ構造のものについて下記に述べも
第２図は薄膜トランジスタの工程断面図である。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device, particularly a semiconductor device using a non-single crystal silicon film and a method for manufacturing the same. ) thin film transistor arrays can be made into large areas at low temperatures and have excellent stability. The thin film transistor array used can have a wide variety of configurations, and there are an infinite number of manufacturing methods. Among them, an inverted staggered structure will be described below. FIG. 2 is a cross-sectional view of the process of making a thin film transistor.
同図（ａ）の工程はゲート電極形成工程であり、例えば
Ｃｒ金属２をスパッタにより、 １００ＯＡ被着形戒し
そのＣｒ金属２を硝酸セリウムアンモニウムを主成分
とした溶液で選択的にエツチングを行なう工程である。The process shown in FIG. 2(a) is a gate electrode forming process, in which, for example, 100 OA of Cr metal 2 is deposited by sputtering, and the Cr metal 2 is selectively etched with a solution containing cerium ammonium nitrate as the main component. It is a process.
同図（ｂ）の工程は三層デポ工程型 例えば４０００Ａ
１５００Ａ／１０００Ａの膜厚で第１のシリコン窒化層
３ （以下ＳｉＮｘ層と略す）、不純物をほとんど含ま
ない第１のａ−３ｉ層４そして再び第２のＳｉＮｘ層５
を好ましくは連続的に被着すも これらの薄膜はいずれ
もシラン（以下ＳｉＨ４層と略す）ガスを主成分とする
原料ガスを３００℃前後の温度で高周波グロー放電によ
り分脈 台底するプラズマＣＶＤによって作製されも
同図 （ｃ）の工程は半導体層保護膜形成工程で、第２
のＳｉＮ層５をゲート上にのみ選択的に残した後、Ｓｉ
Ｈ４ガスにＰＨｓガスを添加したプラズマ放電によって
全面に５００Ａ程度の膜厚の不純物を含む第２のａ−３
ｉ層１０を被着すも 同図（ｄ）の工程はソース・ドレ
イン電極形成工程で、例えば全面にＭｏＳｉ２／ Ａｌ
８．９をスパッタで１０００Ａ／７０００Ａ被着し燐
酸系の溶液でＡＩを選択的に食刻し、形成したＡ１パタ
ーンをマスクとしＴ：、 ＭｏＳｉ２、第１、第２の
ａ−８ｉ層をフッ硝酸系の溶液で選択的に食刻する工程
であも この構造によって安定な容量が実現できること
が特開昭５７−４５９６８号に開示されている。The process in figure (b) is a three-layer deposition process type, for example, 4000A.
A first silicon nitride layer 3 (hereinafter abbreviated as SiNx layer) with a film thickness of 1500A/1000A, a first a-3i layer 4 containing almost no impurities, and again a second SiNx layer 5.
These thin films are preferably deposited continuously, but all of these thin films are made by plasma CVD using a high-frequency glow discharge at a temperature of around 300°C using a raw material gas mainly composed of silane (hereinafter abbreviated as SiH4 layer) gas. Even if it is made
The step in (c) of the same figure is the semiconductor layer protective film forming step, and
After selectively leaving the SiN layer 5 only on the gate, the SiN layer 5 of
The second a-3 contains impurities with a film thickness of about 500A on the entire surface by plasma discharge with PHs gas added to H4 gas.
Although the i-layer 10 is deposited, the process shown in FIG.
8.9 was deposited at 1000A/7000A by sputtering, the AI was selectively etched with a phosphoric acid solution, and using the formed A1 pattern as a mask, the T:, MoSi2, first and second a-8i layers were etched. JP-A-57-45968 discloses that this structure allows a stable capacity to be achieved even in the process of selectively etching with a nitric acid solution.
発明が解決しようとする課題
上述した従来のＴＰＴアレーは７枚の製膜工程を必要と
し必然的にフォトマスク枚数が４枚以上になり、作製工
程が長くコスト的には苦しいことは明かである。その作
製工程の中でプラズマＣＶＤ法は確立した技術ではある
力曳 メンテサイクルが他の装置に比べて非常に短く、
メンテ方法も難し鶏 また パラメータが多いから制御
しにくいので、なるべく回数を減らし安定なプロセスを
確立する必要があも そして、プロセスの歩留まり向上
の妨げになっているｎ”ａ−３ｉの密着性が弱く、この
上に厚い金属層をかさねて堆積すると時として問題が発
生し九
−Ｘ ソース・ドレイン電極に使用されている金属と
不純物を含まないａ−８ｉ層との間にｎ″ａ−８ｉ層を
介在しなければオーミック接続になりにくく、また 金
属と不純物を含まないａ−３ｉ層との間のブロッキング
層を形成しなければＴＰＴ個々の性能のばらつきが太き
（１
本発明はかかる点に鑑ム 構造が簡素で工程の少なく不
良発生率の少なく配線抵抗が小さい半導体装置及びその
製造方法を提供することを目的とすも
課題を解決するための手段
本発明はプラズマＣＶＤ法による製膜回数を減らし な
おかつ不純物を含まないａ−３ｉ層と金属配線との接続
のオーミック性を保ちつつ歩留まりを向上させるもので
あも 即ちａ−８ｉ層を選択的に形成した後、膜上に非
金属族元素を含んだガスと水素ガスでプラズマ放電を行
Ｌ＼ 表面上に非金属族元素の活性化状態を作り上げて
から高融点金属を主成分とした物質にドーピング法によ
り非金属族元素を含有させた膜を形成する力＼ また（
上 高融点金属を主成分とした物質に非金属族元素を深
さ方向に濃度勾配あるいは前記シリコン膜に近接するに
したがって元素の濃度勾配を形成するかどちらかを施し
すことにより、ａ−３ｉ層と非金属族元素を含有させた
膜との界面にＨの量を多く介在させる。Problems to be Solved by the Invention The conventional TPT array described above requires a process for forming seven films, which inevitably results in the number of photomasks being four or more, and it is clear that the process is long and difficult in terms of cost. . The plasma CVD method is an established technology in the manufacturing process.The maintenance cycle is very short compared to other equipment.
The maintenance method is also difficult.Also, since there are many parameters, it is difficult to control, so it is necessary to establish a stable process by reducing the number of times as much as possible.Also, the adhesion of n"a-3i, which is an impediment to improving the process yield, is If thick metal layers are deposited on top of this metal layer, problems may sometimes occur. If there is no intervening layer, it will be difficult to form an ohmic connection, and if a blocking layer is not formed between the metal and the a-3i layer that does not contain impurities, there will be wide variations in the performance of each TPT (1) The present invention solves this problem. In view of the above, an object of the present invention is to provide a semiconductor device with a simple structure, fewer steps, a lower defect rate, and a lower wiring resistance, and a method for manufacturing the same. In other words, after selectively forming the A-8i layer, a non-metallic layer is formed on the film. Plasma discharge is performed using a gas containing group elements and hydrogen gas. After creating an activated state of non-metal group elements on the surface, non-metal group elements are added to a substance whose main component is a high melting point metal using a doping method. The force that forms a film ＼ Also (
By applying either a concentration gradient of a non-metal group element in the depth direction to a substance mainly composed of a high melting point metal or a concentration gradient of the element as it approaches the silicon film, a-3i A large amount of H is present at the interface between the layer and the film containing a non-metal group element.
旧＆ ａ−３’ｉ層と非金属族元素を含有させた膜と
の・界面で動きやすく、Ｈと非金属族元素の衝突等でａ
−３ｉ層の中に非金属族元素を運ぶ役目をすも その上
加熱処理あるいは光などの電磁波照射処理の少なくとも
どちらか一方を施すことにより、非金属族元素を不純物
を含まないａ−３ｉ層により広く拡散してオーミック接
続にし 金属とａ−８ｉ層との間のブロッキング層をも
形威すも
作用
上記手段を用いるとｎ”ａ−３ｉ膜を形成する必要がな
くな４ｎ″ａ−３ｉ膜を形成しないで高融点金属を主成
分とした物質にドーピング法により非金属族元素を含有
させた膜を形成する力＼ また（友 高融点金属を主成
分とした物質に非金属族元素を深さ方向に濃度勾配ある
いは前記シリコン膜に近接するにしたがって元素の濃度
勾配を形成して含有させた半導体素子ｉ′！、、プラズ
マＣＶＤ法を一回のみで構成でき、工程数が減り生産性
が向上する。また 現状での歩留まりに大きな影響を及
ぼしているプロセス不良の一つであるｎ”ａ−３ｉ剥離
という問題点がなくなる。その上 ｎ″ａ−３ｉ膜を含
んだ多層膜のエツチングにおいてｎ′″ａ−３ｉ膜のオ
ーバーエツチングがなくなり、プロセス的に安定になる
。It is easy to move at the interface between the old &a-3'i layer and the film containing non-metal group elements, and a
The role of transporting non-metal group elements into the -3i layer is to provide impurity-free a-3i elements to the non-metal group elements by applying at least one of heat treatment and electromagnetic wave irradiation treatment such as light. By using the above method, there is no need to form an n"a-3i film, and the 4n"a-3i Ability to form a film in which non-metal group elements are added to a substance whose main component is a high-melting point metal without forming a film＼Also, (tomo) Semiconductor element i'!, in which a concentration gradient of elements is formed in the depth direction or in the vicinity of the silicon film, can be constructed using only one plasma CVD method, reducing the number of steps and improving productivity. In addition, the problem of n''a-3i peeling, which is one of the process defects that currently has a large impact on yield, is eliminated.In addition, the etching of multilayer films including n''a-3i films is eliminated. In this process, over-etching of the n'''a-3i film is eliminated and the process becomes stable.
実施例
以下に 本発明の実施例について図面を参照しながら説
明する。EXAMPLES Below, examples of the present invention will be described with reference to the drawings.
（実施例１）
本発明（よ 非単結晶シリコンを用いた半導体装置にお
ける配線と半導体層との接続に関するものであるが下記
にＴＰＴを例にとって説明する。(Example 1) The present invention relates to a connection between a wiring and a semiconductor layer in a semiconductor device using non-single crystal silicon, and will be described below using TPT as an example.
第１図＋１ＴＰＴの工程断面図である。同図（ａ）の工
程はゲート電極形成工程であり、例えばＣｒ金属２をス
パッタにより、 １００ＯＡ被着形戒し そのＣｒ金属
２を硝酸セリウムアンモニウムを主成分とした溶液で選
択的にエツチングを行なう工程であ瓜 同図（ｂ）の工
程は三層デボ工程で、例えば４０００Ａ１５００Ａ／１
００ＯＡの膜厚で第１のＳｉＮｘ層３、不純物をほとん
ど含まないａ−３ｉ層４そして再び第２のＳｉＮｘ層５
を好ましくは連続的に被着すも これらの薄膜はいずれ
もＳｉＨ４層ガスを主成分とする原料ガスを３００℃前
後の温度で高周波グロー放電により分脈 合成するプラ
ズマＣＶＤによって作製される。同図（Ｃ）の工程は半
導体層保護膜形成工程で、第２のＳｉＮｘ層５をゲート
上にのみ選択的に残した後、ＰＨｓ ／ Ｐｔ（ｓ ＋
Ｈ２の比が０．０１から０．５０までの間の混合ガスで
ＲＦ放電を行し＼ 第１のＰドープＭｏＳｉ２層６ （
同は 以下Ｐ ＭｏＳｉ２層と示す）を形成した後
、Ｍｏ５ｉａをスパッタ装置で形成するときにＰＨａ
／ ＰＨｓ ＋ Ａｒの比が０．０１から０．５０まで
の間の混合ガスでＲＦ放電を行ＬＸ、第２のＰ−ＭｏＳ
ｉ２層７を形成すも 同図（ｄ）の工程はソース・ドレ
イン電極形成工程で、例えば全面にＡ１８、９をスパッ
タで７０００Ａ被着し燐酸系の溶液でＡ１を選択的に食
刻限 形成したＡ１パターンをマスクとして、第１、第
２のＰ−ＭｏＳｉ２層６．７、ａ−８ｉ層４をフッ硝酸
系の溶液で選択的に食刻する工程であも 最後に 加熱
処理を施す。FIG. 1 is a process sectional view of +1TPT. The process shown in FIG. 2(a) is a gate electrode forming process, in which, for example, 100 OA of Cr metal 2 is deposited by sputtering, and the Cr metal 2 is selectively etched with a solution containing cerium ammonium nitrate as the main component. The process shown in Figure (b) is a three-layer debo process, for example 4000A1500A/1
A first SiNx layer 3 with a film thickness of 00OA, an a-3i layer 4 containing almost no impurities, and a second SiNx layer 5 again.
These thin films are preferably deposited continuously. All of these thin films are produced by plasma CVD, in which a source gas containing SiH4 layer gas as a main component is synthesized by high-frequency glow discharge at a temperature of around 300°C. The process shown in FIG. 3C is a semiconductor layer protective film forming process, in which the second SiNx layer 5 is selectively left only on the gate, and then PHs/Pt(s +
RF discharge was performed with a mixed gas with a H2 ratio of 0.01 to 0.50, and the first P-doped MoSi2 layer 6 (
After forming a P-MoSi2 layer (hereinafter referred to as PMoSi2 layer), PHa
Perform RF discharge with a gas mixture with a ratio of /PHs + Ar between 0.01 and 0.50, LX, the second P-MoS
Although the i2 layer 7 is formed, the step shown in the figure (d) is the source/drain electrode forming step, for example, A18, 9 is deposited on the entire surface by sputtering at 7000A, and A1 is selectively etched using a phosphoric acid solution. Using the A1 pattern as a mask, the first and second P-MoSi2 layers 6.7 and the A-8i layer 4 are selectively etched with a fluoro-nitric acid solution, and finally a heat treatment is performed.
これにより第１、第２のＭｏＳｉ２６、７からａ−３ｉ
層４にＰ元素を拡散させ、Ｐイオンの活性化が図れる。As a result, from the first and second MoSi26, 7 to a-3i
By diffusing the P element into the layer 4, the P ions can be activated.
な抵 本実施例（上 第１図（ａ）の工程で、Ｃｒのゲ
ート配線２を形成するのにスパッタ法を使用した力ｔ
金属層が形成できるならば 蒸着方法を問わず、例えば
電子ビームｍ ＣＶＤ！ 抵抗加熱法等でもかま
わな（１また 材料の種類Ｃよ高温処理を行っても半導
体層または絶縁体層に拡散しない物質であれば ＩＴ○
、ＭｏＳｉ２、ＭｏＴａ等でも本発明の特許請求の範囲
に適用すも また 本実施例では非金属元素を含有する
膜としてＰＨａガスを混入したＲＦ放電スパッタ法によ
る第１、第２のＰ−ＭｏＳｉ２膜６、７を形成した力丈
本発明（よ 蒸着方法を問わず、例えば 非金属元素
を含有したターゲットをスパッタする方ａ ＣＶＤＬ
イオンシャワー法等でもかまわな（１そして、膜と
して、Ｍｏ５ｉａだけでなく、高融点金属を主成分とし
た物質であれば あるい（上Ｔａ、 Ｗ、 Ｃｒ、 Ｔ
ｉ、 Ｃｏ、 Ｎｉ、 Ｚｒ。In this embodiment (above), the force t used in the process of FIG.
As long as a metal layer can be formed, regardless of the deposition method, e.g. electron beam CVD! Resistance heating method etc. may also be used (1) If the material type C is a substance that does not diffuse into the semiconductor layer or insulator layer even if subjected to high temperature treatment, IT○
, MoSi2, MoTa, etc. are also applicable to the scope of the claims of the present invention. In addition, in this example, the first and second P-MoSi2 films formed by the RF discharge sputtering method in which PHa gas is mixed are used as films containing nonmetallic elements. 6, 7 is formed by the present invention (regardless of the vapor deposition method, for example, a method of sputtering a target containing a non-metallic element, CVDL).
Ion shower method etc. may also be used (1) If the film is not only Mo5ia but also a substance whose main component is a high melting point metal (Ta, W, Cr, T)
i, Co, Ni, Zr.
Ｒｈ、 Ｐｄ、 Ｐｔのうちいずれか一つの硅化物ある
いは高融点金属同士の化合物であれば 任意のものでよ
い。本実施例では加熱処理を施した力交 光などの電磁
波照射処理でも構わなく、本実施例を例にとるならば
第１、第２のｐ−ＭｏＳｉ２層６、７からａ−３ｉ層４
にＰ元素を拡散させる力＼ 拡散しなくてもＰイオンの
活性化が図れも
また 本実施例では基板ｌとしてガラスを用いた力丈
絶縁基板であれば任意のものでよく、絶縁膜としてＳｉ
Ｎｘ層３を使用しためｔ 少なくとも一層以上の絶縁膜
であれば材料の種類・蒸着方法を問わず任意のものであ
ってもよ賎 本実施例では非晶質シリコンを用いた薄膜
トランジスタアレーについて説明した力支 非単結晶シ
リコン膜を用いた半導体装置あれば 多結晶質シリコン
等でも本発明の特許請求の範囲に適用する。最後に Ａ
１８．９を本実施例では導電膜に採用したが 少なくと
も導電体が一層以上あり、かス 絶縁膜のコンタクトホ
ールの断差をカバーするものであれば任意のものでよく
、非金属元素としてＰ元素を例にとったたａ６． Ｐ
’ｆｈガスを使用したカミ 本発明の特許請求の範囲は
非金属元素を含有するガス（Ｐ、 Ｂ、 Ｓｂ、 Ｇａ
＠であれば 例えｉ；ＣＢ２Ｈｅ等の任意のものでよし
１（実施例２）
実施例２の工程断面図を第１図（ａ）〜（ｄ）に示す。Any one of Rh, Pd, and Pt silicide or a compound of high melting point metals may be used. In this example, heat treatment and electromagnetic wave irradiation treatment such as light may be used.
First and second p-MoSi layers 6 and 7 to a-3i layer 4
It is also possible to activate P ions even without diffusion.
Any insulating substrate may be used, and Si as an insulating film may be used.
Since the Nx layer 3 is used, any insulating film having at least one layer may be used regardless of the type of material or deposition method. In this example, a thin film transistor array using amorphous silicon will be explained. If there is a semiconductor device using a non-monocrystalline silicon film, polycrystalline silicon or the like is also applicable to the claims of the present invention. Finally A
18.9 was used as the conductive film in this example, but any material may be used as long as it has at least one layer of conductor and covers the gap between the contact holes in the insulating film. Using elements as an example a6. P
The claim of the present invention is based on gases containing non-metallic elements (P, B, Sb, Ga
For example, if it is @, any material such as CB2He may be used.1 (Example 2) Process cross-sectional views of Example 2 are shown in FIGS. 1(a) to (d).
実施例１の工程とほぼ同じである力交 同図（Ｃ）の工
程（よ ＰＨｓ ＋ Ａｒの混合ガスでＲＦ放電を行う
ときに 放電開始と同時にＰＨ３／ ＰＨａ ＋ Ａｒ
の比を０．１５の状態にしておき放電終了時には０．０
１になるように混合ガスのガス比を時間に関して変化さ
せてＰ−ＭｏＳｉａを形成させる。本実施例ζ上 不純
物を含まないａ−３ｉ層４と第１のＰ−ＭｏＳｉ２６と
の界面にＰ元素の濃度を高くすることにより接続抵抗を
下げると同時に第２のＰ−ＭｏＳｉ２７とＡ１８、９の
界面はＰ元素濃度を０にすることにより配線抵抗を下げ
ることができも まｆ＝ Ｐｌｈガスの濃度比を０．
１５に記述しである力ｔ ０．１０−０．５０までの
比であればまた 本実施例では高融点金属を主成分とし
た物質に非金属族元素を深さ方向に濃度勾配を形式した
力文 不純物を含まないａ−８ｉ層４に近接するにした
がって元素の濃度勾配を形成した構造の半導体素子であ
れ（よ 本発明の特許請求の範囲に適用すも
発明の効果
本発明（よ この構造を用いたＴＰＴアレーを液晶表示
装置に採用するとＴＰＴアレーの不良原因の一つである
ｎ’ ａ−３ｉ剥離という問題点が解決し歩留まりを向
上させるものである。ｎ″ａ−３ｉ膜を形成しない半導
体素子は 不純物を含まないａ−３ｉ層と金属配線との
接続のオーミック性を保ちっつＣＶＤの製膜工程が短縮
できるた△ 量産性に富へ技術的に工場導入が可能であ
る。そして、非金属族元素を深さ方向に濃度勾配を形式
したものや不純物を含まないａ−３ｉ層に近接するにし
たがって元素の濃度勾配を形式したもα あるい（よ
加熱処理あるいは電磁波照射処理を・施してＬ 同様の
効果が得られる。最後に 半導体層のオーミック接続を
必要とするＭＯ３構造にも適用できａThe process of force exchange diagram (C), which is almost the same as the process of Example 1, is similar to the process shown in Figure (C).
The ratio is set to 0.15 and 0.0 at the end of discharge.
P-MoSia is formed by changing the gas ratio of the mixed gas over time so that the ratio becomes 1. Embodiment ζ Top By increasing the concentration of P element at the interface between the a-3i layer 4 that does not contain impurities and the first P-MoSi 26, the connection resistance is lowered and at the same time the second P-MoSi 27 and A18, 9 The interconnect resistance can be lowered by setting the P element concentration to 0 at the interface.
In this example, a concentration gradient of a non-metal group element was formed in the depth direction in a material mainly composed of a high-melting point metal. If the semiconductor element has a structure in which a concentration gradient of elements is formed as it approaches the a-8i layer 4 that does not contain impurities, the effect of the invention (as applied to the claims of the present invention) is Adopting a TPT array using this structure in a liquid crystal display device solves the problem of n'a-3i peeling, which is one of the causes of defects in TPT arrays, and improves yield. The semiconductor element that is not formed can shorten the CVD film forming process while maintaining the ohmic properties of the connection between the impurity-free A-3I layer and the metal wiring, making it technically possible to introduce it into a factory for mass production. .Then, the concentration gradient of non-metal group elements is formed in the depth direction, or the concentration gradient of the element is formed as it approaches the a-3i layer that does not contain impurities.
The same effect as L can be obtained by applying heat treatment or electromagnetic wave irradiation treatment. Finally, it can also be applied to MO3 structures that require ohmic connections between semiconductor layers.
第１図は本発明の一実施例にかかるＴＰＴの工程断面は
第２図は従来のＴＰＴの工程断面図である。
２＝Ｃｒ恩 ３・・・第１のＳｉＮｘ、 ４ ・・・
ａ−８ｉ、［５・・・第２のＳｉＮｘ、 ６”第１の
Ｐ−ＭｏＳｉ２．７・・・第２のＰ−ＭｏＳｉ２゜FIG. 1 is a cross-sectional view of a TPT process according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a conventional TPT process. 2=Cr-on 3...first SiNx, 4...
a-8i, [5...second SiNx, 6''first P-MoSi2.7...second P-MoSi2゜
Claims (11)
配線との間に非金属族元素を含有させた高融点金属を主
成分とする層と、前記層と前記第１の非単結晶シリコン
膜の間に前記第１の非単結晶シリコン膜よりも水素元素
を多く含有する第２の非単結晶シリコン膜とを介在させ
たことを特徴とする半導体装置。(1) A layer mainly composed of a high-melting point metal containing a non-metal group element between a first non-single crystal silicon film close to the wiring and the wiring; A semiconductor device characterized in that a second non-single crystal silicon film containing more hydrogen element than the first non-single crystal silicon film is interposed between the crystal silicon films.
を主成分とする層と、前記第１の非単結晶シリコン膜と
、前記層と前記第１の非単結晶シリコン膜の間に前記第
１の非単結晶シリコン膜よりも水素元素を多く含有する
第２の非単結晶シリコン膜とを含むことを特徴とする半
導体装置。(2) A layer in which the wiring itself is mainly composed of a high melting point metal containing a non-metal group element, the first non-single crystal silicon film, and between the layer and the first non-single crystal silicon film. and a second non-single crystal silicon film containing more hydrogen element than the first non-single crystal silicon film.
配線との間に高融点金属を主成分とした物質に非金属族
元素を前記第１の非単結晶シリコン膜に近接するにした
がって元素の濃度勾配をおおきく形成して含有させた膜
と、前記膜と前記第１の非単結晶シリコン膜の間に前記
第１の非単結晶シリコン膜よりも水素元素を多く含有す
る第２の非単結晶シリコン膜とを介在させたことを特徴
とする半導体装置。(3) A non-metallic group element is added to a substance containing a high melting point metal as a main component between the first non-single-crystal silicon film adjacent to the wiring and the wiring. Therefore, a film in which elements are contained by forming a large concentration gradient, and a second film containing hydrogen element in a larger amount than the first non-single crystal silicon film between the film and the first non-single crystal silicon film. 1. A semiconductor device characterized in that a non-single crystal silicon film is interposed therebetween.
属族元素を前記第１の非単結晶シリコン膜に近接するに
したがって元素の濃度勾配をおおきく形成して含有させ
た膜と、前記第１の非単結晶シリコン膜と、前記膜と前
記第１の非単結晶シリコン膜の間に前記第１の非単結晶
シリコン膜よりも水素元素を多く含有する第２の非単結
晶シリコン膜とで構成されたことを特徴とする半導体装
置。(4) a film in which the wiring itself contains a non-metal group element in a substance whose main component is a high-melting point metal, forming a concentration gradient of the element that increases as it approaches the first non-single-crystal silicon film; the first non-single-crystal silicon film; and a second non-single-crystal silicon containing more hydrogen element than the first non-single-crystal silicon film between the film and the first non-single-crystal silicon film. A semiconductor device comprising a film.
配線との間に高融点金属を主成分とした物質に非金属族
元素を深さ方向に濃度勾配をおおきく形成して含有させ
た膜と、前記膜と前記第１の非単結晶シリコン膜の間に
前記第１の非単結晶シリコン膜よりも水素元素を多く含
有する第２の非単結晶シリコン膜とを介在させたことを
特徴とする半導体装置。(5) Between the first non-single-crystal silicon film close to the wiring and the wiring, a non-metallic group element is contained in a substance mainly composed of a high-melting point metal, forming a large concentration gradient in the depth direction. and a second non-single-crystal silicon film containing more hydrogen element than the first non-single-crystal silicon film is interposed between the film and the first non-single-crystal silicon film. A semiconductor device characterized by:
属族元素を深さ方向に濃度勾配をおおきく形成して含有
させた膜と、前記第１の非単結晶シリコン膜と、前記膜
と前記第１の非単結晶シリコン膜の間に前記第１の非単
結晶シリコン膜よりも水素元素を多く含有する第２の非
単結晶シリコン膜とで構成されたことを特徴とする半導
体装置。(6) a film in which the wiring itself contains a non-metal group element in a material mainly composed of a high-melting point metal with a large concentration gradient in the depth direction; the first non-single crystal silicon film; A semiconductor characterized in that a second non-single-crystal silicon film containing more hydrogen element than the first non-single-crystal silicon film is provided between the film and the first non-single-crystal silicon film. Device.
前記膜上に非金属族元素を含んだガスと水素ガスでプラ
ズマ放電を行う工程と、前記膜上に高融点金属を主成分
とした物質にドーピング法により非金属族元素を含有さ
せた膜を形成する工程と、前記工程後に加熱処理あるい
は電磁波照射処理の少なくともどちらか一方を施す工程
とを含むことを特徴とする半導体装置の製造方法。(7) forming a non-single crystal silicon film on the substrate;
A step of performing plasma discharge on the film with a gas containing a non-metal group element and hydrogen gas, and a film containing a non-metal group element on the film by a doping method in a substance whose main component is a high melting point metal. 1. A method of manufacturing a semiconductor device, comprising a step of forming a semiconductor device, and a step of performing at least one of a heat treatment and an electromagnetic wave irradiation treatment after the step.
族元素を含有させた膜を形成する工程と、前記膜上に非
金属族元素を含んだガスと水素ガスでプラズマ放電を行
う工程と、前記膜上に非単結晶シリコン膜を形成する工
程と、前記工程後に加熱処理あるいは電磁波照射処理の
少なくともどちらか一方を施すことにより前記高融点金
属を主成分とした物質に近接する非単結晶シリコン膜に
前記非金属族元素を濃度勾配生成する拡散工程とを含む
ことを特徴とする半導体装置の製造方法。(8) Forming a film on the substrate containing a non-metal group element in a substance mainly composed of a high-melting point metal, and plasma discharge using a gas containing the non-metal group element and hydrogen gas on the film. a step of forming a non-single-crystal silicon film on the film; and a step of applying at least one of heat treatment or electromagnetic wave irradiation treatment after the step to get close to the substance whose main component is the high melting point metal. 1. A method of manufacturing a semiconductor device, comprising: a diffusion step of generating a concentration gradient of the non-metal group element in a non-single-crystal silicon film.
前記膜上に非金属族元素を含んだガスと水素ガスでプラ
ズマ放電を行う工程と、前記膜上に高融点金属を主成分
とした物質に非金属族元素を含有させた膜を形成する工
程と、前記工程後に加熱処理あるいは電磁波照射処理の
少なくともどちらか一方を施すことにより前記高融点金
属を主成分とした物質に近接する非単結晶シリコン膜に
前記非金属族元素を濃度勾配生成する拡散工程とを含む
ことを特徴とする半導体装置の製造方法。(9) forming a non-single crystal silicon film on the substrate;
A step of performing plasma discharge on the film using a gas containing a non-metal group element and hydrogen gas, and a step of forming a film on the film containing a non-metal group element in a substance mainly composed of a high melting point metal. and diffusion to generate a concentration gradient of the non-metal group element in the non-single-crystal silicon film adjacent to the substance containing the high melting point metal as a main component by performing at least one of heat treatment or electromagnetic wave irradiation treatment after the step. A method for manufacturing a semiconductor device, comprising the steps of:
Ｗ、Ｃｒ、Ｔｉ、Ｃｏ、Ｎｉ、Ｚｒ、Ｒｈ、Ｐｄ、Ｐｔ
のうちいずれか、一つの硅化物あるいは高融点金属同士
の化合物であることを特徴とする請求項１、２、３、４
、５、６のいずれかに記載の半導体装置(10) Substances mainly composed of high melting point metals such as Mo, Ta,
W, Cr, Ti, Co, Ni, Zr, Rh, Pd, Pt
Claims 1, 2, 3, and 4, characterized in that any one of these is one silicide or a compound of high melting point metals.
, 5, 6. The semiconductor device according to any one of .
Ｗ、Ｃｒ、Ｔｉ、Ｃｏ、Ｎｉ、Ｚｒ、Ｒｈ、Ｐｄ、Ｐｔ
のうちいずれか一つの硅化物あるいは高融点金属同士の
化合物であることを特徴とする請求項７、８、９のいず
れかに記載の半導体装置の製造方法。(11) Substances mainly composed of high melting point metals such as Mo, Ta,
W, Cr, Ti, Co, Ni, Zr, Rh, Pd, Pt
10. The method for manufacturing a semiconductor device according to claim 7, wherein the material is one of silicides or a compound of high melting point metals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1181112A JP2811765B2 (en) | 1989-07-12 | 1989-07-12 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1181112A JP2811765B2 (en) | 1989-07-12 | 1989-07-12 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0344968A true JPH0344968A (en) | 1991-02-26 |
| JP2811765B2 JP2811765B2 (en) | 1998-10-15 |
Family
ID=16095058
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1181112A Expired - Fee Related JP2811765B2 (en) | 1989-07-12 | 1989-07-12 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2811765B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5719078A (en) * | 1995-02-11 | 1998-02-17 | Samsung Electronics Co., Ltd. | Method for making a thin film transistor panel used in a liquid crystal display having a completely self-aligned thin film transistor |
| US6104042A (en) * | 1999-06-10 | 2000-08-15 | Chi Mei Optoelectronics Corp. | Thin film transistor with a multi-metal structure a method of manufacturing the same |
| WO2009063648A1 (en) * | 2007-11-14 | 2009-05-22 | Panasonic Corporation | Thin-film transistor, manufacturing method therefor and electronic device using a thin-film transistor |
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|---|---|---|---|---|
| JPS6014473A (en) * | 1983-07-05 | 1985-01-25 | Asahi Glass Co Ltd | Electrode structure for thin film transistor |
| JPS61234080A (en) * | 1985-04-10 | 1986-10-18 | Nec Corp | Manufacture of thin film transistor |
| JPS6331169A (en) * | 1986-07-17 | 1988-02-09 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | Manufacture of silicon device |
| JPH01143360A (en) * | 1987-11-30 | 1989-06-05 | Matsushita Electric Ind Co Ltd | Insulated gate type transistor and manufacture thereof |
-
1989
- 1989-07-12 JP JP1181112A patent/JP2811765B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6014473A (en) * | 1983-07-05 | 1985-01-25 | Asahi Glass Co Ltd | Electrode structure for thin film transistor |
| JPS61234080A (en) * | 1985-04-10 | 1986-10-18 | Nec Corp | Manufacture of thin film transistor |
| JPS6331169A (en) * | 1986-07-17 | 1988-02-09 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | Manufacture of silicon device |
| JPH01143360A (en) * | 1987-11-30 | 1989-06-05 | Matsushita Electric Ind Co Ltd | Insulated gate type transistor and manufacture thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5719078A (en) * | 1995-02-11 | 1998-02-17 | Samsung Electronics Co., Ltd. | Method for making a thin film transistor panel used in a liquid crystal display having a completely self-aligned thin film transistor |
| US6104042A (en) * | 1999-06-10 | 2000-08-15 | Chi Mei Optoelectronics Corp. | Thin film transistor with a multi-metal structure a method of manufacturing the same |
| WO2009063648A1 (en) * | 2007-11-14 | 2009-05-22 | Panasonic Corporation | Thin-film transistor, manufacturing method therefor and electronic device using a thin-film transistor |
| US8436355B2 (en) | 2007-11-14 | 2013-05-07 | Panasonic Corporation | Thin-film transistor, manufacturing method therefor, and electronic device using a thin-film transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2811765B2 (en) | 1998-10-15 |
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| JPH02268443A (en) | Semiconductor device |
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