JP2797361B2 - Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor device, particularly to a semiconductor device using an amorphous silicon film.

2. Description of the Related Art In recent years, a thin film transistor array using amorphous silicon (hereinafter abbreviated as aSi) can have a large area at a low temperature.
Due to its excellent stability, application to liquid crystal display substrates and image sensors is being actively pursued. Moreover, the thin film transistor array using the aSi can have a variety of configurations, and there are an unlimited number of manufacturing methods. Among them, those having an inverted stagger structure are described below.

FIG. 3 is a process sectional view of a thin film transistor. The step of FIG. 3A is a step of forming a gate electrode, for example, a step of depositing Cr metal at 1000 A by sputtering and selectively etching Cr with a solution containing cerium ammonium nitrate as a main component. The process shown in FIG. 3B is a three-layer deposition process, for example, a first silicon nitride layer (hereinafter abbreviated as SiN _X layer) having a thickness of 4000 A / 500 A / 1000 A, a first aSi layer containing almost no impurities, and Again, a second SiN _X layer is applied, preferably continuously. Each of these thin films is heated at 300 ° C using silane (hereinafter abbreviated as SiH ₄ layer) gas as a main component gas.
It is manufactured by the plasma sea-wave (CVD) method of decomposing and synthesizing at high and low temperatures by high frequency glow discharge.
The step shown in FIG. 2C is a step of forming a semiconductor layer protective film, which is the second step.
After leaving selectively only the SiN _X layer on the gate, the SiH ₄ gas
A second aSi layer containing an impurity having a thickness of about 500 A is deposited on the entire surface by plasma discharge to which PH ₃ gas is added. The step (d) in the figure is a source / drain electrode forming step, for example, MoSi ₂ / Al is deposited on the entire surface by sputtering at 1000A / 7000A, and Al is selectively etched with a phosphoric acid solution to form an Al pattern. This is a step of selectively etching the MoSi ₂ , the first and second aSi layers with a hydrofluoric-nitric acid-based solution using as a mask. Japanese Patent Application Laid-Open No. 57-45968 discloses that a stable capacity can be realized by this structure.

Problems to be Solved by the Invention It is clear that the above-described conventional TFT array requires seven film forming steps, and inevitably requires four or more photomasks, and the manufacturing steps are long and costly. . Although the plasma CVD method is an established technique in the manufacturing process, the maintenance cycle is very short compared to other apparatuses, and the maintenance method is difficult. In addition, since there are many parameters, it is difficult to control, so it is necessary to establish a stable process by reducing the number of times as much as possible. Then, there is a problem of n ⁺ aSi peeling which hinders the improvement of the process yield.

Conversely, unless an n ⁺ aSi layer is interposed between the metal used for the source / drain electrodes and the aSi layer containing no impurities, ohmic connection is unlikely to occur and the performance of individual TFTs greatly varies.

The present invention has been made in view of the problems of the related art, and has a TFT with a simple structure, a small number of steps, a small defect rate, and a small wiring resistance.
The purpose is to provide an array.

Means for Solving the Problems A semiconductor device according to the present invention has the following features.
A semiconductor device using an amorphous silicon layer containing almost no impurities, wherein an amorphous silicon layer containing impurities is interposed between a source / drain electrode containing Al and the amorphous silicon layer. In addition, a film containing a non-metal ion and containing a high melting point metal as a main component is interposed, and the concentration of the non-metal ion in the film containing a high melting point metal containing the non-metal ion as the main component is set to The structure is characterized in that the height is increased as approaching the crystalline silicon layer.

The use of the above means makes it unnecessary to form an n ⁺ aSi film. Alternatively, the yield can be increased through the n ⁺ aSi film, and the TFT array characteristics can be improved. First, a semiconductor element without an n ⁺ aSi film can be formed by a single plasma CVD method, and the number of steps is reduced, and productivity is improved. In addition, the problem of n ⁺ aSi peeling, which is one of the process defects that greatly affects the current yield, is eliminated. In addition, when etching a multilayer film including an n ⁺ aSi film, the n ⁺ aSi
Over-etching of the film is eliminated, and the process becomes stable.

Embodiment (Embodiment 1) The present invention relates to a connection between a wiring and a semiconductor layer in a semiconductor device using amorphous silicon.
This will be described using a TFT as an example.

FIG. 1 is a sectional view of a TFT process. The step of FIG. 3A is a step of forming a gate electrode, for example, a step of depositing Cr metal at 1000 A by sputtering and selectively etching Cr with a solution containing cerium ammonium nitrate as a main component. The step shown in FIG. 4B is a three-layer deposition step, for example, a first SiN _X layer having a film thickness of 4000 A / 500 A / 1000 A, an aSi layer containing almost no impurities, and again a second SiN _X layer, which is preferably continuous. To be adhered to. These thin films are all SiH ₄
It is produced by plasma CVD which decomposes and synthesizes a raw material gas containing a layer gas as a main component at a temperature of about 300 ° C. by high-frequency glow discharge. The step (c) in the same figure is a semiconductor layer protective film forming step, in which after selectively leaving the second SiN _X layer only on the gate, when forming MoSi ₂ by a sputtering apparatus, PH ₃ / PH ₃ +
RF discharge is performed with a mixed gas having an Ar ratio of 0.01 to 0.15 to form MoSi ₂ containing phosphorus ions. The step (d) in the figure is a source / drain electrode formation step, for example, Al is deposited on the entire surface by sputtering at 7000 A, and a phosphoric acid-based solution is used to deposit Al.
Is selectively etched, and the MoSi ₂ and aSi layers are selectively etched with a hydrofluoric / nitric acid-based solution using the formed Al pattern as a mask.

In the present embodiment, the sputtering method was used to form the Cr gate wiring in the step of FIG. 1A. However, if the metal layer 3 can be formed, regardless of the vapor deposition method, for example, An electron beam method, a CVD method, a resistance heating method, or the like may be used. In addition, as long as the material does not diffuse into the semiconductor layer or the insulator layer even after the high-temperature treatment, ITO, MoSi ₂ , MoTa
And so on. Further, in this embodiment, the MoSi ₂ film was formed by RF discharge sputtering mixed with PH ₃ gas as a film containing non-metal ions, but the present invention is not limited to the vapor deposition method, and includes, for example, non-metal ions. The sputtering method of the target, CVD method, ion shower method or the like may be used. As the film, not only MoSi ₂ but also any material may be used as long as the material has a high melting point metal as a main component.

In this example, glass was used as the substrate. However, any substrate may be used as long as it is an insulating substrate, and the SiN _x layer is used as the insulating film. Any method may be used regardless of the method. Finally, MoSi ₂ / Al is used for the conductive film in this embodiment, but any material may be used as long as it has at least one conductor and covers a step of the contact hole of the insulating film.

Example 2 FIG. 2 shows a sectional view of a process in Example 2. Is almost the same as the process of Example 1, step in FIG (c) is, PH ₃ + Ar
When performing an RF discharge with a mixed gas of
Keep the ratio of ₃ / PH ₃ + Ar at 0.15 and at the end of discharge
MoSi ₂ is formed by changing the gas ratio of the mixed gas with respect to time so as to be 0.01. In this embodiment, the connection resistance is reduced by increasing the concentration of P ions at the interface between the aSi layer containing no impurities and MoSi _2, and the interface between MoSi ₂ and Al is reduced by setting the P ion concentration to 0 to reduce the wiring. Resistance can be reduced.

(Example 3) In this example, after the second SiN _X layer was selectively left only on the gate in each step (c) of Example 1 and Example 2, SiH _{4 was used.}
Plasma discharge with PH ₃ gas added to the gas
A step of depositing a second aSi layer containing an impurity having a thickness of about 00A is added, and the number of steps is increased as compared with the first and second embodiments, but the adhesion between the metal film and the n ⁺ aSi film is reduced. Improved, n ⁺ aSi delamination disappeared, yield improved, and connection resistance decreased
The TFT array characteristics are also improved.

Effect of the Invention The present invention is a new structure, unlike the conventional TFT structure,
If a TFT array using this structure is employed in a liquid crystal display device, the problem of n ⁺ aSi peeling, which is one of the causes of the failure of the TFT array, will be solved, and the yield will be improved. n ⁺ aSi
Semiconductor elements that do not form a film can shorten the CVD film-forming process while maintaining the ohmic connection between the aSi layer containing no impurities and the metal wiring, so they are rich in mass productivity and can be technically introduced into factories. . Further, the semiconductor device through the n ⁺ aSi film, the better the adhesion between the metal film and the n ⁺ aSi layer n ⁺ aSi peeling is eliminated to improve the yield, lowers yet, also the connection resistance TFT
The array characteristics are also improved. Further, the present invention can be applied to a MOS structure which requires ohmic connection of a semiconductor layer.

[Brief description of the drawings]

FIG. 1 is a process sectional view of a TFT of Example 1 of the present invention, FIG. 2 is a process sectional view of a TFT of Example 2 of the present invention, and FIG. 3 is a process sectional view of a conventional TFT. 2 ...... Cr layer, 3 ...... first SiN _X, 4 ...... aSi layer, 5 ......
Second SiN _x , 6... P ion-doped MoSi ₂ .

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinichiro Ishihara 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-61-184882 (JP, A) JP-A-62- 115868 (JP, A) JP-A-2-150067 (JP, A) JP-A-60-183770 (JP, A) JP-A-63-309923 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/336 H01L 29/786 H01L 29/40

Claims (1)

(57) [Claims] 1. A semiconductor device using an amorphous silicon layer containing almost no impurities, comprising an amorphous silicon layer containing impurities between a source / drain electrode containing Al and the amorphous silicon layer. Without interposing a porous silicon layer, a film containing a non-metal ion and containing a high melting point metal as a main component is interposed, and the non-metal ion is contained in a film containing a high melting point metal as a main component. A semiconductor device, wherein the concentration is increased as approaching the amorphous silicon layer.