JPS62124736A - Silicon thin-film and manufacture thereof - Google Patents

Silicon thin-film and manufacture thereof

Info

Publication number
JPS62124736A
JPS62124736A JP26406585A JP26406585A JPS62124736A JP S62124736 A JPS62124736 A JP S62124736A JP 26406585 A JP26406585 A JP 26406585A JP 26406585 A JP26406585 A JP 26406585A JP S62124736 A JPS62124736 A JP S62124736A
Authority
JP
Japan
Prior art keywords
silicon thin
thin film
film
substrate
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26406585A
Other languages
Japanese (ja)
Other versions
JPH0722130B2 (en
Inventor
Shinichiro Ishihara
伸一郎 石原
Ryuma Hirano
龍馬 平野
Michihiro Miyauchi
美智博 宮内
Takashi Hirao
孝 平尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP60264065A priority Critical patent/JPH0722130B2/en
Publication of JPS62124736A publication Critical patent/JPS62124736A/en
Publication of JPH0722130B2 publication Critical patent/JPH0722130B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To increase On currents by approximately one column by manufactur ing a TFT by using silicon thin-films deposited in the same device in order of a silicon thin-film under an amorphous state and a silicon thin-film consisting of a polycrystal from the substrate side. CONSTITUTION:A TFT is manufactured in such a manner that a first layer is brought to a low substrate temperature where a silicon thin-film 2 under an amorphous state is acquired when the first layer is deposited on a substrate 1 and a second layer is brought to a high substrate temperature where a silicon thin-film 3 in which crystalline orientation appears is obtained. The preparation may be conducted by changing a set temperature in the device with locations or at a proper time. Crystalline orientation distinctly appears on the surface of the thin-films having double layer structure by a function, in which the stress of the second polycrystalline thin-film 3 is absorbed by the first amorphous thin-film 2, by employing such a method, and the silicon thin-films with the smooth and uniform surface are obtained.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はシリコン薄膜を低圧熱分解法(以下LPCVD
法と略す)で作成する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to the production of silicon thin films by low-pressure pyrolysis (hereinafter referred to as LPCVD).
method).

従来の技術 絶縁基板上にシリコン薄膜を形成する方法は、例えばジ
ャパン ジェイ オプ アプライド フィジックス(J
pn J、of Applied Physics) 
 の22巻第7号1983年発行のL438ページに述
べられている。基板にはサファイアを用い、バッファ層
として直流四極スパッタ法で室温で作成されたアモルフ
ァスシリコン膜を用い、その上に1気圧で基板温度10
oo℃ でシリコンエビタキシャル膜を得ている。
Conventional techniques A method for forming a silicon thin film on an insulating substrate is, for example, developed by Japan J.O.P. Applied Physics (J.
pn J, of Applied Physics)
22, No. 7, 1983, page L438. The substrate is made of sapphire, and the buffer layer is an amorphous silicon film prepared at room temperature by DC quadrupole sputtering.
A silicone epitaxial film was obtained at oo°C.

一方、従来からLPCVD法によってシリコン薄膜を作
成する場合は、基板温度は600〜660℃程度で、温
度は故意には変えずに作成していた。
On the other hand, conventionally, when forming a silicon thin film by the LPCVD method, the substrate temperature was about 600 to 660° C., and the temperature was not intentionally changed.

また、気体状シリコン化合物を希釈してLPCVD法で
作成する場合、希釈ガスは組成が一定していた。
Further, when the gaseous silicon compound is diluted and created by the LPCVD method, the dilution gas has a constant composition.

発明が解決しようとする問題点 エピタキシャルシリコン薄膜を形成する場合は基板温度
が1oOo℃であるため、大型で均熱長の長い電気炉を
使用しなければならない。さらに半導体層を重ねる場合
、下側の半導体層中の不純物が成膜中に拡散し、微細な
素子構造を構成するこ−とが難しかった。
Problems to be Solved by the Invention When forming an epitaxial silicon thin film, since the substrate temperature is 100° C., it is necessary to use a large electric furnace with a long soaking length. Furthermore, when semiconductor layers are stacked, impurities in the lower semiconductor layer diffuse during film formation, making it difficult to construct a fine device structure.

これら欠点を解決するために開発されたのがLPCVD
法である。従来のLPCVD法では、アモルファス状の
シリコン薄膜を形成する場合はシリコン薄膜はなめらか
な表面を持っているが、アモルファス状のシリコンであ
るためキャリアの易動度が小さく、これで半導体素子を
作成すると特性が悪かった。一方、結晶の配向面がはっ
きりと現れるシリコン薄膜は、キャリアの易動度が大き
くなるが基板上に形成すると白河し、基板上にあるゴミ
、汚れ、キズ等で不均一性が強調され、特性のそろった
半導体素子を得るのが難しかった。
LPCVD was developed to solve these drawbacks.
It is the law. In the conventional LPCVD method, when forming an amorphous silicon thin film, the silicon thin film has a smooth surface, but since it is amorphous silicon, the mobility of carriers is low, and when semiconductor devices are created with this The characteristics were bad. On the other hand, silicon thin films in which crystal orientation planes clearly appear have high carrier mobility, but when formed on a substrate, they become white, and non-uniformity is accentuated by dust, dirt, scratches, etc. on the substrate, and the characteristics It was difficult to obtain semiconductor elements with uniform characteristics.

問題点を解決するだめの手段 本発明は、以上のような問題点を解決するため、表面が
なめらかで白河がなく、かつ結晶配向性がはっきり現れ
るシリコン薄膜を提供するものである。本発明かかるシ
リコン薄膜は、同一製造装置内において連続で作成でき
るものである。
Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a silicon thin film with a smooth surface, no white rivers, and clearly showing crystal orientation. The silicon thin film according to the present invention can be continuously produced within the same manufacturing apparatus.

シリコン薄膜の構成は少なくとも二層構造であり基板に
近い側ではアモルファス状の薄膜に、もう一方の層は結
晶配向性がはっきり現れる薄膜にするものである。この
構成を得る第1の手段は、基板に第1層を堆積する際ア
モルファス状のシリコン薄膜が得られる低い基板温度に
し、次に第2層では結晶配向性が現れるシリコン薄膜が
得られる高い基板温度にして作成するものである。これ
は、装置内の設定温度を場所によって変えるか時間をみ
はからって変えれば良い。
The silicon thin film has at least a two-layer structure, with the side near the substrate being an amorphous thin film, and the other layer being a thin film with clear crystal orientation. The first means to obtain this structure is to deposit the first layer on the substrate using a low substrate temperature that allows an amorphous silicon thin film to be obtained, and then to use a high substrate temperature for the second layer to obtain a silicon thin film that exhibits crystal orientation. It is created by adjusting the temperature. This can be done by changing the set temperature inside the device depending on the location or by changing it by taking time into account.

第2の手段は、シリコン化合物の希釈ガスを変える方法
である。同一の基板温度であってもHeの場合はアモル
ファス状の薄膜が得られ、N2の場合は多結晶薄膜が得
られることを発見したことに基づくもので、基板に近い
層はHeで希釈し、次にN2で希釈してシリコン薄膜を
二層堆積するものである。この方法も装置内の希釈ガス
を所定の時間で切り換えれば実現できるものである。
The second method is to change the dilution gas for the silicon compound. This is based on the discovery that even at the same substrate temperature, an amorphous thin film can be obtained with He, while a polycrystalline thin film can be obtained with N2.The layer near the substrate is diluted with He, Next, two layers of silicon thin film are deposited by diluting with N2. This method can also be realized by switching the diluent gas in the device at predetermined intervals.

作  用 このような方法を用いることにより、第2の多結晶薄膜
のストレスを第1のアモルファス薄膜が吸収するという
機能によって二層構造の薄膜の表面は結晶配向がはっき
り現れており、しかも表面がなめらかで均一なシリコン
薄膜が得られる。
Effect By using such a method, the first amorphous thin film absorbs the stress of the second polycrystalline thin film, so that the surface of the two-layered thin film has a clear crystal orientation, and moreover, the surface is A smooth and uniform silicon thin film can be obtained.

実施例 以下、本発明の実施例について説明する。Example Examples of the present invention will be described below.

実施例1 石英ガラス基板を用い、5iH420tzccM、He
60s+ccMの混合ガスをLPGVD装置内に導入し
、真空度が約0.5Torrになるよう排気量を制御す
る。基板温度を610℃の場合と630℃の場合2通り
行ない、それぞれ堆積時間は60分間であった。表面状
態は610℃の場合はなめらかであり、630℃の場合
は白河していた。注意深く洗浄しないと、630℃の場
合は堆積ムラが生じた。
Example 1 Using a quartz glass substrate, 5iH420tzccM, He
A mixed gas of 60 s+ccM is introduced into the LPGVD apparatus, and the exhaust amount is controlled so that the degree of vacuum is approximately 0.5 Torr. The deposition time was 60 minutes in each case, with the substrate temperature being 610°C and 630°C. The surface condition was smooth at 610°C, and white at 630°C. Unless carefully cleaned, uneven deposition occurred at 630°C.

X線回折から610’Cの場合は何らピークは現れなか
ったが、630℃の場合は(220)等いくつかのピー
クが現れて多結晶であることがわかった。
From X-ray diffraction, no peak appeared at 610'C, but several peaks such as (220) appeared at 630°C, indicating that it was polycrystalline.

石英ガラス基板、S 1H420sccM 、真空度0
.5Torr 、基板温度610℃は変えずに、S L
H4の希釈ガスとしてN2ガスe o sccMを用い
ると、X線回折パターンに(220)等のピークが発生
し、多結晶であることがわかった。
Quartz glass substrate, S 1H420sccM, degree of vacuum 0
.. 5Torr, without changing the substrate temperature of 610℃, S L
When N2 gas e o sccM was used as a diluent gas for H4, peaks such as (220) appeared in the X-ray diffraction pattern, indicating that it was polycrystalline.

このような事実をもとに本発明による二層構造のシリコ
ン薄膜を作成し半導体素子の応用例としてTPTを作成
した。以下その方法を示す。
Based on these facts, a two-layer silicon thin film according to the present invention was fabricated, and a TPT was fabricated as an application example of a semiconductor device. The method is shown below.

S 1H420sccM、He 60 sccM、真空
度0.6Torr 、石英ガラス基板1の基板温度が6
10℃の条件で1〜5分間アモルファス状シリコン薄膜
2を20−500人堆積し、次に基板温度を630〜6
50℃に上昇して6o分間多結晶状シリコン薄膜3を約
5OOQ人堆積した。X線回折パターンから、(220
)のピークは630℃〜650℃で単一層を堆積させた
ピークよりも大きなピークが得られ、しかも、シリコン
薄膜表面は白河せずなめらかであった。電気炉に温度勾
配を設けて基板を移動させることによって基板温度を変
える方法、電気炉自体の温度を変える方法、いずれの方
法でも同様な薄膜が得られた。
S 1H 420sccM, He 60sccM, degree of vacuum 0.6Torr, substrate temperature of quartz glass substrate 1 6
Deposit 20 to 500 amorphous silicon thin films 2 for 1 to 5 minutes at 10°C, then lower the substrate temperature to 630 to 60°C.
The temperature was increased to 50° C., and approximately 500000000 polycrystalline silicon thin film 3 was deposited for 60 minutes. From the X-ray diffraction pattern, (220
) was obtained at 630° C. to 650° C., which was larger than the peak obtained when a single layer was deposited, and the silicon thin film surface was smooth without white spots. Similar thin films were obtained using both methods: changing the substrate temperature by creating a temperature gradient in the electric furnace and moving the substrate, and changing the temperature of the electric furnace itself.

次にシリコン薄膜3の表面を200〜300人酸化させ
保護膜とした後、島状にシリコン薄膜2゜3を工・シチ
ングし、200〜300人の保護酸化膜を除いた後、シ
リコン薄膜2を酸化させてゲート酸化膜11を作成する
(第2図(a))。
Next, the surface of the silicon thin film 3 is oxidized by 200 to 300 layers to form a protective film, and then an island-shaped silicon thin film 2.3 is etched, and after removing the 200 to 300 protective oxide film, the silicon thin film 2 is oxidized to form a gate oxide film 11 (FIG. 2(a)).

ゲート酸化膜11にソース、ドレイン電極用のコンタク
トホール12,13をあけ、リンをそのホールからイオ
ン注入する。これは電極とシリコン薄膜3とのオーミッ
ク接触を確保するためである。イオン注入した後熱処理
すると、n型佃域14.15ができる。これに、金属蒸
着膜例えばAl蒸着膜によってゲート電極16およびソ
ース。
Contact holes 12 and 13 for source and drain electrodes are formed in the gate oxide film 11, and phosphorus ions are implanted through the holes. This is to ensure ohmic contact between the electrode and the silicon thin film 3. When heat treatment is performed after ion implantation, n-type pocket regions 14 and 15 are formed. A gate electrode 16 and a source are formed on this by a metal evaporation film, for example, an Al evaporation film.

ドレイン電極17.18を形成する。(第2図(b))
以上のようにしてTPTを作成した。このように二重構
造で、しかも同一製造装置内で作成したシリコン薄膜を
用いたTPTは、従来のシリコン薄膜を用いて作成した
TPTに比べ、大きな○N10FF  比が得られた。
Drain electrodes 17 and 18 are formed. (Figure 2(b))
TPT was created as described above. In this way, the TPT using a silicon thin film having a double structure and produced in the same manufacturing equipment had a larger ○N10FF ratio than the TPT produced using a conventional silicon thin film.

実施例2 SiH420sccM、He 60 sacM、真空度
0.5Torr  、基板温度610℃の条件で1〜6
分間アモルファス状シリコン薄膜を20〜500人堆積
し、次にHe 60 sccMの代わりにN2を60s
ccM流しながら、60分間多結晶のシリコン薄膜を約
4000人堆積した。X線回折パターンから実施例3と
同様(220)の大きなピークが観察された。希釈ガス
をHeからN2に変えるとき、5lH4を止めた場合す
なわち堆積を中断した場合も、HeからN2に序々にこ
れら混合比を変えながら堆積を中断しなかった場合も、
同様なシリコン薄膜が得られた。また、HeやN2にN
2を混合させた場合S iH4との混合比によっては堆
積速度が低下したが、X線回折パターンは同様なものが
得られ、表面はなめらかであった。
Example 2 1 to 6 under the conditions of SiH 420 sccM, He 60 sacM, vacuum degree 0.5 Torr, and substrate temperature 610°C
Deposit an amorphous silicon thin film for 20-500 min, then add N2 instead of He 60 sccM for 60 s.
Approximately 4,000 polycrystalline silicon thin films were deposited for 60 minutes while flowing ccM. A large peak (220) similar to that in Example 3 was observed in the X-ray diffraction pattern. When changing the diluent gas from He to N2, either when 5lH4 was stopped, that is, the deposition was interrupted, or when the mixing ratio was gradually changed from He to N2 but the deposition was not interrupted.
A similar silicon thin film was obtained. In addition, He and N2
When 2 was mixed, the deposition rate decreased depending on the mixing ratio with SiH4, but the same X-ray diffraction pattern was obtained and the surface was smooth.

ナオ、SiHの代わりに、S i)(cg3. S i
H,、C12゜5iH3C1!、Si2H6を用いても
、堆積速度は変わるものの実施例で示したような同様な
薄膜が得られた。
Nao, instead of SiH, S i) (cg3. Si
H,,C12゜5iH3C1! , Si2H6 were used to obtain thin films similar to those shown in the examples, although the deposition rate was different.

このようにして作成したシリコン薄膜を用いても実施例
1で示したのと同様な特性を持つTFTが作成された。
A TFT having characteristics similar to those shown in Example 1 was also produced using the silicon thin film thus produced.

発明の効果 基板側からアモルファス状のシリコン薄膜、多結晶より
なるシリコン薄膜の順に同一装置内で堆積されたシリコ
ン薄膜を用いてTPT (薄膜トランジスタ)を作成す
ると、キャリアの易動度が大きくなったために、ON電
流が約1桁増加した。
Effects of the invention When a TPT (thin film transistor) is created using silicon thin films deposited in the same apparatus in the order of an amorphous silicon thin film and a polycrystalline silicon thin film from the substrate side, carrier mobility increases. , the ON current increased by about one order of magnitude.

また装置を一台使用するだけで、二層構造を持つ良質の
シリコン薄膜を作成することができるため工業的にも有
意義である。
Also, it is industrially significant because it is possible to create a high-quality silicon thin film with a two-layer structure by using only one device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例による二層構造のシリコン薄
膜を示す図、第2図は本発明によるシリコン薄膜を用い
てTPTを作成するプロセスを示す図である。 2・・・・・・アモルファス状シリコン薄膜、3・・・
・・・多結晶状シリコン薄膜、11・・・・・・ゲート
酸化膜、16・・・・・・ゲート電極、17.18・・
・・・・ソース、ドレイン電極。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第2図 /      ZJ//
FIG. 1 is a diagram showing a two-layer silicon thin film according to an embodiment of the present invention, and FIG. 2 is a diagram showing a process for producing a TPT using the silicon thin film according to the present invention. 2... Amorphous silicon thin film, 3...
... Polycrystalline silicon thin film, 11 ... Gate oxide film, 16 ... Gate electrode, 17.18 ...
...Source and drain electrodes. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2/ZJ//

Claims (3)

【特許請求の範囲】[Claims] (1)基板上に、低圧熱分解法によって作成された、X
線、電子線等による回折パターンから結晶面を示すピー
クが現れない第1のシリコン薄膜、上記第1のシリコン
薄膜上に少なくともX線または電子線等による回折パタ
ーンから結晶面を示すピークが現れる低圧熱分解法によ
って作成された第2のシリコン薄膜を少なくとも構成要
素とすることを特徴とするシリコン薄膜。
(1) X created on the substrate by low pressure pyrolysis method
A first silicon thin film in which a peak indicating a crystal plane does not appear in a diffraction pattern by an X-ray, an electron beam, etc., and a low pressure at which a peak indicating a crystal plane appears in a diffraction pattern by at least an X-ray, an electron beam, etc. on the first silicon thin film; A silicon thin film characterized in that at least a constituent element thereof is a second silicon thin film created by a pyrolysis method.
(2)基板上に気体状シリコン化合物を低圧で熱分解し
て少なくとも2層よりなるシリコン薄膜を作成するに際
し、上記基板に近い側のシリコン薄膜がアモルファス状
になり、もう一方の膜が多結晶になるよう互いの膜の熱
分解温度を異ならせて作成することを特徴とするシリコ
ン薄膜の作成方法。
(2) When creating a silicon thin film consisting of at least two layers on a substrate by thermally decomposing a gaseous silicon compound at low pressure, the silicon thin film on the side closer to the substrate becomes amorphous, and the other film becomes polycrystalline. A method for producing a silicon thin film, characterized in that the films are produced at different thermal decomposition temperatures so that the films have different thermal decomposition temperatures.
(3)基板上に気体状シリコン化合物を低圧で熱分解し
て少なくとも2層よりなるシリコン薄膜を作成するに際
し、上記基板に近い側のシリコン薄膜がアモルファス状
になるよう上記気体状シリコン化合物をHeまたはHe
とH_2との混合ガスで希釈し、もう一方の膜が多結晶
になるよう上記気体状シリコン化合物をN_2またはN
_2とH_2との混合ガスで希釈することを特徴とする
シリコン薄膜の作成方法。
(3) When creating a silicon thin film consisting of at least two layers on a substrate by thermally decomposing the gaseous silicon compound at low pressure, the gaseous silicon compound is heated using He so that the silicon thin film on the side closer to the substrate becomes amorphous. or He
The above gaseous silicon compound is diluted with a mixed gas of N_2 or N_2 so that the other film becomes polycrystalline.
A method for creating a silicon thin film, characterized by diluting it with a mixed gas of _2 and H_2.
JP60264065A 1985-11-25 1985-11-25 Silicon thin film and method for producing the same Expired - Lifetime JPH0722130B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60264065A JPH0722130B2 (en) 1985-11-25 1985-11-25 Silicon thin film and method for producing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60264065A JPH0722130B2 (en) 1985-11-25 1985-11-25 Silicon thin film and method for producing the same

Publications (2)

Publication Number Publication Date
JPS62124736A true JPS62124736A (en) 1987-06-06
JPH0722130B2 JPH0722130B2 (en) 1995-03-08

Family

ID=17398035

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60264065A Expired - Lifetime JPH0722130B2 (en) 1985-11-25 1985-11-25 Silicon thin film and method for producing the same

Country Status (1)

Country Link
JP (1) JPH0722130B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01152719A (en) * 1987-12-10 1989-06-15 Sanyo Electric Co Ltd Formation of soi structure
US5913125A (en) * 1992-06-26 1999-06-15 International Business Machines Corporation Method of controlling stress in a film
JP2009164569A (en) * 2007-09-11 2009-07-23 Applied Materials Inc Dopant using controlled crystal structure, polycrystalline silicon film using multi-layer silicon film, and adjustment of stress of ambient layer
JP2016539495A (en) * 2013-10-21 2016-12-15 ユ−ジーン テクノロジー カンパニー.リミテッド Method and apparatus for depositing amorphous silicon film

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51128268A (en) * 1975-04-30 1976-11-09 Sony Corp Semiconductor unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51128268A (en) * 1975-04-30 1976-11-09 Sony Corp Semiconductor unit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01152719A (en) * 1987-12-10 1989-06-15 Sanyo Electric Co Ltd Formation of soi structure
US5913125A (en) * 1992-06-26 1999-06-15 International Business Machines Corporation Method of controlling stress in a film
JP2009164569A (en) * 2007-09-11 2009-07-23 Applied Materials Inc Dopant using controlled crystal structure, polycrystalline silicon film using multi-layer silicon film, and adjustment of stress of ambient layer
JP2016539495A (en) * 2013-10-21 2016-12-15 ユ−ジーン テクノロジー カンパニー.リミテッド Method and apparatus for depositing amorphous silicon film

Also Published As

Publication number Publication date
JPH0722130B2 (en) 1995-03-08

Similar Documents

Publication Publication Date Title
JPH03133176A (en) Silicon carbide semiconductor device and manufacture thereof
KR20010023407A (en) Method for forming monocrystalline silicon layer, method for manufacturing semiconductor device, and semiconductor device
JPS62124736A (en) Silicon thin-film and manufacture thereof
KR19990013304A (en) How to crystallize amorphous membrane
KR100250020B1 (en) Forming method of polysilicon thin film
KR100469503B1 (en) How to crystallize amorphous film
JPH04245419A (en) Manufacture of semiconductor substrate
JPS63119576A (en) Thin film transistor
JP3535465B2 (en) Method for manufacturing semiconductor device
JPS59134819A (en) Manufacture of semiconductor substrate
KR960004902B1 (en) Preparation of polycrystalline silicon thin film
JPS63307776A (en) Thin-film semiconductor device and manufacture thereof
JPS63250178A (en) Manufacture of thin film semiconductor device
JP4585464B2 (en) Manufacturing method of semiconductor device
KR960026967A (en) Polycrystalline Thin Film Transistor and Manufacturing Method Thereof
JPH0319340A (en) Manufacture of semiconductor device
JPH03200319A (en) Formation of poly-crystalline silicon
KR100472855B1 (en) Polycrystalline silicon thin film manufacturing method of semiconductor device
KR100709282B1 (en) The manafacturing method of the silicon thin film transistor
JP2503626B2 (en) Method of manufacturing MOS field effect transistor
JPH0281421A (en) Forming method for polycrystalline silicon film
JPS63192223A (en) Manufacture of semiconductor device
JPS6164118A (en) Manufacture of semiconductor device
JPH0496219A (en) Formation of polycrystalline silicon semiconductor film
JPH036022A (en) Formation of multilayer insulating film