JP2000216395A - Method and apparatus for manufacture of thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide high throughput in the manufacturing process of a reverse staggered thin-film transistor for realizing low cost of a liquid crystal display. SOLUTION: A phosphine plasma treatment is executed to a transparent insulating substrate 1, on which an amorphous silicon film 4 is formed (c). Then, a metal film is formed (d). Thereby, without separately forming an n-type amorphous silicon film 8, the n-type amorphous silicon film 8 is automatically formed in a source/drain region. Thereby, the yield and the process throughput in the formation of a thin-film transistor can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor and a manufacturing apparatus for realizing the method, and more particularly, to a method for manufacturing a thin film transistor used for an active matrix type liquid crystal display and a method for manufacturing the same. Related to a manufacturing apparatus.

[0002]

2. Description of the Related Art In recent years, research and development of a thin film transistor used as a device for driving each pixel of a liquid crystal flat panel display have been actively conducted. With the spread of notebook computers, the demand for liquid crystal displays has rapidly increased, and the demand for displays for large monitors has also been combined.
There is a demand for improved productivity and higher performance. It is the thin film transistor substrate manufacturing process that limits the productivity of the liquid crystal display manufacturing, and one of the important factors that determines the performance (definition and the like) of the liquid crystal display is the element performance of the thin film transistor. Therefore, it will become important in the future how to manufacture high performance thin film transistors with high productivity.

In an inverted staggered thin film transistor, an n-type amorphous silicon film is formed between a source / drain electrode and an amorphous silicon film serving as an active layer in order to form an ohmic contact in a source / drain region. It must be formed. In the conventional method of manufacturing an inverted staggered thin film transistor, the plasma C
An n-type amorphous silicon film is formed by using the VD method. For example, JP-A-5-304171, JP-A-9-223800 and JP-A-10-12882 disclose that an n-type amorphous silicon film is formed by plasma CV.
A method for forming a film using the D method is described.

[0004] A conventional method of manufacturing a general inverted staggered thin film transistor will be described below with reference to the above-mentioned Japanese Patent Application Laid-Open No. 5-30.
The method disclosed in Japanese Patent No. 4171 will be described with reference to FIG.

First, as shown in FIG. 5A, a gate electrode metal film is formed on a transparent insulating substrate 1, and the metal film is patterned into a desired shape to form a gate electrode 2. .

Thereafter, as shown in FIG. 5B, a silicon nitride film 3, an amorphous silicon film 4, and an n-type amorphous silicon film 8 as a gate insulating film are formed on the gate electrode 2 by plasma. Films are sequentially formed by a CVD method or the like.

Next, as shown in FIG. 5C, the n-type amorphous silicon film 8 and the amorphous silicon film 4 are patterned into a desired island shape.

After a metal film for a source / drain electrode is formed, the source / drain electrode 7 is formed by patterning the metal film into a desired shape as shown in FIG.

Finally, the n-type amorphous silicon film 8 on the channel is removed by etching to obtain a structure shown in FIG.
A thin film transistor as shown in (e) is completed.

In order to manufacture a thin film transistor with high yield, it is desirable to reduce the number of film forming steps as much as possible. If a thin film transistor can be realized without individually forming an n-type amorphous silicon film, the number of steps can be reduced. Thereby, it is possible to improve the yield and reduce the manufacturing cost.

A method for realizing an inverted staggered thin film transistor without individually forming an n-type amorphous silicon film is disclosed in Japanese Patent Application Laid-Open No. 2-163971. According to this method, the use of a metal containing nickel phosphide for the source / drain electrodes makes it unnecessary to form an n-type amorphous silicon film. The source / drain electrodes are formed by a sputtering method using nickel phosphide and another metal or a mixture thereof as a target material. When characteristics of a thin film transistor formed by using such a method are measured, it is described that characteristics equivalent to those of a thin film transistor formed by individually forming an n-type amorphous silicon film are obtained.

Japanese Patent Application Laid-Open No. 9-331067 discloses a method of continuously forming an amorphous silicon film, a gate insulating film and an aluminum film for forming a gate wiring on a substrate in a vacuum. I have.

[0013]

However, according to the method described in Japanese Patent Application Laid-Open No. 2-163971, since the phosphorus is present as an impurity in the source / drain electrode metal, the resistance of the source / drain electrode is reduced. A new problem of increase occurs.

This causes a signal delay due to an increase in source / drain wiring resistance particularly when a large-sized liquid crystal display is realized, and adversely affects display.

According to the method described in Japanese Patent Application Laid-Open No. 9-331067, since the amorphous silicon film is formed at the bottom, the amorphous silicon film must be formed into an n-type. First, phosphorus must be implanted into the amorphous silicon film, and it is difficult to eliminate the necessity of individually forming an n-type amorphous silicon film.

The present invention has been made in view of the above-mentioned problems of the prior art, and it has been found that phosphorus does not exist as an impurity in the source / drain electrode metal and n
It is an object of the present invention to provide a method and an apparatus for manufacturing a type thin film transistor in which it is not necessary to individually form a shaped amorphous silicon film.

[0017]

In order to achieve the above object, according to the present invention, a first step of forming an amorphous silicon film on a substrate and a step of forming the amorphous silicon film are described. A second step of subjecting the processed substrate to a plasma treatment including at least a group V element, and a third step of depositing a metal film on the plasma-treated amorphous silicon film. A manufacturing method is provided.

According to the method, in the first step, an amorphous silicon film is formed on a substrate. Thereafter, at the time of the plasma treatment in the second step, the group V element diffuses into the surface portion of the amorphous silicon film or deposits on the surface of the amorphous silicon film. Further, at the time of forming the metal film in the third step, the V deposited on the surface of the amorphous silicon film
Group element diffuses into the surface layer of the amorphous silicon film, and in these second and third steps, an n-type amorphous silicon film is automatically formed between the amorphous silicon film and the metal film. Formed. That is, according to the present method, the group V element does not exist as an impurity in the metal serving as the source / drain electrodes, and there is no need to separately form an n-type amorphous silicon film.

Claims 2 and 3 relate to the first to third steps according to claim 1, respectively, in which the first step and the second step are performed without breaking the vacuum, that is, the semiconductor device is oxidized. A manufacturing method, the first step and the second step, wherein the manufacturing method is performed without being exposed to the atmosphere, and the second step and the third step are performed without exposing the semiconductor device to the oxidizing atmosphere. And a third step of providing the semiconductor device without exposing the semiconductor device to an oxidizing atmosphere.

According to these methods, the same effect as the method according to claim 1 can be obtained. In particular, by performing each step without exposing the semiconductor device to an oxidizing atmosphere, a cleaner interface can be formed.

The oxidizing atmosphere includes the air.

According to a fourth aspect of the present invention, there is provided a manufacturing method using a phosphine plasma treatment as the plasma treatment including the group V element according to the first to third aspects.

According to this method, the same effects as those of the first to third aspects can be obtained.

A first step of sequentially forming an insulating film and an amorphous silicon film over the gate electrode formed on the substrate, and the step of forming the insulating film and the amorphous silicon film under reduced pressure. A second step of performing a phosphine plasma treatment on the substrate on which the film is sequentially formed, and forming a metal film on the amorphous silicon film subjected to the phosphine plasma treatment, and forming the metal film on a source electrode and a drain electrode. A third step of patterning the amorphous silicon film; and a fourth step of patterning the amorphous silicon film.

According to this method, the same effects as those of the first to fourth aspects can be obtained.

According to a sixth aspect of the present invention, there is provided a first step of sequentially forming an insulating film and an amorphous silicon film so as to cover a gate electrode formed on a substrate, and a second step of patterning the amorphous silicon film. A step of performing a phosphine plasma treatment under reduced pressure on the substrate on which the amorphous silicon film has been patterned, and forming a metal film on the substrate having been subjected to the phosphine plasma treatment. And a fourth step of patterning the semiconductor device into a shape of a source electrode and a drain electrode.

According to this method, the same effects as those of the first, third, and fourth aspects can be obtained.

According to a fifth aspect of the present invention, a method of manufacturing a semiconductor device further comprises the steps of:
A fifth step of removing an unnecessary portion of the amorphous silicon film subjected to the phosphine plasma treatment between the source electrode and the drain electrode can be provided.

Further, as described in claim 8,
The fifth step can be performed simultaneously by patterning the metal film for the source electrode and the drain electrode by a dry etching method or a wet etching method.

That is, by performing dry etching or wet etching on the metal film serving as the source / drain electrodes, an unnecessary portion of the extremely thin n-type amorphous silicon film can be removed at the same time. Accordingly, a step for removing or modifying an unnecessary portion of the n-type amorphous silicon film, for example, an etching step or a plasma processing step can be reduced.

Instead of the method described in claim 7 or 8,
As described in claim 9, by performing a plasma treatment on an unnecessary portion of the amorphous silicon film between the source electrode and the drain electrode, the unnecessary portion can be modified into an insulating film.

According to a tenth aspect of the present invention, a process of exposing the amorphous silicon film formed on the substrate to phosphine plasma and a process of forming a metal film on the amorphous silicon film subjected to the phosphine plasma process are performed. Another object of the present invention is to provide a semiconductor manufacturing apparatus capable of continuously performing a semiconductor device without exposing the semiconductor device to an oxidizing atmosphere.

According to this semiconductor manufacturing apparatus,
The method of manufacturing a semiconductor device described in 2 or 3 can be performed.

In another embodiment, a process for forming an amorphous silicon film on a substrate, a process for exposing the amorphous silicon film to a phosphine plasma process, and a process for forming a metal film on the amorphous silicon film are provided. A semiconductor manufacturing apparatus capable of continuously performing processing without exposing the semiconductor device to an oxidizing atmosphere.

With this semiconductor manufacturing apparatus, the method of manufacturing a semiconductor device according to claim 1 or 3 can be implemented.

In a twelfth aspect of the present invention, a first chamber for exposing the substrate to phosphine plasma, a second chamber for forming a metal film on the substrate, and a first chamber and a second chamber are provided. A semiconductor manufacturing apparatus comprising: a gate valve connected between the gate valves while maintaining a vacuum.

According to this semiconductor manufacturing apparatus,
The method of manufacturing a semiconductor device described in 2 or 3 can be performed.

A thirteenth aspect includes a first chamber for heating the substrate, a second chamber for exposing the substrate to phosphine plasma, and a third chamber for forming a metal film on the substrate. A first gate valve that connects the first chamber and the second chamber while maintaining a vacuum, and a connection that maintains the second chamber and the third chamber while maintaining a vacuum And a second gate valve.

According to this semiconductor manufacturing apparatus,
The method of manufacturing a semiconductor device described in 2 or 3 can be performed.

[0040] Claim 14 includes a first chamber for heating the substrate, a second chamber for exposing the substrate to phosphine plasma, and a third chamber for forming a metal film on the substrate. A fourth chamber as a space for transporting a substrate, a first gate valve for connecting the first chamber and the fourth chamber while maintaining a vacuum, a second chamber and a fourth A second gate valve that connects to the chamber while maintaining a vacuum,
There is provided a semiconductor manufacturing apparatus comprising: a third gate valve that connects a third chamber and a fourth chamber while maintaining a vacuum.

According to this semiconductor manufacturing apparatus,
The method of manufacturing a semiconductor device described in 2 or 3 can be performed.

According to a fifteenth aspect, a first chamber for heating a substrate, a second chamber for forming a gate insulating film on the substrate, and an amorphous silicon film on the substrate are formed. A third chamber for exposing the substrate to phosphine plasma, a fifth chamber for forming a metal film on the substrate, a first chamber and a second chamber. A first gate valve that connects while maintaining a vacuum, a second gate valve that connects between the second and third chambers while maintaining a vacuum, a third chamber and a third A third gate valve that connects the fourth chamber while maintaining a vacuum, and a fourth gate valve that connects the fourth chamber and the fifth chamber while maintaining a vacuum. Semiconductor manufacturing equipment Subjected to.

According to this semiconductor manufacturing apparatus,
The method of manufacturing a semiconductor device described in 2 or 3 can be performed.

According to a sixteenth aspect, a first chamber for heating a substrate, a second chamber for forming a gate insulating film on the substrate, and an amorphous silicon film are formed on the substrate. A third chamber for exposing the substrate to phosphine plasma, a fifth chamber for forming a metal film on the substrate, and a fourth chamber for transferring the substrate. Sixth chamber, a first gate valve that connects the first chamber and the sixth chamber while maintaining a vacuum, and while maintaining a vacuum between the second chamber and the sixth chamber A second gate valve to connect, a third gate valve to connect while maintaining a vacuum between the third chamber and the sixth chamber, and a vacuum between the fourth chamber and the sixth chamber Maintain while contacting Providing a fourth gate valve, a fifth gate valve connecting while maintaining a vacuum between the fifth chamber and sixth chamber, a semiconductor manufacturing apparatus comprising a to.

According to this semiconductor manufacturing apparatus,
The method of manufacturing a semiconductor device described in 2 or 3 can be performed.

[0046]

Embodiments of the present invention will be described below.

FIG. 1 is a diagram showing each step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

First, as shown in FIG. 1A, a gate electrode 2 is formed by patterning a metal for a gate electrode formed on a transparent insulating substrate 1 into a desired shape, and then a plasma CVD method or the like is performed. The gate insulating film 3 and the amorphous silicon film 4 are sequentially formed on the transparent insulating substrate 1 by using.

Subsequently, as shown in FIG. 1B, the amorphous silicon film 4 is patterned into a desired island shape.

Next, as shown in FIG. 1C, phosphorus 6 is deposited on the surface of the amorphous silicon film 4 by exposing the transparent insulating substrate 1 to phosphine plasma 5. At this time, phosphorus may diffuse into the surface layer of the amorphous silicon film 4.

Thereafter, a source / drain electrode metal film is formed by a sputtering method or the like, and is patterned into a desired shape to obtain a source / drain electrode 7 as shown in FIG.

Also during this sputter deposition, the phosphorus 6 diffuses into the surface layer of the amorphous silicon film 4 and the n-type amorphous silicon layer 8 is automatically formed.

Here, the phosphine plasma treatment (FIG. 1)
(C)) and the metal sputter deposition for the source / drain electrodes (FIG. 1 (d)) are performed without breaking the vacuum,
A process in which the semiconductor device is continuously exposed without being exposed to the oxidizing atmosphere is also possible, and a process in which the transparent insulating substrate 1 is exposed to the oxidizing atmosphere or the atmosphere by breaking the vacuum between the two processes is also available. It is possible. According to the former process in which both processes are continuously performed, the throughput of the process can be improved. However, no matter which process is used, the characteristics of the completed thin film transistor are almost the same.

Finally, as shown in FIG. 1E, the unnecessary n-type amorphous silicon film 8 between the source and drain electrodes is removed by etching to complete the thin film transistor.

In the first embodiment, finally, a step of etching and removing the unnecessary n-type amorphous silicon film 8 between the source and drain electrodes (FIG. 1E).
In the step shown in FIG. 1D, the unnecessary n-type amorphous silicon film 8 between the source and drain electrodes can be removed by etching simultaneously with the etching of the metal film. . That is, FIG. 1D and FIG.
The two steps shown in (e) can be performed in one step.
This is because the automatically formed n-type amorphous silicon layer 8 has a very small thickness. In this case, there is no need for a separate step for etching and removing the unnecessary n-type amorphous silicon film 8 between the source and drain electrodes.

As described above, according to the method of manufacturing a semiconductor device according to the present embodiment, an inverted staggered thin film transistor can be manufactured without individually forming an n-type amorphous silicon film. .

In the first embodiment, after the amorphous silicon film 4 is formed into a desired island shape (FIG. 1)
(B)), phosphine plasma treatment (FIG. 1 (c)), metal sputter deposition and patterning thereof (FIG. 1 (d)) were performed in this order, but as in the second embodiment described below. Alternatively, the processes can be performed in the order of film formation of the amorphous silicon film 4, phosphine plasma treatment, metal sputter film formation and patterning, and island formation of the amorphous silicon film.

Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described.

First, as shown in FIG. 2A, a gate electrode 2 is formed by patterning a gate electrode metal film formed on a transparent insulating substrate 1 into a desired shape.

Thereafter, a gate insulating film 3 and an amorphous silicon film 4 are formed on the transparent insulating substrate 1 by using a plasma CVD method or the like.

After that, as shown in FIG. 2B, a phosphine plasma treatment for exposing the transparent insulating substrate 1 to the phosphine plasma 5 is performed, and
Is deposited. At this time, phosphorus may diffuse into the surface layer of the amorphous silicon film 4.

After the phosphine plasma treatment, FIG.
As shown in (c), a source film is formed on the amorphous silicon film 4.
The drain electrode metal film 7 is formed by a sputtering method or the like.

Also during this sputtering film formation, the phosphorus 6 diffuses into the surface layer of the amorphous silicon film 4 and the n-type amorphous silicon layer 8 is automatically formed.

Here, the formation of the gate insulating film 3, the formation of the amorphous silicon film 4, phosphine plasma treatment,
It is possible to perform a process in which the four steps of sputtering film formation of the drain electrode metal film 7 are continuously performed without exposing the semiconductor device to an oxidizing atmosphere, and the process is transparent between any of the steps. A process in which the insulating substrate 1 is once exposed to the atmosphere is also possible. In the case of a process in which four steps are continuously performed, the throughput of the process can be improved. However, no matter which process you create,
The characteristics of the completed thin film transistor are almost the same.

Thereafter, as shown in FIG. 2D, the metal film formed by the sputtering method was patterned into a desired source / drain electrode shape to form the source / drain electrode 7 and to make it n-type. The amorphous silicon film 8 and the amorphous silicon film 4 are patterned into a desired island shape.

Finally, the unnecessary n-type amorphous silicon film 8 is removed by etching to complete a thin film transistor as shown in FIG.

In the second embodiment, the step of etching and removing the unnecessary n-type amorphous silicon film 8 between the source and drain electrodes is finally performed.
In the step (d), when the metal film is etched, the unnecessary n-type amorphous silicon film 8 between the source and drain electrodes can be simultaneously removed by etching.
That is, the two steps of FIG. 2D and FIG. 2E can be performed in one step. This is the automatically formed n
This is because the thickness of the formed amorphous silicon layer 8 is very small. In this case, there is no need for a separate step for etching and removing the unnecessary n-type amorphous silicon film 8 between the source and drain electrodes.

As described above, according to the method of manufacturing a semiconductor device according to the present embodiment, an inverted staggered thin film transistor can be manufactured without individually forming an n-type amorphous silicon film.

In the first embodiment, the phosphine plasma treatment and the metal sputtering film formation can be performed without breaking the vacuum, that is, without exposing the semiconductor device to an oxidizing atmosphere. Hereinafter, as a third embodiment of the present invention, a semiconductor manufacturing apparatus for performing the method of manufacturing a semiconductor device according to the first embodiment will be described.

FIG. 3A shows a first example of a semiconductor device manufacturing apparatus according to the third embodiment.

The semiconductor device manufacturing apparatus in the first example includes a substrate heating chamber 10 as a first chamber for heating a substrate and a second phosphine plasma treatment for exposing the substrate to phosphine plasma. A phosphine plasma processing chamber 11 as a chamber, a metal deposition chamber 12 as a third chamber for depositing a source / drain electrode metal film on a substrate,
Substrate heating chamber 10 and phosphine plasma processing chamber 1
1 and a second gate valve 9b that connects the phosphine plasma processing chamber 11 and the metal film formation chamber 12 while maintaining a vacuum. Become.

In this manufacturing apparatus, first, the substrate is heated in the substrate heating chamber 10, and thereafter, the substrate is transferred to the phosphine plasma processing chamber 11, and the phosphine plasma processing is performed in the phosphine plasma processing chamber 11. Further, the substrate is transferred to the metal film forming chamber 12, and a metal for source / drain electrodes is formed in the metal film forming chamber 12.

During the transfer of the substrate between the substrate heating chamber 10, the phosphine plasma processing chamber 11, and the metal film formation chamber 12, the vacuum state is broken by the first gate valve 9a and the second gate valve 9b. Has been maintained without.

Note that the semiconductor device manufacturing apparatus in the first example need not necessarily have the substrate heating chamber 10. The substrate may be heated by means separate from the substrate heating chamber 10, and then the heated substrate may be transferred into the phosphine plasma processing chamber 11.

The semiconductor device manufacturing apparatus of the first example shown in FIG. 3A is an example of an in-line type apparatus. On the other hand, as an example of a single-wafer apparatus, FIG. 3B shows an apparatus for manufacturing a semiconductor device according to a second example of the third embodiment.

The semiconductor device manufacturing apparatus of the second example includes a substrate heating chamber 10 as a first chamber for heating a substrate and a second phosphine plasma treatment for exposing the substrate to phosphine plasma. A phosphine plasma processing chamber 11 as a chamber, a metal film forming chamber 12 as a third chamber for forming a metal film for source / drain electrodes on a substrate, a substrate heating chamber 10, a phosphine plasma processing chamber 11
And a substrate transfer chamber 13 as a fourth chamber as a space for transfer between the metal film formation chambers 12, the substrate heating chamber 10, and the substrate transfer chamber 13.
A first gate valve 16a connecting the phosphine plasma processing chamber 11 and the substrate transfer chamber 13 while maintaining a vacuum, a first gate valve 16a connecting the phosphine plasma processing chamber 11 and the substrate transfer chamber 13 while maintaining a vacuum, A third gate valve 16c that connects the film forming chamber 12 and the substrate transfer chamber 13 while maintaining a vacuum.

This manufacturing apparatus is used as follows.

First, the substrate is heated in the substrate heating chamber 10, the substrate is transferred to the phosphine plasma processing chamber 11 through the substrate transfer chamber 13, and phosphine plasma processing is performed in the phosphine plasma processing chamber 11.

Thereafter, the substrate transfer chamber 13 is again
Transports the substrate to the metal film formation chamber 12 without exposing the semiconductor device to an oxidizing atmosphere or the atmosphere through
A metal film for source / drain electrodes is formed in the metal film forming chamber 12.

During the transfer of the substrate between the substrate heating chamber 10, the phosphine plasma processing chamber 11, the metal film forming chamber 12, and the substrate transfer chamber 13,
First gate valve 16a, second gate valve 16
b, The third gate valve 16c maintains the vacuum state without breaking.

The substrate heating chamber 10 in each of the manufacturing apparatuses shown in FIGS. 3A and 3B has a normal structure for heating the substrate, and includes, for example, a heater, a vacuum pump, and the like. Have been.

The substrate transfer chamber 13 has a normal structure for transferring a substrate between the chambers.
For example, it includes a substrate transfer arm, a vacuum pump, and the like.

The phosphine plasma processing chamber 11
Has a structure for performing the phosphine plasma treatment shown in FIG. 1C, such as a vacuum pump, a phosphine gas inlet, a heater for heating a substrate, an electrode plate to which an RF voltage can be applied, and the like. Is formed from. The phosphine plasma processing chamber 11 uses a conventional plasma C
It can be configured as having substantially the same device configuration as the VD chamber.

The metal film forming chamber 12 has a structure for forming a metal film for the source / drain electrodes shown in FIG. 1D, and includes, for example, a vacuum pump, a sputtering gas (such as argon). ) Inlet, substrate heater, D
It is formed from a metal target or the like to which a C voltage can be applied. The metal film forming chamber 12 can be configured to have almost the same apparatus configuration as a conventional DC sputtering apparatus. Further, the present invention is not limited to the sputtering apparatus, and may be configured to have a device configuration substantially the same as a general vapor deposition device.

In the method of manufacturing a semiconductor device according to the second embodiment, the gate insulating film, the amorphous silicon film,
The four steps of phosphine plasma treatment and metal sputter film formation can be performed without exposing the semiconductor device to an oxidizing atmosphere. Hereinafter, as a fourth embodiment of the present invention, a semiconductor manufacturing apparatus for performing the method of manufacturing a semiconductor device according to the second embodiment will be described.

FIG. 4A shows a first example of a semiconductor device manufacturing apparatus according to the fourth embodiment.

The semiconductor device manufacturing apparatus in the first example has a substrate heating chamber 10 as a first chamber for heating a substrate and a second chamber for forming a gate insulating film on the substrate. Gate insulating film forming chamber 14, an amorphous silicon film forming chamber 15 as a third chamber for forming an amorphous silicon film on a substrate, and phosphine plasma treatment for exposing the substrate to phosphine plasma. A phosphine plasma processing chamber 11 as a fourth chamber for carrying out the process, a metal film forming chamber 12 as a fifth chamber for forming a metal film for source / drain electrodes on a substrate, and a substrate heating chamber 10 A first gate valve 17a for connecting the chamber and the gate insulating film forming chamber 14 while maintaining a vacuum, and a gate insulating film forming chamber. A second gate valve 17b connects the bar 14 and the amorphous silicon film formation chamber 15 while maintaining a vacuum, and connects the second gate valve 17b between the amorphous silicon film formation chamber 15 and the phosphine plasma processing chamber 11. Third gate valve 17 connected while maintaining vacuum
and a fourth gate valve 17d for connecting the phosphine plasma processing chamber 11 and the metal film forming chamber 12 while maintaining a vacuum.

The present manufacturing apparatus is used as follows.

In this manufacturing apparatus, first, the substrate is heated in the substrate heating chamber 10, and thereafter, the substrate is transferred into the gate insulating film forming chamber 14, and the gate is placed on the substrate in the gate insulating film forming chamber 14. An insulating film is formed. Next, the substrate is placed in an amorphous silicon film formation chamber 1.
5, and an amorphous silicon film is formed on the gate insulating film in the amorphous silicon film forming chamber 15. After that, the substrate is transferred into the phosphine plasma processing chamber 11 and
A phosphine plasma treatment is performed within 1. Further, the substrate is transferred into the metal film forming chamber 12, and a metal film for source / drain electrodes is formed in the metal film forming chamber 12.

During the transfer of the substrate between the substrate heating chamber 10, the gate insulating film deposition chamber 14, the amorphous silicon film deposition chamber 15, the phosphine plasma processing chamber 11, and the metal deposition chamber 12, the first The vacuum state is maintained without being broken by the fourth to fourth gate valves 17a to 17d.

Note that the semiconductor device manufacturing apparatus in the first example need not necessarily have the substrate heating chamber 10. The substrate is heated by means different from the substrate heating chamber 10 and then the substrate is heated in the gate insulating film forming chamber 1.
4 may be conveyed.

The apparatus for manufacturing a semiconductor device according to the first example shown in FIG. 4A is an example of an in-line type apparatus. On the other hand, as an example of a single-wafer apparatus, FIG. 4B shows an apparatus for manufacturing a semiconductor device according to a second example of the fourth embodiment.

The semiconductor device manufacturing apparatus of the second example has a substrate heating chamber 10 as a first chamber for heating a substrate and a second chamber for forming a gate insulating film on the substrate. Gate insulating film deposition chamber 14
And an amorphous silicon film formation chamber 1 as a third chamber for forming an amorphous silicon film on a substrate
5, a phosphine plasma processing chamber 11 as a fourth chamber for performing phosphine plasma processing for exposing the substrate to phosphine plasma, and a fifth chamber for forming a metal film for source / drain electrodes on the substrate A metal film forming chamber 12, a substrate transfer chamber 13 as a sixth chamber as a space for transferring a substrate between the chambers 10, 14, 15, 11, 12, a substrate heating chamber 10, A first gate valve 18a for connecting the transfer chamber 13 while maintaining a vacuum, and a second gate valve for connecting the gate insulating film deposition chamber 14 and the substrate transfer chamber 13 while maintaining a vacuum. A vacuum is maintained between the gate valve 18b, the amorphous silicon film deposition chamber 15, and the substrate transfer chamber 13. Third gate valve 18c to be connected
And a fourth gate valve 18d for connecting the phosphine plasma processing chamber 11 and the substrate transfer chamber 13 while maintaining a vacuum, and maintaining a vacuum between the metal film forming chamber 12 and the substrate transfer chamber 13. And a fifth gate valve 18e that is connected to the fifth gate valve 18e.

The present manufacturing apparatus is used as follows.

First, the substrate is heated in the substrate heating chamber 10, the substrate is transferred to the gate insulating film forming chamber 14 via the substrate transfer chamber 13, and a gate insulating film is formed on the substrate.

Thereafter, the substrate transfer chamber 13 is again
The substrate is transported into the amorphous silicon film formation chamber 15 without exposing the semiconductor device to an oxidizing atmosphere via, and an amorphous silicon film is formed on the substrate.

Next, the substrate transfer chamber 13 is again
The substrate is transferred to the phosphine plasma processing chamber 11 without subjecting the semiconductor device to an oxidizing atmosphere through the, and subjected to phosphine plasma processing.

Finally, again, the substrate transfer chamber 13
The substrate is transferred to the metal film forming chamber 12 without exposing the semiconductor device to the oxidizing atmosphere through the
A metal film for a drain electrode is formed.

The substrate is transported between the substrate heating chamber 10, the gate insulating film deposition chamber 14, the amorphous silicon film deposition chamber 15, the phosphine plasma processing chamber 11, the metal deposition chamber 12, and the substrate transport chamber 13. In between, the first to fifth gate valves 18a
Through 18e, the vacuum state is maintained without breaking.

The substrate heating chamber 10 in each of the manufacturing apparatuses shown in FIGS. 4A and 4B has an ordinary structure for heating a substrate, and includes, for example, a heater, a vacuum pump, and the like. Have been.

The substrate transfer chamber 13 has a normal structure for transferring a substrate between the chambers.
For example, it includes a substrate transfer arm, a vacuum pump, and the like.

The phosphine plasma processing chamber 11
Has a structure for performing the phosphine plasma treatment shown in FIG. 1C, such as a vacuum pump, a phosphine gas inlet, a heater for heating a substrate, an electrode plate to which an RF voltage can be applied, and the like. Is formed from. The phosphine plasma processing chamber 11 uses a conventional plasma C
It can be configured as having substantially the same device configuration as the VD chamber.

The metal film forming chamber 12 has a structure for forming a metal film for the source / drain electrodes shown in FIG. 1D, and includes, for example, a vacuum pump, a sputtering gas (such as argon). ) Inlet, substrate heater, D
It is formed from a metal target or the like to which a C voltage can be applied. The metal film forming chamber 12 can be configured to have almost the same apparatus configuration as a conventional DC sputtering apparatus. Further, the present invention is not limited to the sputtering apparatus, and may be configured to have substantially the same apparatus configuration as a general vapor deposition apparatus.

Further, the gate insulating film formation chamber 14 and the amorphous silicon film formation chamber 15 can be configured to have the same structure as a conventional plasma CVD chamber, for example.

[0105]

The present invention will be described below in detail with reference to examples, but the present invention is not limited to these examples.

A method for manufacturing an inverted staggered thin film transistor will be described as an embodiment of the present invention in the order of steps shown in FIG.

First, a glass substrate 1 which is a transparent insulating substrate
A chromium film as a gate electrode metal was formed thereon to a thickness of 100 nm by a sputtering method, and was patterned into a desired shape by a wet etching method to form a gate electrode 2.

Thereafter, as shown in FIG. 1A, a silicon nitride film 3 as a gate insulating film is formed to a thickness of 400 nm by a plasma CVD method at a substrate temperature of 300 ° C. using a mixed gas of silane, ammonia and nitrogen as a raw material. An amorphous silicon film 4 as an active layer was formed to a thickness of 100 nm using a mixed gas of silane and hydrogen as a raw material.

Thereafter, as shown in FIG. 1B, the amorphous silicon film 4 was etched by a dry etching method and patterned into a desired island shape.

Subsequently, the amorphous silicon film 4 is subjected to phosphine plasma processing at a substrate temperature of 250 ° C. using the phosphine plasma processing chamber 11 in the manufacturing apparatus shown in FIG. 3A or 3B. , FIG. 1 (c)
As shown in FIG. 6, phosphorus 6 was deposited on the surface of the amorphous silicon film 4. At this time, phosphorus may diffuse into the surface layer of the amorphous silicon film 4 in some cases. As a source gas for the phosphine plasma treatment, a 0.5% phosphine gas based on hydrogen was used.

Further, the glass substrate 1 is transported into the metal film formation chamber 12 without breaking the vacuum, that is, without exposing the semiconductor device to an oxidizing atmosphere, and
At 50 ° C., chromium as a metal for source / drain electrodes was formed to a thickness of 100 nm by a sputtering method.

Thereafter, as shown in FIG. 1D, the chromium film was patterned into a desired shape to form source / drain electrodes 7.

Finally, unnecessary n between the source and drain electrodes
By etching and removing the shaped amorphous silicon film 8, a thin film transistor as shown in FIG. 1E was completed.

The thickness of the n-type amorphous silicon film 8 formed in this embodiment is about several nm, which is very thin. For this reason, the unnecessary n-type amorphous silicon film 8 between the source and drain electrodes is removed by etching instead of etching away the unnecessary n-type amorphous silicon film 8 between the source and drain electrodes. A thin film transistor can also be formed by a method of modifying an insulating film by a treatment.

Alternatively, in the step shown in FIG. 1D, the source and drain electrodes are patterned by a dry etching method or a wet etching method, so that this extremely thin, unnecessary n-type amorphous silicon film 8 is formed. Can also be removed at the same time. This eliminates the need for a process such as the etching removal of the n-type amorphous silicon film 8 or the plasma treatment, which is the final process described above, and the number of processes can be reduced.

In the thin film transistor of the present invention produced according to this example, good switching characteristics with an on / off ratio of 6 digits or more and a field effect mobility of about 0.7 cm ² V ⁻¹ s ⁻¹ were obtained.

This is because an n-type amorphous silicon film 8 is formed by using the manufacturing method and the manufacturing apparatus according to the present invention.
Good ohmic contact is obtained in the source / drain region without forming
This shows that a thin film transistor having sufficient characteristics as a switching element of a liquid crystal display can be manufactured.

A method of manufacturing an inverted staggered type thin film transistor according to the second embodiment of the present invention will be described below with reference to the steps shown in FIG.

First, a glass substrate 1 as a transparent insulating substrate was used.
After forming a film of chromium as a metal for a gate electrode to a thickness of 100 nm by sputtering, chromium was patterned into a desired shape by wet etching to form a gate electrode 2.

Then, at a substrate temperature of 300 ° C., a silicon nitride film 3 as a gate insulating film was formed to a thickness of 400 nm by using a mixed gas of silane, ammonia and nitrogen as a raw material at a substrate temperature of 300 ° C. Formed.

The above-described formation of the silicon nitride film 3 is described in FIG.
(A) or in the gate insulating film forming chamber 14 in the manufacturing apparatus shown in FIG.

Next, the glass substrate 1 is transported into the amorphous silicon film forming chamber 15, and the amorphous silicon film 4 as an active layer is formed using a mixed gas of silane and hydrogen as a raw material.
00 nm was formed.

Further, the glass substrate 1 is transferred into the phosphine plasma processing chamber 11 without subjecting the semiconductor device to the oxidizing atmosphere, and the amorphous silicon film 4 is subjected to the phosphine plasma processing. As shown in b), phosphorus 6 was deposited on the surface of the amorphous silicon film 4. At this time, phosphorus may diffuse into the surface layer of the amorphous silicon film 4 in some cases. The substrate temperature at the time of the phosphine plasma treatment is 250 ° C.
Phosphine gas was used.

Thereafter, the glass substrate 1 is exposed to the atmosphere, and then the glass substrate 1 is transferred into the metal film forming chamber 12, and at a substrate temperature of 250 ° C., as shown in FIG. Chromium as a metal for use was deposited to a thickness of 100 nm by a sputtering method using an argon gas. At this time, a thin n-type amorphous silicon film 8 of about several nm was automatically formed between the amorphous silicon film 4 and the chromium film.

Thereafter, the chromium film formed by sputtering is patterned into a desired shape, and the source / drain electrodes 7 are formed.
Was formed. Further, as shown in FIG. 2D, the n-type amorphous silicon film 8 and the amorphous silicon film 4 were patterned into a desired island shape.

Finally, unnecessary n between the source and drain electrodes
By etching and removing the shaped amorphous silicon film 8, a thin film transistor as shown in FIG. 2E was completed.

As in the case of the first embodiment, the thickness of the n-type amorphous silicon film 8 formed in this embodiment is about several nm, which is very thin. For this reason, the source
Unnecessary n-type amorphous silicon film 8 between drain electrodes
A thin film transistor can also be formed by a method in which is converted into an insulating film by plasma treatment.

Alternatively, also in this embodiment, FIG.
By patterning the source / drain electrodes by a dry etching method or a wet etching method in the step shown in (d), this extremely thin and unnecessary n-type amorphous silicon film 8 can be removed at the same time. Was.
This eliminates the need for the above-described final processes such as the etching removal of the n-type amorphous silicon film 8 and the plasma treatment.

In the thin film transistor of the present embodiment fabricated as described above, the on / off ratio is 6 digits or more and the field effect mobility is 0.8 cm, as in the first embodiment.
Good switching characteristics of about ² V ^-1 s ^-1 were obtained.

In this embodiment, the substrate 1 is exposed to the air after the phosphine plasma treatment on the amorphous silicon film 4, and then the metal film is formed. After the phosphine plasma treatment, the vacuum is not broken. Similar transistor characteristics were obtained even when metal films were continuously formed.

By using the manufacturing method and the manufacturing apparatus according to the present invention, a good ohmic contact can be obtained in the source / drain regions without forming an n-type amorphous silicon film individually. As a result, it is shown that a thin film transistor having sufficient characteristics as a switching element of a liquid crystal display can be manufactured.

In addition to the above-described embodiments, the semiconductor manufacturing method and the semiconductor manufacturing apparatus according to the present invention can be applied to various inverted staggered thin film transistor structures having different structures, and also to a polycrystalline silicon film other than an amorphous silicon film. Obviously, the present invention can be applied to the thin film transistor used.

The present invention is not limited to a thin film transistor, but is applicable to any semiconductor device having an amorphous silicon / n-type amorphous silicon / metal junction.

In the phosphine plasma treatment, it is also possible to use a phosphine gas based on various gases other than hydrogen gas (eg, argon gas, helium gas, etc.).

As for metal film formation after phosphine plasma treatment, only sputter film formation has been described.
Various film formation methods such as an evaporation method other than sputtering can be applied.

In the above embodiment, the gate electrode, the source
Although an example in which chromium is used as the drain electrode has been described, other known metals such as molybdenum, aluminum, and tantalum and their alloys, or a laminated structure of these metals, the present invention is applicable to any form. A semiconductor manufacturing method and a semiconductor manufacturing apparatus can be applied.

[0137]

As described above, according to the present invention,
In the inverted staggered thin film transistor, the phosphine plasma treatment is performed after forming the amorphous silicon film without individually forming the n-type amorphous silicon film, so that the n-type amorphous silicon film is formed in the source / drain regions. A crystalline silicon film can be automatically formed.

In addition, by using the present invention, the number of film formation steps can be reduced, so that the yield of thin film transistors can be improved.

Furthermore, by connecting a plasma CVD apparatus and a metal film forming apparatus such as sputtering as in the present invention,
These processes are continuously performed to form a thin film transistor, so that the throughput of the manufacturing process can be improved.

Further, since the thickness of the n-type amorphous silicon film formed by the present invention is very small, unnecessary n-type amorphous silicon film between the source and drain electrodes is subjected to plasma treatment to form an insulating film. The thin film transistor can also be manufactured by a method of modifying the thickness of the thin film transistor.

By patterning the source / drain electrodes by dry etching or wet etching, unnecessary n-type amorphous silicon films between the source / drain electrodes can be removed at the same time. This eliminates the need for processes such as etching and plasma treatment of the n-type amorphous silicon film, which are the final steps, and can reduce the number of steps.

As described above, by using the present invention, the yield of the reverse staggered thin film transistor can be reduced.
The process throughput is greatly improved, and the cost of the liquid crystal display manufacturing process can be reduced.

[Brief description of the drawings]

FIGS. 1A to 1E are cross-sectional views of a semiconductor device showing respective steps in a first embodiment of a method for manufacturing a thin film transistor according to the present invention.

FIGS. 2A to 2E are cross-sectional views of a semiconductor device showing respective steps in a second embodiment of the method for manufacturing a thin film transistor according to the present invention.

FIGS. 3A and 3B are schematic views showing one embodiment of a semiconductor manufacturing apparatus according to the present invention.

FIGS. 4A and 4B are schematic views showing another embodiment of the semiconductor manufacturing apparatus according to the present invention.

5 (a) to 5 (e) are cross-sectional views of a semiconductor device showing respective steps in a conventional method for manufacturing an inverted staggered thin film transistor.

[Explanation of symbols]

Reference Signs List 1 transparent insulating substrate 2 gate electrode 3 gate insulating film 4 amorphous silicon film 5 phosphine plasma 6 phosphorus 7 source / drain electrode 8 n-type amorphous silicon film 9a, 9b gate valve 10 substrate heating chamber 11 phosphine plasma Processing chamber 12 Metal film forming chamber 13 Substrate transport chamber 14 Gate insulating film forming chamber 15 Amorphous silicon film forming chamber 16a, 16b, 16c Gate valve 17a, 17b, 17c, 17d Gate valve 18a, 18b, 18c, 18d, 18e Gate valve

Claims (16)

[Claims] A first step of forming an amorphous silicon film on a substrate; and a step of forming at least V on the substrate on which the amorphous silicon film is formed.
A method of manufacturing a semiconductor device, comprising: a second step of performing a plasma treatment including a group III element; and a third step of forming a metal film on the amorphous silicon film subjected to the plasma treatment. 2. The semiconductor device according to claim 1, wherein, following the first step, the second step is performed without exposing the semiconductor device to an oxidizing atmosphere. Manufacturing method. 3. The method according to claim 1, wherein, after the second step, the third step is performed without exposing the semiconductor device to an oxidizing atmosphere. A method for manufacturing a semiconductor device. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the plasma treatment including the group V element is a plasma treatment using at least a phosphine gas. 5. A first step of sequentially forming an insulating film and an amorphous silicon film over a gate electrode formed on a substrate, and sequentially forming the insulating film and the amorphous silicon film under reduced pressure. A second step of performing a phosphine plasma treatment on the formed substrate; and forming a metal film on the amorphous silicon film subjected to the phosphine plasma treatment, and patterning the metal film into a shape of a source electrode and a drain electrode. A method of manufacturing a semiconductor device, comprising: a third step; and a fourth step of patterning the amorphous silicon film. 6. A first step of sequentially forming an insulating film and an amorphous silicon film over a gate electrode formed on a substrate; and a second step of patterning the amorphous silicon film. Under a reduced pressure, a third step of performing a phosphine plasma treatment on the substrate on which the amorphous silicon film has been patterned, and forming a metal film on the substrate on which the phosphine plasma treatment has been performed, using the metal film as a source electrode and A fourth step of patterning into a shape of a drain electrode. 7. The method according to claim 5, further comprising a fifth step of removing an unnecessary portion of the amorphous silicon film subjected to the phosphine plasma treatment between the source electrode and the drain electrode. A method for manufacturing a semiconductor device. 8. The method according to claim 7, further comprising a step of simultaneously executing the fifth step by patterning the metal film into a shape of a source electrode and a drain electrode by a dry etching method or a wet etching method. 13. The method for manufacturing a semiconductor device according to item 5. 9. An unnecessary portion of the amorphous silicon film subjected to the phosphine plasma treatment between the source electrode and the drain electrode is converted into an insulating film by performing a plasma treatment using at least an oxygen gas or a nitrogen gas. 9. The method for manufacturing a semiconductor device according to claim 7, further comprising the step of: 10. A semiconductor device comprising: a process of exposing an amorphous silicon film formed on a substrate to phosphine plasma; and a process of forming a metal film on the amorphous silicon film subjected to the plasma processing. Is a semiconductor manufacturing apparatus that can be continuously performed without being exposed to an oxidizing atmosphere. 11. A process for forming an amorphous silicon film on a substrate, a process for exposing the amorphous silicon film to phosphine plasma, and a process for forming a metal film on the amorphous silicon film subjected to the plasma process. A semiconductor manufacturing apparatus capable of continuously performing a film forming process without exposing the semiconductor device to an oxidizing atmosphere. 12. A first chamber for exposing the substrate to phosphine plasma, a second chamber for forming a metal film on the substrate, the first chamber and the second chamber. And a gate valve connected while maintaining a vacuum between the semiconductor manufacturing apparatus. 13. A first chamber for heating a substrate, a second chamber for exposing the substrate to phosphine plasma, a third chamber for forming a metal film on the substrate, A first gate valve that connects the first chamber and the second chamber while maintaining a vacuum; and a connection that maintains a vacuum between the second chamber and the third chamber. And a second gate valve to be manufactured. 14. A first chamber for heating a substrate, a second chamber for exposing the substrate to phosphine plasma, a third chamber for forming a metal film on the substrate, A fourth chamber as a space for transporting the substrate, a first gate valve for connecting the first chamber and the fourth chamber while maintaining a vacuum, and the second chamber And a second gate valve for connecting the fourth chamber while maintaining a vacuum, and a third gate for connecting the third chamber and the fourth chamber while maintaining a vacuum A semiconductor manufacturing apparatus comprising: a valve; 15. A first chamber for heating a substrate, a second chamber for forming a gate insulating film on the substrate, and forming an amorphous silicon film on the substrate. A third chamber, a fourth chamber for exposing the substrate to phosphine plasma, a fifth chamber for forming a metal film on the substrate, the first chamber and the second A first gate valve that connects between the chambers while maintaining a vacuum; a second gate valve that connects between the second chamber and the third chamber while maintaining a vacuum; A third gate valve that connects the third chamber and the fourth chamber while maintaining a vacuum; and a connection that maintains the vacuum between the fourth chamber and the fifth chamber. Fourth A gate valve, a semiconductor manufacturing apparatus comprising a. 16. A first chamber for heating a substrate, a second chamber for forming a gate insulating film on the substrate, and forming an amorphous silicon film on the substrate. A third chamber for exposing the substrate to phosphine plasma; a fifth chamber for forming a metal film on the substrate; and a space for transporting the substrate. A sixth chamber, a first gate valve for connecting the first chamber and the sixth chamber while maintaining a vacuum, and between the second chamber and the sixth chamber. A second gate valve that connects while maintaining a vacuum, a third gate valve that connects between the third chamber and the sixth chamber while maintaining a vacuum, and the fourth chamber A fourth gate valve that connects the sixth chamber while maintaining a vacuum; and a fifth gate valve that connects the fifth chamber and the sixth chamber while maintaining a vacuum. And a semiconductor manufacturing apparatus comprising: