JP2003172949A - Manufacturing method for array substrate for display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for an array substrate for a display device wherein a contact defect is prevented and yield is enhanced. <P>SOLUTION: In the manufacturing method for the array substrate, a substrate 10 on which a plurality of films and contact holes 31, 35 and 52 are formed is washed and then dried by preliminarily heating the substrate at a prescribed temperature and removing residual moisture. After the drying stage, a transparent conductive film in an amorphous state is formed on the substrate to form a pixel electrode 28 without exposing the preliminarily heated substrate to the atmosphere. After that, the pixel electrode is subjected to annealing treatment and crystallized by heating the substrate. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an array substrate for a display device used for a flat display device such as a liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, flat-panel display devices that replace CRT displays have been actively developed, and liquid crystal display devices have attracted particular attention due to their advantages such as light weight, thin shape, and low power consumption. For example, an active matrix type liquid crystal display device in which a switch element is arranged for each display pixel has a structure in which a liquid crystal layer is held between an array substrate and a counter substrate via an alignment film.

The array substrate has a plurality of signal lines and scanning lines arranged in a grid on a transparent insulating substrate such as glass or quartz, and amorphous silicon (hereinafter referred to as "amorphous silicon") is formed at each intersection of the signal lines and scanning lines. , A-Si) and other thin film transistors (hereinafter abbreviated as TFT) using a semiconductor thin film.
Are connected. The gate electrode of the TFT is electrically connected to the scanning line, the drain electrode is electrically connected to the signal line, and the source electrode is connected to the pixel electrode made of a transparent conductive material such as ITO (Indium Tin Oxide). .

In the counter substrate, a counter electrode made of ITO is arranged on a transparent insulating substrate such as glass, and if a color display is realized, color filter layers are stacked.

Conventionally, an array substrate for a liquid crystal display device is manufactured by the following steps. First, a gate electrode and a scanning line integrated with the gate electrode are patterned on a glass substrate. Next, after depositing a silicon oxide film as a first gate insulating film and a silicon nitride film as a second gate insulating film on the upper surface of the glass substrate, a-Si is deposited on the upper surface thereof.
A semiconductor film made of is deposited. Next, after depositing a silicon nitride film as a channel protective film on the upper surface of the semiconductor film, patterning is performed.

Subsequently, after depositing a low-resistance semiconductor film made of n ⁺ a-Si and a metal film, the source electrode, the signal line, and the drain electrode integrated with the signal line are patterned. Thereafter, the same resist pattern is used to pattern the low-resistance semiconductor film of n ⁺ a-Si and the semiconductor film of a-Si by PE (plasma etching).

Next, after depositing an interlayer insulating film made of a silicon nitride film on the entire surface, BHF (buffered hydrofluoric acid) is deposited.
Thus, the interlayer insulating film and the first and second insulating films are wet-etched to form a contact hole that connects the source electrode and the pixel electrode and a contact hole that exposes a connection end of the signal line or the scanning line.

Then, the substrate surface is MS (Megasonic)
After washing, the substrate is dried by removing water by spin drying or the like. Amorphous IT, which will later become the pixel electrode
O (hereinafter abbreviated as a-ITO) is deposited on the substrate by a sputtering method. At this time, the substrate is set at room temperature in the film forming chamber, for example, and the film is formed with water added. Then, after patterning the a-ITO, it is annealed at 230 ° C. or higher to crystallize the a-ITO and to form a low-resistance ITO.
And the array substrate is completed.

[0009]

However, in the above-described conventional manufacturing process, a connection failure may occur at a portion connected to the ITO via the contact hole. When this defective connection point was confirmed, it was found that the ITO swelled in the contact hole portion, and sufficient electrical connection with the lower layer was not obtained. Then, as a result of sincere examination by the present inventors regarding this cause, it has become clear that it is due to the following reason. That is, in the spin drying in the cleaning step before the film formation of a-ITO, the water in the recesses such as the contact holes of the array substrate cannot be completely removed, that is, the residual water easily remains. In particular, water tends to remain on the array substrate at the center of rotation during spin drying. Therefore, if an annealing step (230 ° C. or higher) is performed for the purpose of crystallizing a-ITO after forming a-ITO with water remaining, the ITO partially swells due to evaporation of residual water, It is considered that contact failure occurs between the source electrode and the pixel electrode.
The present invention has been made in view of the above points, and an object thereof is to provide a method of manufacturing an array substrate for a display device capable of preventing the occurrence of contact defects and improving the manufacturing yield.

[0010]

In order to achieve the above object, a method of manufacturing an array substrate according to the present invention is such that a scanning line arranged on a substrate and a scanning line arranged on the substrate are stacked and laminated on the substrate. A first insulating film, a semiconductor film disposed on the first insulating film, a source electrode and a drain electrode electrically connected to the semiconductor film, the source electrode and the drain electrode, and the semiconductor film. A thin-film transistor including a low-resistance semiconductor film interposed therebetween, a signal line extending from the drain electrode and extending substantially orthogonal to the scanning line, and a first electrode disposed on the source electrode and the drain electrode. 2. A method of manufacturing an array substrate for a display device, comprising: a pixel electrode electrically connected to the source electrode via a contact hole of an insulating film; A step of washing the plate, a drying step of preheating the washed substrate at a predetermined temperature to remove residual moisture, and an amorphous state without exposing the preheated substrate to the atmosphere after the drying step. The method is characterized by including a step of forming a transparent conductive film in a quality state on the substrate, and an annealing step of heating the substrate to crystallize the transparent conductive film in the amorphous state.

Further, according to the method of manufacturing an array substrate of the present invention, the substrate is dried by 100 in the drying step.
It is characterized in that it is preheated to a temperature of ℃ or more and dried. Further, according to the array substrate manufacturing method of the present invention, in the drying step, the substrate is preheated to a temperature substantially the same as the substrate temperature when the transparent conductive film is formed, and dried. I am trying. The drying step is
It can be performed in a preheating chamber of a film forming apparatus for forming the above-mentioned amorphous transparent conductive film.

According to the method of manufacturing an array substrate for a display device of the present invention configured as described above, the water remaining on the substrate in the cleaning process before forming the pixel electrodes is completely removed by the preliminary heating in the drying process. After the removal, by forming the pixel electrode without exposing the substrate to the atmosphere, it is possible to prevent the occurrence of contact failure due to residual moisture and improve the manufacturing yield.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. First, an array substrate of a liquid crystal display device manufactured by the manufacturing method according to the embodiment of the present invention will be described.

As shown in FIG. 1, the array substrate includes a plurality of scanning lines 14 provided on a transparent insulating substrate 10 such as glass or quartz, and a plurality of signal lines 15 substantially orthogonal to the scanning lines. Is equipped with. Each signal line 15 is an insulating substrate 1
The signal line connection pad 16 is provided near one end of the signal line 0. Further, each scanning line 14 is drawn out near the other end side of the substrate 10, and a scanning line connection pad 18 is provided at the end thereof.

A TFT 20 using a semiconductor thin film is connected to each intersection of the scanning line 14 and the signal line 15.
In the TFT 20, the scanning line 14 itself is used as a gate electrode, and the first gate insulating film 32 and the second gate insulating film 3 are formed thereon.
4 and the drain electrode 24 and the source electrode 26 provided on the semiconductor film 36 via the low resistance semiconductor film 37. And
The drain electrode 24 of the TFT 20 is electrically connected to the signal line 15, and the source electrode 26 is connected to a light transmissive pixel electrode 28 made of, for example, ITO.

The connection end 15a of the signal line 15 constitutes the signal line connection pad 16 together with the pad member 31a arranged in the contact hole 31 formed in the interlayer insulating film 30 as the third insulating film, and also scans. Connection end 14 of wire 14
The a constitutes the scanning line connection pad 18 together with the pad member 35a arranged in the contact hole 35 formed in the interlayer insulating film 30 and the first gate insulating film 32.
These pad members 31a and 35a are made of the same material as the pixel electrode 28 in the same step.

The pixel electrode 28 is provided for the scanning line 14 via the first gate insulating film 32 and the interlayer insulating film 30, and for the signal line 15 via the interlayer insulating film 30. Are arranged. Note that, in order to achieve a high aperture ratio, it is desirable that the end portion of the pixel electrode 28 be planarly overlapped with a part of the scanning line 14 or the signal line 15. Next, a more detailed structure of the array substrate will be described along with a method of manufacturing the array substrate. First, as shown in FIG. 2A, a MoW alloy film is deposited to a thickness of 250 nm on the insulating substrate 10 by sputtering, and then a resist is applied,
Further, the resist is exposed and developed using the first mask pattern to form a first resist pattern. Then, through the patterning (first patterning) using the first resist pattern as a mask, the plurality of scanning lines 14 and the auxiliary capacitance lines 38 are formed on the insulating substrate 10. Each scan line 14
Is a connection end portion 1 drawn out to one end side of the insulating substrate 10.
4a.

Subsequently, as shown in FIG. 2B, a first gate insulating film 32 made of a silicon oxide film is formed by a plasma CVD (chemical vapor deposition) method to form a first gate insulating film 175.
nm, and then a second gate insulating film 34 made of a silicon nitride film having a thickness of 150 nm and a-S having a thickness of 50 nm.
A semiconductor film 36 made of i: H and a channel protective film made of a silicon nitride film having a thickness of 300 nm are formed by plasma C
By the VD method, the film is continuously formed without being exposed to the atmosphere.

Then, a resist is applied on this, and the scanning line 14 is formed by a backside exposure technique using the scanning line 14 as a mask.
A second resist pattern self-aligned with is formed, and the channel protective film is patterned (second patterning) using the second resist pattern as a mask to form an island-shaped channel protective film 40.

After that, as shown in FIG. 2C, the semiconductor film 36 is formed so that a good ohmic contact can be obtained.
The exposed surface is treated with hydrofluoric acid, and a low resistance semiconductor film 37 made of n ⁺ a-Si: H containing phosphorus as an impurity and having a thickness of 50 nm is deposited thereon by plasma CVD.

Next, a Mo layer having a thickness of about 250 nm and about 250 are formed.
A laminated film including an Al layer having a thickness of 0 nm and a Mo layer having a thickness of about 50 nm is deposited by the sputtering method. Then, a resist is applied, exposure and development are performed using a third master pattern to form a third resist pattern, and using this third resist pattern as a mask, a mixed acid of phosphoric acid, nitric acid, acetic acid, and water is used. The Mo / Al / Mo laminated film is wet-etched. Thereby, the source electrode 26, the drain electrode 24, and the signal line integrated with the drain electrode are formed.

Then, using the third resist pattern or the source electrode 26, the drain electrode 24, and the signal line as a mask, the low resistance semiconductor film 37, the semiconductor film 36,
And the second gate insulating film 34 by RIE (reactive
Patterning (third patterning) is performed collectively by an ion etching method. At this time, the etching selection ratio with respect to the channel protective film 40 is appropriately controlled.

As a result, the semiconductor film 36, the low resistance semiconductor film 37, the source electrode 26, the signal line 15, the connection end integrated with the signal line, and the drain electrode 24 integrated with the signal line.
Is formed. At the same time, the second gate insulating film 34 made of a silicon nitride film other than the third resist pattern is removed.

Then, the semiconductor film 36 and the low resistance semiconductor film 3 are formed.
Since the 7, the source electrode 26, the drain electrode 24, and the second gate insulating film 34 are etched based on the common third resist pattern, a slight step difference occurs due to the difference in the over-etching amount, but at the portion of the TFT 20. , The contours are formed so as to substantially coincide with each other.

Subsequently, as shown in FIG. 3A, an interlayer insulating film 30 made of a silicon nitride film having a thickness of 200 nm is deposited over the entire surface of the substrate, and then a resist is applied,
The resist is exposed and developed using the fourth master pattern,
A fourth resist pattern is formed. Then, the interlayer insulating film 30 is patterned (fourth patterning) based on the fourth resist pattern by wet etching with BHF (buffered hydrofluoric acid), and the contact hole 52 communicating with the source electrode 41 and the connection end of the signal line 42. A contact hole 31 (see FIG. 1) communicating with the. At the same time, the first gate insulating film 32 and the interlayer insulating film 30 in the portion facing the connection end 14 a of the scanning line 14 are continuously and collectively removed to form a contact hole 35.

Subsequently, after the substrate 10 on which the various films and the contact holes 31 and 35 are formed is washed and dried as described above, as shown in FIG.
-Deposit ITO.

Here, cleaning, drying and a-IT of the substrate 10 are performed.
The O film forming process will be described in detail. As shown in FIG. 4, the film forming apparatus 50 includes a cassette station 54 disposed in the vicinity of the transport path A, a processing unit 56 provided opposite to the cassette station, and a cassette station 5.
4 and a spin cleaning unit 58 provided laterally offset with respect to the processing unit 56, provided between the cassette station and the processing unit 56, and a glass substrate between the cassette station, the processing unit, and the spin cleaning unit 58. A transport robot 57 for loading and unloading the substrate and a transport robot 59 for transporting the substrate in the processing unit 56 are provided.

The cassette station 54 has two cassette mounting portions 54a arranged along the transport path A, and each cassette mounting portion 54a has a cassette C in which a plurality of substrates 10 are stored in a stacked state. It is mounted detachably. The cassette C is transported along the transport path A by a transport device (not shown) and placed on the cassette placement portion 54a.

The processing section 56 of the film forming apparatus 50 is arranged side by side in the Y direction with respect to the cassette station 54. The processing unit 56 is a multi-chamber type processing unit, and includes a load lock chamber 60 whose inside can be controlled to atmospheric pressure or vacuum. One end of the load lock chamber 60 faces the cassette station 54. At the other end of the load lock chamber 60, a vacuum transfer chamber 61 having a substantially hexagonal plane is arranged with one side thereof being in contact with the load lock chamber. Further, on the other five sides of the vacuum transfer chamber 61, a preheating chamber 62 for preheating the substrate 10 and four film forming chambers 64 for forming a thin film on the substrate 10 by sputtering are provided. These preheating chamber 62 and film forming chamber 64
Respectively function as individual processing units.

The spin cleaning unit 58 of the film forming apparatus 50 spin-cleans the substrate 10 taken out from the cassette C, is provided adjacent to the cassette station 54 and the processing section 56, and is provided at the cassette station. The first space connecting the cassette station and the load lock chamber 60 of the processing unit to the space between the processing unit 56 and the processing unit 56.
Direction, that is, the second direction orthogonal to the Y direction, that is, X
It is provided offset in the direction.

The transfer robot 57 of the film forming apparatus 50 includes the cassette station 54 and the load lock chamber 6 of the processing section 56.
0, the substrate 10 is taken out from the cassette station 54 and loaded into the spin cleaning unit 58, and the substrate 10 after cleaning is loaded into the load lock chamber 60. Further, the transfer robot 57 takes out the substrate formed by the processing unit 56 from the load lock chamber 60 and returns it to the cassette C.

The transfer robot 59 has a vacuum transfer chamber 6
1, the substrate 10 is taken out from the load lock chamber 60 and selectively carried into the preheating chamber 62 and the film forming chamber 64. Then, the transfer robot 59 returns the substrate formed by the processing unit 56 to the load lock chamber 60.

In the film forming apparatus 50 configured as described above, the substrates 10 are taken out one by one from the cassette C by the transfer robot 57 and sent to the spin cleaning unit 58 where they are spin cleaned. After the cleaning is completed, the substrate 10
Is carried into the load lock chamber 60 by the transfer robot 57. The processing unit 56 includes the load lock chamber 60.
The inside is evacuated to a predetermined degree of vacuum.

Subsequently, the substrate 10 is transferred from the load lock chamber 60 to the preheating chamber 62 by the transfer robot 59. Then, in the preheating chamber 62, the pressure of the substrate 10 is reduced to 10
Preheating is performed to a temperature of 100 ° C. or higher in an Ar gas atmosphere of 0 Pa or higher. As a result, the water remaining on the substrate 10 in the cleaning process is completely removed, and the substrate 10 is dried.

The preheating temperature of the substrate 10 is set to 100 ° C. to 120 ° C., and preferably set to a temperature substantially the same as the substrate temperature at the time of forming an a-ITO film described later. Here, one substrate was preheated and dried by setting the preheating chamber 62 in an Ar gas atmosphere having a predetermined pressure, preheating temperature of 115 ° C., and heating time of 1 minute.

After the drying by the preheating is completed, the substrate 1
0 is taken out from the preheating chamber 62 by the transfer robot 59, and is transferred into the film forming chamber 64 through the vacuum transfer chamber 61. During this time, the substrate 10 is sent from the preheating chamber 62 to the film forming chamber 64 and subjected to the film forming process without being exposed to the atmosphere.

As shown in FIG. 3B, in the film forming chamber 64, at least one gas of Ar or Kr is mainly used by the DC sputtering method, and further H ₂ 0 is introduced to the substrate 10. An a-ITO film having a thickness of 40 nm is formed. The substrate temperature during film formation is set to 100 ° C to 120 ° C,
Desirably, it is set to be substantially the same as the preheating temperature. The film formation time was 30 seconds, and the pressure in the film formation chamber 64 was 0.65 Pa.

The gas pressure adjusting time, that is, the time until the substrate 10 is carried into the film forming chamber 64, the gas is introduced, and the glow discharge is started is set to 300 seconds or more, which is similar to the above. The effect is obtained.

The substrate 10 on which the a-ITO film is formed as described above is taken out from the film forming chamber 64 by the transfer robot 59 and transferred to the load lock chamber 60. Further, the substrate 10 is transferred to the load lock chamber 60 by the transfer robot 57.
And is returned to one of the cassettes C. Then, the cassette C on which the substrate 10 having the a-ITO film formed thereon is placed is carried to the next step.

After that, an a-IT formed on the substrate 10 is formed.
Apply resist on O. Then, the resist is exposed and developed using the fifth master pattern to form a fifth resist pattern, and based on the fifth resist pattern, the a-ITO film is etched with a caustic acid-based weak organic acid etchant. By doing so, patterning (fifth patterning) is performed.

As a result, the pixel electrode 28 electrically connected to the source electrode 26 through the contact hole 52 is formed, and at the same time, the scanning line 14 is formed through the contact hole 35.
A pad member 35a made of the same material as the pixel electrode 28 and connected to the connection end 14a of the pixel electrode 28, and a pad member 31a made of the same material as the pixel electrode 28 and connected to the connection end of the signal line 15 through the contact hole 31. .

Subsequently, the entire substrate 10 is heated at 230 ° C. for 30 minutes in an oven in a nitrogen atmosphere to perform an annealing treatment to stabilize the characteristics of the TFT 20, and at the same time, a-I
The pixel electrode 28 made of TO and the pad members 31a, 3
Crystallize 5a.

After the above-mentioned annealing process is completed, a protective film is formed on the substrate by a silicon nitride film or the like, if necessary, to complete the manufacture of the array substrate.

When a liquid crystal display device was assembled using the array substrate manufactured in this way and a screen display inspection was carried out, no display unevenness was confirmed and good display could be obtained.

According to the method of manufacturing an array substrate described above, by preheating the cleaned substrate, it is possible to completely remove the residual water remaining on the substrate, especially in the contact holes. . Furthermore, the substrate 10 dried by preheating is not exposed to the atmosphere, and the film formation chamber 64
It is possible to prevent moisture from adhering to the substrate by carrying it in and depositing a film here. Therefore, a-ITO
When the annealing treatment is performed after the film formation, the contact failure between the source electrode and the pixel electrode due to the residual moisture on the substrate 10 can be prevented, and the manufacturing yield of the array substrate can be improved.

Further, according to the above manufacturing method, preheating
The substrate temperature is 100 ° C or higher, or the substrate during film formation
After the film is heated to almost the same temperature, the film is formed.
Therefore, preheating keeps the entire substrate at a uniform temperature.
The film forming process can be performed in the open state. Therefore, film formation
It is possible to prevent cracking of the substrate 10 at the time. same
Sometimes it is necessary to stabilize the substrate temperature by preheating.
H during film formation _TwoBy stabilizing the O atmosphere
As a result, the quality of the formed a-ITO film is stabilized.
It is possible to

The present invention is not limited to the above-described embodiments, but can be variously modified within the scope of the present invention. For example, the preheating of the substrate is not limited to the case where the preheating chamber of the film forming apparatus is used. Specifically, the gas pressure adjusting time, that is, the substrate 10 is loaded into the film forming chamber 64,
By setting the time until the gas is introduced and the glow discharge is started to, for example, 300 seconds or more, the substrate can be preheated for a predetermined time, and the same effect as described above can be obtained.

Further, the shape of each film forming the array substrate,
The thickness, forming method, and the like can be variously modified as necessary.
Furthermore, the pixel electrode is not limited to ITO, and it is possible to use another transparent conductive film.

As a semiconductor film forming a part of the TFT,
The present invention, which has been described for the configuration including a-Si, can also be applied to a method for manufacturing an array substrate having a polycrystalline silicon film as a semiconductor film.

[0050]

As described above in detail, according to the present invention, there is provided a method of manufacturing an array substrate for a display device capable of preventing the occurrence of contact failure and improving the manufacturing yield of the array substrate. You can

[Brief description of drawings]

FIG. 1 is a sectional view showing an array substrate manufactured by a manufacturing method according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a manufacturing process of the array substrate.

FIG. 3 is a cross-sectional view for explaining a manufacturing process of the array substrate.

FIG. 4 is a plan view showing a film forming apparatus used in the manufacturing process of the array substrate.

[Explanation of symbols]

Reference numeral 10 ... Glass substrate, 14 ... Scan line 14a ... Scan line connecting end, 15 ... Signal line 16 ... Signal line connecting pad, 18 ... Scan line connecting pad 20 ... TFT, 24 ... Drain electrode 26 ... Source electrode, 28 ... Pixel electrode 31, 35, 52 ... Contact hole 30 ... Interlayer insulating film, 32 ... First gate insulating film 34 ... Second gate insulating film, 36 ... Semiconductor film 37 ... Low resistance semiconductor film, 40 ... Channel protective film 50 ... Film forming apparatus , 58 ... Spin cleaning unit 62 ... Preheating chamber, 64 ... Film forming chamber

   ─────────────────────────────────────────────────── ─── Continued front page    (71) Applicant 390009531             International Business Machine             'S Corporation             INTERNATIONAL BUSIN             ESS MASCHINES CORPO             RATION             United States 10504, New York             Armonk New Orchard Draw             Do (72) Inventor Akira Hirahara             2 shares, 1-9-1 Harara-cho, Fukaya City, Saitama Prefecture             Company Toshiba Fukaya Factory (72) Inventor Kiyotsugu Mizouchi             2 shares, 1-9-1 Harara-cho, Fukaya City, Saitama Prefecture             Company Toshiba Fukaya Factory (72) Inventor Chen Yongfeng             800 Miyake, Yasu-cho, Yasu-gun, Shiga Prefecture             Japan IBM Corporation Yasu Office             Within F term (reference) 2H092 GA13 GA16 GA17 GA21 GA25                       GA26 GA28 HA04 JA24 JA27                       JA34 JA35 JA36 JA37 JA40                       JB01 JB04 JB13 JB16 JB22                       JB24 JB33 JB56 KB01 KB11                       KB12 MA01 MA05 MA08 MA12                       MA13 MA17 MA28 MA29 MA35                       MA42 MA43 NA01 NA07 NA11                       NA18 NA29                 5C094 AA42 BA02 BA43 EA04 EA10                       FB12 GB10 HA08                 5F110 AA26 BB01 CC07 DD02 DD03                       EE06 EE44 FF02 FF03 FF09                       FF30 GG02 GG13 GG15 GG25                       GG45 HK03 HK04 HK09 HK16                       HK22 HK33 HK35 HL07 HL26                       HL27 NN02 NN12 NN24 NN35                       NN72 QQ09 QQ12                 5G435 AA16 AA17 BB12 HH20 KK05                       LL06 LL07 LL08

Claims (8)

[Claims] 1. A scanning line arranged on a substrate, a first insulating film laminated on the substrate so as to overlap the scanning line, a semiconductor film arranged on the first insulating film, A thin film transistor including a source electrode and a drain electrode electrically connected to the semiconductor film; and a low-resistance semiconductor film interposed between the source electrode and the drain electrode and the semiconductor film; A pixel line electrically connected to the source electrode through a signal line extending out and extending substantially orthogonal to the scanning line and a contact hole of a second insulating film disposed on the source electrode and the drain electrode. And a step of cleaning the substrate after forming the contact holes, and preheating the cleaned substrate at a predetermined temperature to remove residual moisture. A drying step of removing, a step of forming a transparent conductive film in an amorphous state on the substrate without exposing the preheated substrate to the atmosphere after the drying step, and heating the substrate to A method of manufacturing an array substrate for a display device, comprising: an annealing step of crystallizing a transparent conductive film in an amorphous state. 2. The substrate is treated with 100 in the drying step.
The method of manufacturing an array substrate for a display device according to claim 1, further comprising preheating to a temperature of ℃ or more and drying. 3. The display device according to claim 2, wherein, in the drying step, the substrate is preheated to a temperature substantially the same as the substrate temperature at the time of forming the transparent conductive film and dried. Array substrate manufacturing method. 4. The substrate is treated with 100 in the drying step.
4. The method for manufacturing an array substrate for a display device according to claim 1, further comprising preheating to a temperature of .degree. C. to 120.degree. C. and drying. 5. The method for manufacturing an array substrate for a display device according to claim 1, wherein in the drying step, the substrate is preheated in an Ar gas atmosphere. 6. The substrate is subjected to a pressure of 1 in the drying step.
The method for manufacturing an array substrate for a display device according to claim 5, wherein preheating is performed in an Ar gas atmosphere of 00 Pa or more. 7. The display according to claim 1, wherein the drying step is performed in a preheating chamber of a film forming apparatus for forming the amorphous conductive film. Method of manufacturing array substrate for device. 8. A pixel is formed from an amorphous indium tin oxide formed by introducing H ₂ 0 mainly by using at least one gas of Ar and Kr by a sputtering method in the step of forming the pixel electrode. An electrode is formed, The manufacturing method of the array substrate for display devices of any one of Claim 1 thru | or 7 characterized by the above-mentioned.