JP2003017707A - Method of manufacturing array substrate of display unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing an array substrate, where display nonuniformity is prevented from occurring without deteriorating the characteristics of a TFT. SOLUTION: A semiconductor film whose hydrogen concentration is 8 at.% or above is formed as the semiconductor film 36 of a thin film transistor 20, and then a pixel electrode 28 electrically connected to the source electrode of the thin film transistor 20 is formed by the use of an amorphous transparent conductive film. In succession, the semiconductor film and the pixel electrode are subjected to annealing to turn the pixel electrode crystalline from an amorphous state. Annealing is carried out under the condition that an increase rate of hydrogen concentration around the interface of a semiconductor film amounts to 20% or below after annealing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an array substrate used for a flat display device such as a liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, flat-panel display devices that replace CRT displays have been actively developed, and liquid crystal display devices have attracted particular attention because of their advantages such as light weight, thin shape, and low power consumption. For example, an active matrix type liquid crystal display device in which a switch element is arranged for each display pixel is
It has a structure in which a liquid crystal layer is held between an array substrate and a counter substrate via an alignment film.

The array substrate has a plurality of signal lines and scanning lines arranged in a grid pattern on a transparent insulating substrate such as glass or quartz. Amorphous silicon (hereinafter referred to as "amorphous silicon") is formed at each intersection of the signal lines and the scanning lines. , A-Si: H) and other thin film transistors (hereinafter abbreviated as TFT) using semiconductor thin films are connected. The gate electrode of the TFT is electrically connected to the scanning line, the drain electrode is electrically connected to the signal line, and the source electrode is transparent conductive material such as I.
It is connected to a pixel electrode made of TO (indium-tin-oxide).

In the counter substrate, a counter electrode made of ITO is arranged on a transparent insulating substrate such as glass, and if a color display is realized, color filter layers are stacked.

[0005]

The array substrate described above is annealed in the final step of the manufacturing process to stabilize the TFT characteristics and crystallize the amorphous ITO. However, under this annealing condition, for example, when the temperature is high, hydrogen in the a-Si: H film becomes a-Si: H.
They gather near the interface of the H film. Then, when the annealing temperature is high, this hydrogen generation becomes intense, and a void is generated at the interface between the n ⁺ Si film arranged as the ohmic contact layer and the a-Si film.

Results of analyzing the hydrogen concentration in the a-Si: H film
As a result, as the annealing temperature increases, hydrogen becomes aS
It can be seen that the i: H film moves to the vicinity of the interface. this
Time n ⁺Inside the a-Si film, as hydrogen diffuses,
The Fermi level approaches the center of the forbidden band, and the Hall current
The blocking effect of will deteriorate. Therefore, TF
The hole current that flows when T is off increases and this array substrate
When a liquid crystal display device is constructed using a plate, the holding characteristic
It is observed as display unevenness due to flicker.

On the contrary, if the annealing treatment is insufficient, the crystallization of the amorphous ITO is insufficient, the specific resistance of the pixel electrode is increased, and the corrosion resistance against chemicals and humidity is deteriorated.

The present invention has been made in view of the above points, and an object thereof is to manufacture an array substrate capable of preventing the occurrence of display unevenness without deteriorating TFT characteristics. It is to provide a manufacturing method of.

[0009]

To achieve the above object, according to the manufacturing method of the present invention, it is possible to prevent undesired migration of hydrogen in the semiconductor film by appropriately setting the conditions of the annealing treatment. At the same time, the pixel electrode made of a transparent conductive film in an amorphous state is favorably crystallized.

That is, in the method of manufacturing the array substrate according to the present invention, the semiconductor film arranged via the insulating film with respect to the gate electrode connected to the scanning line and the source electrically connected to the semiconductor film. A thin film transistor including an electrode and a drain electrode, a low-resistance semiconductor film interposed between the source electrode and the drain electrode, and the semiconductor film, and extending from the drain electrode and substantially orthogonal to the scanning line. In a method of manufacturing an array substrate for a display device, which includes an extended signal line and a pixel electrode electrically connected to the source electrode, a step of forming a semiconductor film having a hydrogen concentration of 8 at% or more; The method further includes a step of forming the pixel electrode with a transparent conductive film in a crystalline state, and an annealing step of annealing the semiconductor film and the pixel electrode to crystallize the pixel electrode. Neil process, the hydrogen concentration increase in the vicinity of the interface of the semiconductor film after the annealing process is 20%
The feature is that the annealing is performed under the following annealing conditions.

Further, according to the array substrate manufacturing method of the present invention, in the annealing step, the annealing temperature and the annealing time are set so that the product of the annealing temperature and the annealing time is in the range of about 6900 to 7650. It is characterized by doing.

Further, according to the array substrate manufacturing method of the present invention, the annealing temperature is set to 230 ° C. to 255 ° C.
It is desirable to set the temperature in the range of 0 ° C., and the pixel electrode is formed by forming indium tin oxide at a temperature of 150 ° C. or less by a sputtering method.

According to the array substrate manufacturing method configured as described above, the annealing conditions are optimized,
An undesired increase in hydrogen concentration near the interface of the semiconductor film can be suppressed, TFT characteristics can be stabilized, and an array substrate having crystallized pixel electrodes can be obtained. Therefore, by using this array substrate, it is possible to obtain a liquid crystal display device in which the occurrence of display unevenness is prevented and the image quality is improved.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. First, an array substrate of a liquid crystal display device manufactured by the manufacturing method according to the embodiment of the present invention will be described.

As shown in FIG. 1, the array substrate has a plurality of scanning lines 14 provided on a transparent insulating substrate 10 such as glass or quartz, and a plurality of signal lines 15 substantially orthogonal to the scanning lines. I have it. Each signal line 15 is one of the insulating substrate 10.
The signal line connection pad 16 is provided near one of the two edges and is provided at that end. In addition, each scanning line 14 is a substrate 1
The scanning line connection pad 18 is provided near the other end of the scanning line 0.

A TFT 20 using a semiconductor thin film is connected to each intersection of the scanning line 14 and the signal line 15.
In the TFT 20, the scanning line 14 itself is used as a gate electrode, and the first gate insulating film 32 and the second gate insulating film 3 are formed thereon.
4 and a drain electrode 24 and a source electrode 26 provided on the semiconductor film 36 via a low resistance semiconductor film 37 arranged as an ohmic contact layer. The drain electrode 24 of the TFT 20 is electrically connected to the signal line 15, and the source electrode 26 is connected to the light transmissive pixel electrode 28 made of, for example, ITO.

The connection end 15a of the signal line 15 constitutes the signal line connection pad 16 together with the pad member 31a arranged in the contact hole 31 formed in the interlayer insulating film 30 as the third insulating film, and also scans. Connection end 14 of wire 14
The a constitutes the scanning line connection pad 18 together with the pad member 35a arranged in the contact hole 35 formed in the interlayer insulating film 30 and the first gate insulating film 32.
These pad members 31a and 35a are formed simultaneously with the pixel electrode 28.

The pixel electrode 28 is arranged for the scanning line 14 via the first gate insulating film 32 and the interlayer insulating film 30, and for the signal line 15 via the interlayer insulating film 30. Are arranged. In addition, in order to achieve a high aperture ratio, it is possible to overlap the end portion of the pixel electrode 28 with a part of the scanning line 14 or the signal line 15 in a plane. Next, a more detailed structure of the array substrate will be described along with a method of manufacturing the array substrate.

First, as shown in FIG. 2A, a MoW alloy film of 300 is formed on the insulating substrate 10 by sputtering.
After depositing to a thickness of nm, a resist is applied, and the resist is exposed and developed using the first mask pattern to form a first resist pattern. Then, through the patterning (first patterning) using the first resist pattern as a mask, the plurality of scanning lines 14 and the auxiliary capacitance lines 38 are formed on the insulating substrate 10. Each scanning line 14 has a connection end portion 14 a extended to one end side of the insulating substrate 10.

Then, as shown in FIG. 2B, CVD
A first gate insulating film 32 made of a silicon oxide film is deposited to a thickness of 150 nm by a (chemical vapor deposition) method. A second gate insulating film 34 made of a silicon nitride film having a thickness of 150 nm, a semiconductor film 36 made of a-Si: H having a thickness of 50 nm, and a channel protective film made of a silicon nitride film having a thickness of 200 nm are formed thereon by a CVD method. , Continuous film formation without exposure to the atmosphere. The semiconductor film 3
The hydrogen concentration in 6 is set to about 8 at% or more.

Control of hydrogen concentration in the semiconductor film 36
Is the silane (SiH _Four) Gas and hydrogen
(H₂) Achieved by adjusting the mixing ratio with gas, film forming temperature, etc.
Is made. For example, in this embodiment, silane (SiH
_Four) Gas flow rate is 600sccm, hydrogen (H₂) Gas flow rate
2000sccm, power 2kW, film formation temperature 350 ° C
The hydrogen concentration in the film was set to 9 at%.

Then, a resist is applied on this and a second resist pattern self-aligned with the scanning line 14 is formed by a backside exposure technique using the scanning line 14 as a mask, and this second resist pattern is used as a mask. The protective film is patterned (second patterning) to form an island-shaped channel protective film 40.

After that, as shown in FIG. 2C, the semiconductor film 36 is formed so that a good ohmic contact can be obtained.
The exposed surface is treated with hydrofluoric acid, and a low-resistance semiconductor film 37 made of n + a-Si: H containing phosphorus as an impurity and having a thickness of 30 nm is deposited thereon by the CVD method. Next, a laminated film 50 including a Mo layer having a thickness of about 25 nm, an Al layer having a thickness of about 350 nm, and a Mo layer having a thickness of about 50 nm is deposited by a sputtering method. Then, a resist is applied and the third
Exposure and development are performed using the master pattern to form a third resist pattern, and using this third resist pattern as a mask, a mixed acid of phosphoric acid, nitric acid, acetic acid, and water is used to form Mo.
The / Al / Mo laminated film 50 is wet-etched. Thereby, the source electrode 26, the drain electrode 24, and the signal line integrated with the drain electrode are formed.

Then, using the third resist pattern or the source electrode 26, the drain electrode 24, and the signal line as a mask, the low resistance semiconductor film 37, the semiconductor film 36,
Then, the second gate insulating film 34 is collectively patterned by the RE (plasma etching) method (third patterning). At this time, the etching selection ratio with respect to the channel protective film 40 is appropriately controlled.

As a result, the semiconductor film 36, the low resistance semiconductor film 37, the source electrode 26, the signal line 15, the connection end integrated with the signal line, and the drain electrode 24 integrated with the signal line.
Is formed. At the same time, the second gate insulating film 34 made of a silicon nitride film other than the third resist pattern is completely removed.

Then, the semiconductor film 36 and the low resistance semiconductor film 3 are formed.
Since the 7, the source electrode 26, the drain electrode 24, and the second gate insulating film 34 are etched based on the common third resist pattern, a slight step difference occurs due to the difference in the over-etching amount, but at the portion of the TFT 20. , The contours are formed so as to substantially coincide with each other.

Subsequently, as shown in FIG. 3A, an interlayer insulating film 30 made of a silicon nitride film having a thickness of 200 nm is deposited over the entire surface of the substrate, and then a resist is applied,
The resist is exposed and developed using the fourth master pattern,
A fourth resist pattern is formed. Then, the interlayer insulating film 30 is patterned (fourth patterning) based on the fourth resist pattern by wet etching with BHF (buffered hydrofluoric acid), and the contact hole 52 communicating with the source electrode 41 and the connection end of the signal line 42. A contact hole 31 (see FIG. 1) communicating with the. At the same time, the first gate insulating film 32 and the interlayer insulating film 30 in the portion facing the connection end 14 a of the scanning line 14 are continuously and collectively removed to form a contact hole 35.

After that, as shown in FIG. 3B, an ITO film in an amorphous state having a thickness of 40 nm is formed over the entire surface of the substrate.
That is, amorphous ITO is deposited at a temperature of 150 ° C. or lower, for example, room temperature by a water-added sputtering method, and a resist is applied thereon. Then, the resist is exposed and developed using the fifth master pattern to form a fifth resist pattern, and the amorphous ITO film is patterned with oxalic acid based on the fifth resist pattern (fifth patterning).

As a result, the pixel electrode 28 electrically connected to the source electrode 26 through the contact hole 52 is formed, and at the same time, the scanning line 14 is formed through the contact hole 35.
A pad member 35a made of the same material as the pixel electrode 28 and connected to the connection end 14a of the pixel electrode 28, and a pad member 31a made of the same material as the pixel electrode 28 and connected to the connection end of the signal line 15 through the contact hole 31. .

Then, the whole substrate is kept at 240 ° C. for 30 minutes.
Annealing is performed by heating in an oven with a nitrogen atmosphere.
The characteristics of the TFT 20 are stabilized, and the pixel electrode made of amorphous ITO is crystallized.

When performing the annealing process, the annealing conditions are set as follows. That is, with respect to the annealing temperature and the annealing time during the annealing process, the increase rate of the hydrogen concentration near the interface of the semiconductor film 36 after the annealing process is about 20.
Set it so that it is less than or equal to%. By controlling the annealing temperature and the annealing time during the annealing treatment so that the rate of increase in the hydrogen concentration near the interface of the semiconductor film 36 is about 20% or less, the increase in the hydrogen concentration near the interface of the semiconductor film 36 is suppressed. It is possible to reduce off-leakage and eliminate display unevenness due to variations in holding characteristics. here,
The vicinity of the interface of the semiconductor film 36 is the position where the impurities in the low resistance semiconductor film 37, here phosphorus, starts to decrease at the boundary between the low resistance semiconductor film 37 and the semiconductor film 36.
When the main surface of No. 6 is used, it means a region extending from this main surface to about 50 angstroms in the thickness direction of the semiconductor film.

Regarding the annealing temperature in the annealing treatment, for example, as shown in FIG. 4, when the annealing temperature rises and exceeds, for example, 260 ° C., hydrogen in the semiconductor film diffuses and the movement to the vicinity of the interface of the semiconductor film 36 is remarkable. Therefore, since the hydrogen concentration near the interface of the semiconductor film 36 increases, the increase rate exceeds 20% depending on the processing time, and the control thereof becomes difficult.

Moreover, as a result of inspecting the display characteristics of a liquid crystal display device using an array substrate manufactured by changing the annealing temperature and the annealing time, as shown in FIG. 5, the annealing temperature and the annealing time are shown. 240 ° C, 3
In the case of 0 minutes, the occurrence rate of display unevenness is 0%, 250 ° C., 30
Minute 0%, 250 ° C, 40 minutes 0.43%, 260
It was 0.35% at 30 ° C. for 30 minutes. Furthermore, to fully crystallize the pixel electrode made of amorphous ITO, 2
It has been found that annealing at 30 ° C. for 30 minutes or more is required.

From the above, the annealing temperature and the annealing time during the annealing treatment are calculated by multiplying these products (temperature x minutes).
Is set within the range of about 6900 to 7650.
In this case, the annealing temperature is preferably set to 230 ° C. or higher, for example, in the range of 230 ° C. to 255 ° C. in consideration of sufficient crystallization of amorphous ITO and control of hydrogen concentration. By performing the annealing treatment under such an annealing condition, the TFT characteristics can be stabilized without increasing the hydrogen concentration near the interface of the semiconductor film 36 by 20% or more, and the pixel electrode 28 can be reliably formed. Therefore, off-leakage can be reduced, and display unevenness due to variations in holding characteristics can be eliminated.

The manufacturing of the array substrate is completed by the above-mentioned annealing treatment. A liquid crystal display device was assembled using the array substrate manufactured in this manner, and a screen display inspection was conducted. As a result, no display unevenness was confirmed, and good display could be obtained.

As described above, according to the above-described array substrate manufacturing method, by optimizing the annealing conditions,
The TFT characteristics can be stabilized without increasing the hydrogen concentration near the interface of the semiconductor film 36 by 20% or more, and the array substrate having the crystallized pixel electrode 28 can be obtained. Therefore, by using this array substrate, it is possible to obtain a liquid crystal display device in which the occurrence of display unevenness is prevented and the image quality is improved.

The present invention is not limited to the above-described embodiments, but can be variously modified within the scope of the present invention. For example, the shape, thickness, forming method, etc. of each film forming the array substrate can be variously modified as necessary. Further, the driving circuit portion may be integrally formed in the peripheral region of the glass substrate. Furthermore, the pixel electrode is not limited to ITO, and it is possible to use another transparent conductive film.

[0038]

As described above in detail, according to the present invention, the TF is optimized by optimizing the annealing temperature and time.
It is possible to provide a method for manufacturing an array substrate that can prevent the occurrence of display unevenness without degrading T characteristics.

[Brief description of drawings]

FIG. 1 is a sectional view showing an array substrate manufactured by a manufacturing method according to an embodiment of the present invention.

FIG. 2 is a sectional view for explaining a manufacturing process of the array substrate.

FIG. 3 is a cross-sectional view for explaining the manufacturing process of the array substrate.

FIG. 4 is a diagram showing a relationship between hydrogen distribution in a semiconductor film and annealing temperature.

FIG. 5 is a diagram showing the relationship between annealing conditions and the occurrence of display unevenness.

[Explanation of symbols]

10 ... Glass substrate 14 ... Scan line 14a ... Scan line connection end 15 ... Signal line 16 ... Signal line connection pad 18 ... Scan line connection pad 20 ... TFT 24 ... Drain electrode 26 ... Source electrode 28 ... Pixel electrode 31, 35, 52 ... Contact holes 30 ... Interlayer insulating film 32 ... First gate insulating film 34 ... Second gate insulating film 36 ... Semiconductor film 37 ... Low-resistance semiconductor film 40 ... Channel protective film

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09F 9/35 H01L 29/78 618F H01L 21/336 616L (71) Applicant 390009531 International Business Machines Corporation INTERNATIONAL BUSIN ESS MASCHINES CORPO RATION United States 10504, New York, Armonk New Orchard Road (72) Inventor Akira Kubo 1-chome, Harara-cho, Fukaya-shi, Saitama, Ltd. Toshiba Fukaya Factory (72) Inventor Kenji Okajima Shiga 800 Miyake, Yasu-machi, Yasu-gun, Japan F-Term (reference) in Yasu branch of IBM Japan, Ltd. 2H092 HA04 JA24 JA46 KA12 MA05 MA08 MA12 MA29 NA01 NA24 NA29 5C094 AA03 AA43 BA03 BA43 CA19 EA04 EA05 EA07 FB14 JA01 5F110 AA17 AA19 CC07 DD02 DD03 EE06 EE44 FF02 FF03 FF09 FF29 GG02 GG05 NN15QA QN NN15QA QN NN15QA QN NNQA QN NNQA NNQA NNQA NNQA NNQA NNQA NNQA NNQA QAQA NNQA QA NNQA QAQA KK09 KK10

Claims (4)

[Claims] 1. A semiconductor film arranged via an insulating film to a gate electrode connected to a scanning line, a source electrode and a drain electrode electrically connected to the semiconductor film, and the source electrode and the drain. A thin film transistor including a low-resistance semiconductor film interposed between an electrode and the semiconductor film, a signal line extending from the drain electrode and extending substantially orthogonal to the scan line, and the source electrode and the electrical line. A method for manufacturing an array substrate for a display device including a pixel electrode electrically connected to the pixel electrode, the step of forming a semiconductor film having a hydrogen concentration of 8 at% or more, and the pixel electrode using a transparent conductive film in an amorphous state. And an annealing step of crystallizing the pixel electrode by annealing the semiconductor film and the pixel electrode, wherein the annealing step is performed after the annealing treatment. Method of manufacturing an array substrate for a display device in which the hydrogen concentration increase in the vicinity of the interface of the body film and performing the annealing conditions of 20% or less. 2. The display device according to claim 1, wherein in the annealing step, the annealing temperature and the annealing time are set such that the product of the annealing temperature and the annealing time is in the range of approximately 6900 to 7650. Of manufacturing an array substrate for a wafer. 3. The annealing temperature is 230 ° C. to 255.
The method for manufacturing an array substrate for a display device according to claim 2, wherein the temperature is set within a range of ° C. 4. Indium tin oxide 150
The method for manufacturing an array substrate for a display device according to claim 1, wherein the pixel electrodes are formed by forming a film by a sputtering method at a temperature of not more than ° C.