JP2000101086A - Fabrication of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fabrication method of semiconductor device in which fabrication time can be shortened while ensuring high fabrication yield. SOLUTION: The fabrication method of semiconductor device comprises a step of forming a first thin film 27 of non single crystal silicon on an insulating substrate 10, a step for forming a second thin film on the first thin film 27, a step for forming mask patterns 30, 31 by etching the second thin film, and a step for forming an ohmic contact region 28 by implanting impurity ions into the first thin film 27 through the mask patterns 30, 31 wherein the step of forming mask patterns 30, 31 and the step of implanting ions are carried out continuously without being exposed to the atmosphere.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device such as a thin film transistor formed on an insulating substrate.

[0002]

2. Description of the Related Art A technique for forming a semiconductor device such as a thin film transistor (TFT) on an insulating substrate such as glass or quartz has been used in various fields including an active matrix type liquid crystal display device, and has attracted attention.

In a conventional TFT, amorphous silicon (a-Si: H) or the like is used for an active layer.
+ A-Si: Source and drain electrodes are arranged via an ohmic contact layer such as H.

FIGS. 3A, 3B and 3C are schematic sectional views of a typical TFT. FIG. 3 (a) and (b)
Is a TFT having an inverted staggered structure, in which a gate electrode 2 on a substrate 1, a gate insulating film 3 covering the gate electrode 2, an a-Si: H film 4, and an a-Si: H film 4 on the gate insulating film 3 Source and drain electrodes 8a, 8b, a-
Ohmic contact layers 7a and 7b made of n + a-Si: H interposed between the Si: H film 4 and the source and drain electrodes 8a and 8b. The TFT shown in FIG. 3A is called a channel protective film type TFT unlike the TFT of FIG. 3B in that the channel protective film 6 is disposed on the a-Si: H film 4. TFT shown in FIG. 3 (b)
Is called a back channel cut type TFT.

FIG. 3C shows a TFT having a staggered structure or a coplanar structure. The source and drain electrodes 8a and 8b, a-Si: H film 4, and a-Si: H film 4 are formed on a substrate 1.
A gate insulating film 3 disposed thereon, a gate electrode 2 disposed on the gate insulating film 3, and n + a interposed between the a-Si: H film 4 and the source and drain electrodes 8a and 8b.
-Si: H ohmic contact layers 7a, 7b
And

[0006]

In each of the above-described TFTs, a method of individually depositing an ohmic contact layer made of n + a-Si: H or the like is employed. Attempts have been made to form an ohmic contact region by doping impurity ions into a semiconductor film such as a Si: H film via a gate electrode or a corresponding mask.

However, conventionally, each of the patterning step and the ion implantation step is performed by a separate manufacturing apparatus. For this reason, manufacturing of a semiconductor device represented by a TFT requires an expensive individual device and a long manufacturing time, and it has been difficult to sufficiently reduce the manufacturing cost. In addition, semi-finished products may accumulate between manufacturing apparatuses, and this undesired accumulation may cause adhesion of fine particles in the air and adsorption of moisture on the surface of the element region on the substrate, thereby lowering the production yield. I understand.

SUMMARY OF THE INVENTION The present invention has been made in view of the above technical problems, and has as its object to provide a method of manufacturing a semiconductor device capable of greatly reducing the time required for manufacturing and the number of expensive devices. Another object of the present invention is to provide a method of manufacturing a semiconductor device in which the retention of undesired semi-finished products during manufacturing is reduced, thereby achieving a high manufacturing yield.

[0009]

According to the first aspect of the present invention,
Forming a first thin film made of a non-single-crystal silicon thin film on an insulating substrate, forming a second thin film on the first thin film, and forming a mask pattern by etching the second thin film; Implanting impurity ions into the first thin film through the mask pattern to form an ohmic contact region, wherein the mask pattern forming step and the ion implantation step are performed by: A method of manufacturing a semiconductor device, wherein the method is performed continuously without being exposed to the air.

The invention according to claim 7 is a step of forming a first thin film made of a non-single-crystal silicon thin film on an insulating substrate, a step of forming a second thin film on the first thin film, Forming a resist pattern on the thin film; etching the second thin film based on the resist pattern to form a mask pattern; implanting impurity ions into the first thin film through the mask pattern to form an ohmic contact Forming a region, after the mask pattern forming step or after the ion implantation step, including a step of removing the resist pattern, the mask pattern forming step, The method of manufacturing a semiconductor device, wherein the ion implantation step and the removing step are performed continuously without being exposed to the air. That.

The invention according to claim 8 provides a step of forming a gate electrode on an insulating substrate, a step of depositing a gate insulating film on the gate insulating film, and a step of forming a non-single crystal on the gate insulating film. Depositing a first thin film made of a silicon thin film, depositing a second thin film on the first thin film, forming a resist pattern corresponding to the gate electrode on the second thin film, Manufacturing a semiconductor device, comprising: a step of forming a mask pattern by etching the second thin film based on a pattern; and a step of forming an ohmic contact region by implanting impurity ions into the first thin film through the mask pattern. A method, after the mask pattern forming step or after the ion implantation step, including a step of removing the resist pattern,
A method of manufacturing a semiconductor device, wherein the mask pattern forming step, the ion implantation step, and the removing step are performed continuously without being exposed to the air.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings, taking an example of manufacturing an array substrate for a TFT-LCD. First, FIG.
As shown in (a), the outer dimensions are 500 mm x 600 m
m, a transparent glass substrate 10 having a thickness of 0.7 mm is prepared,
A 300 nm thick Al-Nd alloy film and 5
A Mo film having a thickness of 0 nm is sequentially deposited by a sputtering method, and is patterned into a predetermined shape to form a gate electrode 20a, 2
0b, a scanning line (not shown) integrated with the gate electrode, an oblique wiring portion (not shown) extending from the scanning line, and OLB pad portions 21a and 21b connected to the oblique wiring portion are formed.

Next, as shown in FIG. 1B, a 150 nm thick silicon oxide (SiOx) is used as a gate insulating film.
Film 23 and 150 nm thick silicon nitride (SiNx)
The film 25 has a thickness of 50 as a semiconductor layer serving as an active layer.
nm-thick amorphous silicon (a-Si: H) thin film 27 and a silicon nitride (SiNx) film 29 having a thickness of 300 nm
Is continuously deposited by a plasma CVD method at a substrate temperature of 300 ° C. Here, an a-Si: H thin film capable of ensuring relatively uniform film quality over a large area is used as the semiconductor layer, but various other semiconductor films such as a polycrystalline silicon thin film can be used.

A photoresist is applied thereon, and the resist is selectively applied to the regions corresponding to the gate electrodes 20a and 20b by back exposure using the gate electrodes 20a and 20b as a mask, as shown in FIG. The pattern 31 is formed. In this embodiment, the photoresist is developed with a chemical solution, but dry development can also be performed in a plasma processing apparatus 100 described later.

Then, such a substrate 10 is carried into the plasma processing apparatus 100 shown in FIG. Here, the plasma processing apparatus 100 will be described with reference to FIG. The plasma processing apparatus 100 includes a susceptor 110 that supports the substrate 10, a vacuum chamber 120 that houses the susceptor 110, a pump 130 that communicates with the vacuum chamber 120 and maintains a vacuum in the chamber 120, and a plasma chamber 120 that communicates with the vacuum chamber 120. A gas supply system 140 for supplying a desired gas into the chamber 120, a dielectric 150 made of ceramic or the like, which is hermetically disposed on the upper surface of the vacuum chamber 120 facing the susceptor 110, and disposed on the dielectric 150 An antenna 160 for applying a high frequency, a first high frequency source 170 for applying a high frequency to the antenna 160, a second high frequency source 180 connected to the susceptor 110, and a control unit 190 for controlling the second high frequency source 180. It is configured with.

The susceptor 1 of the plasma processing apparatus 100
The substrate 10 is placed on the substrate 10 and the inside of the chamber 120 is maintained at a vacuum of 50 to 100 mTorr. Then, while applying a high frequency of 13.56 MHz at 3000 W to the first high frequency source 170, the gas supply system 140 supplies the high frequency of 250 seconds.
After supplying CHF3 of ccm3 and O2 of 50 sccm to stabilize the plasma discharge, a high frequency of 6.0 MHz and 500 W is applied to the susceptor 110 from the second high frequency source 190 under the control of the control unit 190.

The CHF3 and O2 gases ionized or radicalized by the plasma are drawn into the substrate 10 by a self-bias of about -10 V of the substrate 10, and the SiNx film 29 is patterned substantially vertically based on the resist pattern 31. An etching protection film 30 is formed as shown in FIG.

Then, after exhausting the residual gas in the chamber 120, the first high-frequency source 170 is supplied with a power of 13.5 at 2000 W.
While applying a high frequency of 6 MHz, the gas supply system 140
After supplying a PH3 of 20 sccm from the above and stabilizing the plasma discharge, a 2 MHz high frequency of 1500 W is applied to the susceptor 110 from the second high frequency source 190 under the control of the control unit 190. The PH3 gas ionized or radicalized by the plasma is drawn into the substrate 10 by a self-bias of about -200 V of the substrate 10, and the ion implantation is achieved. In this embodiment, the time was controlled to control the dose of phosphorus (P) ions to 1.times.10@16 ions / cm @ 2. Thus, ohmic contact regions 31 and 33 were formed in the a-Si thin film 27.

The ohmic contact regions 31, 33
May be formed over the entire thickness direction of the a-Si thin film 27, or may be formed only near the surface layer. In this embodiment, the a-Si thin film 2
The implantation amount of P ions was set to 1 × 10 16 ions / cm 2 in a region of 8 nm in the thickness direction from the surface layer of No. 7. This is a-
This is to reduce the damage that the Si thin film 27 receives by ion implantation.

After that, the residual gas in the chamber 120 is exhausted, and the first high-frequency source 170 is supplied with a power of 13.5 at 2000 W.
While applying a high frequency of 6 MHz, the gas supply system 140
Supply 50 sccm of CF4 and 950 sccm of O2 from the above to stabilize the plasma discharge. At this time, the self-bias of the substrate 10 is substantially zero, and the CDE based on CF4 and O2 gas ionized or radicalized by the plasma.
In the mode, the resist mask 31 is removed by ashing.

After that, the above substrate was transferred to another processing apparatus and heat-treated at a temperature of about 250 ° C. for 1 hour in a nitrogen atmosphere to activate the impurities. Next, an Al-Nd alloy film having a thickness of 300 nm is deposited by a sputtering method, a resist is applied thereon, and exposure and development are performed to form a resist pattern. Then, the substrate 10 is placed on the susceptor 110 of the same plasma processing apparatus 100 as described above,
The inside of the chamber 120 is maintained at a vacuum of 10 mTorr.
Thereafter, the first high-frequency source 170 is supplied with 1000 W at 13W.
While applying a high frequency of 56 MHz, the gas supply system 14
0 to 500 sccm Cl2 and 500 sccm BC
13 to stabilize the plasma discharge, and then control the second high-frequency sources 190 to 200 under the control of the control unit 190.
A high frequency of 6 MHz is applied to the susceptor 110 at W.

The Cl2 and BCl3 gases ionized and radicalized by the plasma are rapidly drawn into the substrate side by a self-bias of about -10 V of the substrate 10, and RIE is performed.
In the mode, the Al—Nd alloy film is patterned substantially vertically based on the resist pattern, and as shown in FIG. 3F, the signal lines (not shown) integrated with the source and drain electrodes 33 and 35 and the drain electrode 33. Then, an oblique wiring portion (not shown) extending from the signal line and an OLB pad portion 37 connected to the oblique wiring portion are formed.

Thereafter, after the residual gas in the chamber 120 is exhausted, the first high-frequency source 170 is supplied with 3000 W at 1 W.
A high frequency of 3.56 MHz was applied, and CF4 was 250 sccm and O2 was 50 scc from the gas supply system 140.
m to stabilize the plasma discharge. At this time, the self-bias of the substrate 10 is substantially zero, and the CDE mode based on CF4 and O2 gas ionized or radicalized by plasma causes source and drain electrodes 33, 35, signal lines, oblique wiring portions, and OLB pad portions 37. Corresponding to a
-The Si thin film 27 and the SiNx film 25 are selectively removed.

Thereafter, after the residual gas in the chamber 120 is exhausted, the first high-frequency source 170 is supplied with 1 W at 2000 W.
A high frequency of 3.56 MHz was applied and 50 sccm of CF4 and 950 scc of O2 were supplied from the gas supply system 140.
m to stabilize the plasma discharge. At this time, the self-bias of the substrate 10 is substantially zero, and the resist mask 31 is removed by ashing in the CDE mode based on CF4 and O2 gas ionized or radicalized by the plasma.

Thereafter, as shown in FIG. 2G, an organic resin such as polyimide or acrylic is applied in a thickness of 3 μm on the entire surface of the substrate, dried and cured to form an interlayer insulating film 39. This interlayer insulating film 39 has a function of smoothing in addition to a function as interlayer insulation. Then, the interlayer insulating film 39 and the SiOx film 2 on the OLB pad portions 21a and 21b
3. The contact holes 41, 43, and 45 are formed by selectively removing the interlayer insulating film 39 on the OLB pad portion 37 and the interlayer insulating film 39 on the source electrode 35, respectively.

Then, a transparent conductive film such as ITO (Indium Tin Oxide) is deposited by a sputtering method, and is patterned into a desired shape to form a pixel electrode 51 and an OLB pad electrode 5.
3 and 55 are respectively formed.

Thereafter, a protective film is formed with a silicon nitride film or the like as necessary. As described above, according to this embodiment, the patterning of the SiNx film 29, the ion implantation of phosphorus (P) ions, and the ashing of the resist mask 31 are continuously performed in the same chamber 120, thereby reducing the manufacturing time. Was significantly reduced compared to

In addition, the production yield was significantly improved as compared with the prior art, probably because there was no undesired stagnation of the semi-finished product during the process. Further, as described above, the RIE device, the CDE device, the ion implantation device, and the ashing device can be combined into one manufacturing device, so that the investment for the device can be significantly reduced and the occupied area of the device can be significantly reduced. Was.

In this embodiment, as the plasma processing apparatus, the simplest batch type single chamber type is exemplified, but a plasma lock apparatus in which a load lock chamber and an unload lock chamber are air-tightly connected to a vacuum chamber, and a plurality of plasma processing apparatuses are provided in a common vacuum chamber. Needless to say, various types such as a cluster type in which the vacuum chambers are hermetically connected can be used. Also,
In the multi-chamber type, each step may be processed in a dedicated chamber. Specifically, RIE chamber, ion implantation chamber (for boron and phosphorus), CDE
It is practical to use a cluster type in which five process chambers of a chamber and an ashing chamber and two load lock chambers are connected by a common vacuum chamber.

In the above embodiment, the inverted staggered TF
Although T has been described as an example, a TFT having a coplanar structure may be used. Also, Cl2, B as etching gas
Cl3, CF4, CHF3, O2 and also SF6
And C2F6, C3F8, and the like.

[0031]

According to the method of manufacturing a semiconductor device of the present invention, the patterning and ion implantation are performed continuously without being exposed to the atmosphere, so that the manufacturing time can be greatly reduced. Further, according to the present invention, it is possible to reduce undesired stagnation of semi-finished products between processes, thereby achieving a high production yield.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a manufacturing process of a thin film transistor according to one embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a plasma processing apparatus used in a manufacturing process according to one embodiment of the present invention.

FIG. 3 is a schematic configuration diagram of a conventional thin film transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Glass substrate 27 ... a-Si: H thin film 28 ... Ohmic contact region 30 ... Drain electrode 33 ... Source electrode 39 ... Interlayer insulating film 51 ... Pixel electrode 100 ... Plasma processing apparatus 110 ... Susceptor

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Takayoshi Toi 1-9-2, Hara-cho, Fukaya-shi, Saitama F-term in Fukaya Electronics Factory, Toshiba Corporation (reference) 2H092 JA26 JA35 JA36 JA39 JA40 JA44 JA47 KA05 KA12 KA18 KB22 KB25 MA05 MA08 MA17 MA27 MA35 MA37 NA27 NA29

Claims (10)

[Claims] A step of forming a first thin film made of a non-single-crystal silicon thin film on an insulating substrate; a step of forming a second thin film on the first thin film; and etching the second thin film to form a mask pattern. Forming a ohmic contact region by implanting impurity ions into the first thin film through the mask pattern, wherein the mask pattern forming step and the ion A method of manufacturing a semiconductor device, comprising: performing an implantation step continuously without being exposed to the atmosphere. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said mask pattern forming step and said ion implantation step are performed by using different gas species in the same chamber. 3. The step of forming a mask pattern and the step of implanting an ion, wherein the step of converting the gas into plasma and the step of isolating the ions or radicals generated by the plasma conversion step are performed by a potential difference generated on the insulating substrate. 3. The step of drawing into a substrate.
The manufacturing method of the semiconductor device described in the above. 4. The method according to claim 3, wherein the gas used in the ion implantation step contains at least phosphorus. 5. The device according to claim 3, wherein the potential difference generated in the insulating substrate is generated based on a self-bias.
The manufacturing method of the semiconductor device described in the above. 6. The method according to claim 5, wherein the self-bias is adjusted based on voltage control or frequency control of a high-frequency source applied to the insulating substrate. 7. A step of forming a first thin film made of a non-single-crystal silicon thin film on an insulating substrate, a step of forming a second thin film on the first thin film, and forming a resist pattern on the second thin film. Forming, forming a mask pattern by etching the second thin film based on the resist pattern, and forming an ohmic contact region by implanting impurity ions into the first thin film through the mask pattern. A method of manufacturing a semiconductor device, comprising: after the mask pattern forming step or after the ion implantation step, removing the resist pattern; the mask pattern forming step, the ion implantation step, and A method for manufacturing a semiconductor device, wherein the removing step is performed continuously without being exposed to the atmosphere. 8. A step of forming a gate electrode on an insulating substrate, a step of depositing a gate insulating film on the gate insulating film, and forming a first thin film made of a non-single-crystal silicon thin film on the gate insulating film. Depositing a second thin film on the first thin film;
Depositing a thin film, forming a resist pattern corresponding to the gate electrode on the second thin film, etching the second thin film based on the resist pattern to form a mask pattern, Forming an ohmic contact region by implanting impurity ions into the first thin film via a pattern, wherein after the mask pattern forming step or after the ion implanting step, A method for manufacturing a semiconductor device, comprising a step of removing a resist pattern, wherein the mask pattern forming step, the ion implantation step, and the removing step are performed continuously without being exposed to the air. 9. The method according to claim 8, wherein the first thin film is made of amorphous silicon. 10. The method according to claim 8, further comprising a step of forming source and drain electrodes in contact with the ohmic contact region following the ion implantation step.