JPS61184882A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS61184882A JPS61184882A JP2502785A JP2502785A JPS61184882A JP S61184882 A JPS61184882 A JP S61184882A JP 2502785 A JP2502785 A JP 2502785A JP 2502785 A JP2502785 A JP 2502785A JP S61184882 A JPS61184882 A JP S61184882A
- Authority
- JP
- Japan
- Prior art keywords
- region
- channel region
- thin film
- impurity
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 20
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000010408 film Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000002844 melting Methods 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 12
- 238000005530 etching Methods 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、液晶表示装置等に用いる薄膜トランジスタ
（以下ＴＰＴと称す）の工程簡略化の方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for simplifying the process of thin film transistors (hereinafter referred to as TPT) used in liquid crystal display devices and the like.
この発明は、液晶表示装置等に用いるＴＰＴにおいて、
電極領域に高融点金属もしくはケイ素化金属を用いるこ
とにより、前記電極領域に不純物添加が可能となり、チ
ャンネル領域と電極領域のオーミックコンタクト管前記
チャンネル領域と１に他領域の間に別々薄膜層（例えば
不純物添加されたチャンネル層）を設けることなく得る
ことができるようにしたものである。This invention provides a TPT for use in liquid crystal display devices, etc.
By using a high melting point metal or a metal silicide for the electrode region, it is possible to dope the electrode region with impurities, and a separate thin film layer (e.g. This makes it possible to obtain the structure without providing a channel layer doped with impurities.
従来、ＴＰＴの基本構造としては第２図に示すように基
板１の上にゲート領域２を選択的に形成した後ゲート絶
縁膜５、チャンネル領域（例えばａ−８１層）４、不純
物添加された薄膜Ｎｉ６ｔ−順次形成し、フォトリソ工
程によりパターニングした後電極領域７を選択的に形成
しソース及びドレイン電極を造る方法が一般的である。Conventionally, as shown in FIG. 2, the basic structure of TPT is that after a gate region 2 is selectively formed on a substrate 1, a gate insulating film 5, a channel region (for example, the A-81 layer) 4, and impurities are added. A common method is to sequentially form Ni6t thin films, pattern them using a photolithography process, and then selectively form electrode regions 7 to form source and drain electrodes.
この際チャンネル領域と′１極領域のオーミンクコンタ
クトを得るためと、例えばＮチャンネルＴＰＴの場合ホ
ールミ流の発生を阻止しゲートオフ領域でのオフ電流の
増加を防ぐため、前記不純物添加された薄膜層６は不可
欠となる〇
〔発明が解決しようとする問題点〕
しかし、従来のＴＰＴでは前記不純物添加された薄膜６
とチャンネル領域４とのエツチング比が普通非常に近い
ため、電極領域形成と同時に前記不純物添加された薄膜
を選択除去する際その制御がむずかしく、チャンネル領
域４の膜厚は直列抵抗を軽減する等特性上から薄く形成
する方が望ましいにもかかわらず、前記不純物添加され
た薄膜層の厚みとの兼ねおいで比較的厚く形成しなけれ
ばならない制限がおった。At this time, in order to obtain an ohmink contact between the channel region and the '1-pole region, and to prevent the generation of hole current in the case of an N-channel TPT and to prevent an increase in off-current in the gate-off region, the impurity-doped thin film layer is 6 becomes indispensable〇 [Problem to be solved by the invention] However, in conventional TPT, the impurity-doped thin film 6 becomes indispensable.
Since the etching ratio between the etching layer and the channel region 4 is usually very close, it is difficult to control when selectively removing the impurity-doped thin film at the same time as forming the electrode region, and the thickness of the channel region 4 has characteristics such as reducing series resistance. Although it is desirable to form the film thinly from above, there is a restriction that the film must be formed relatively thick due to the thickness of the impurity-doped thin film layer.
上記問題点を解決するために、この発明は、前記不純物
添加された薄膜層を設ける代わシに、電極領域に、％融
点全域もしくはケイ素化金属？用いることによシ、電極
領域に直接不純物添加を可能とし電極領域形成後の適当
な熱処理によって不純物をチャンネル領域へ拡散させ、
チャンネル領域と電極領域の良好なオーミックコンタク
トを得るのが不可能となった。In order to solve the above-mentioned problems, the present invention provides that instead of providing the impurity-doped thin film layer, the electrode region has a % melting point or silicided metal layer. By using this method, impurities can be added directly to the electrode region, and the impurity can be diffused into the channel region by appropriate heat treatment after the electrode region is formed.
It became impossible to obtain good ohmic contact between the channel region and the electrode region.
陥融点金ｋＡ （例えばＯｒ、 Ｍｏ、 Ｔｉ、 Ｔａ
、 Ｗ ）もしくはケイ素化全組（例えば、Ｔｉ５Ｂ
、 ＷＳｉ、 ＭＯ８１など）にインプラやＱＶＤ法に
よって添加された不純物（例えばリン）は電極金属とは
合金を作らず、チャンネル領域と接触している部分から
の拡散も比較的低温で起こすことができる。前記不純物
添°加された電極領域からチャンネル領域へ拡散した不
純物は、その部分の比抵抗を下は電極領域とチャンネル
領域のオーミックコンタクトを与えるとともに、例えば
Ｎチャ゛ンネル型ＴＦＴの場合ホール電流の発生の抑制
の効果もあシＯＮ１０ Ｆ Ｆ比を劣化させることはな
い。Falling point gold kA (e.g. Or, Mo, Ti, Ta
, W ) or all siliconized groups (e.g. Ti5B
, WSi, MO81, etc.) by implantation or QVD method does not form an alloy with the electrode metal, and diffusion from the part in contact with the channel region can occur at a relatively low temperature. . The impurity diffused from the impurity-doped electrode region to the channel region lowers the specific resistance of that region, provides ohmic contact between the electrode region and the channel region, and also increases the hole current in the case of an N-channel TFT, for example. The effect of suppressing the occurrence does not deteriorate the ON10 FF ratio.
以下にこの発明の実施例を図面にもとづいて説明する。 Embodiments of the present invention will be described below based on the drawings.
第１図は、本発明にかかるところのＴＦ−Ｔの縦断面一
を表わす、絶縁基板１の上に選択的に形成されたゲート
領域、さらに−その上へゲート絶縁膜３、チャンネル領
域４、不純物添加された金属薄膜５を堆積させ選択除却
を行なった後適当な熱処理をほど、こして、不純物ｔチ
ャンネル領域へ拡散させオーミックコンタクトを得る、
金属薄膜５のエツチングに社チャンネル領域４とのエツ
チングレート比を充分とれる方法が用いることができる
ので無理な時間割イＷなどによるプロセスの難易度が緩
和され、また加えてチャンネル領域の膜厚などに制限が
与えられないため、特性上良い条件を任意に選択するこ
とができる。FIG. 1 shows a longitudinal cross section of a TF-T according to the present invention, which shows a gate region selectively formed on an insulating substrate 1, a gate insulating film 3, a channel region 4, and a gate region selectively formed on an insulating substrate 1. After depositing and selectively removing the impurity-doped metal thin film 5, an appropriate heat treatment is performed, and the impurity is diffused into the t-channel region to obtain an ohmic contact.
Since the metal thin film 5 can be etched using a method that provides a sufficient etching rate ratio with that of the channel region 4, the difficulty of the process due to unreasonable time schedules can be alleviated, and in addition, the process can be made more easily with respect to the film thickness of the channel region. Since no restrictions are given, conditions with good characteristics can be arbitrarily selected.
第３図は、本発明にかかるところの他の実施例における
ＴＩＦＴの縦断面図であり、絶縁基板１側にソース、ド
レイン用の不純物添加のほどこされた金属薄膜５が作り
込まれた、逆スタガ構造となっている、この様に本発明
によるところの実施例は多種のバリエーションが考えら
れ、広く応用することができる。FIG. 3 is a vertical cross-sectional view of a TIFT according to another embodiment of the present invention, in which a metal thin film 5 doped with impurities for sources and drains is formed on the insulating substrate 1 side. The staggered structure of the embodiment according to the present invention can have many variations and can be widely applied.
この発明は以上説明したように、適当な材料における電
極領域に不純物を添付しＴＰＴ形成後適当な熱処理を加
えることにより、チャンネル領域と′Ｃｔ極領域の良好
なオーミンクコンタクトが得うれ、かつプロセス上制御
の困難な箇所がなくなシ工程簡略化された形で良好な特
性のＴＰＴを得る仁とができる。As explained above, this invention makes it possible to obtain good ohmink contact between the channel region and the 'Ct electrode region by adding impurities to the electrode region of a suitable material and applying appropriate heat treatment after forming the TPT. Since there are no difficult-to-control parts, it is possible to obtain TPT with good characteristics in a simplified process.
第１図は、この発明におけるＴＰＴの縦断面図、第２図
は、従来の構造におけるＴＰＴの縦断面図であり、第３
図は、この）へ明における１”ＦＴの他の実施例の綾吟
ｆ面図である。
１・・・基板 ２・・・ゲート領域３・・・
ゲート絶縁膜 ４・・・チャンネル領域５・・・不純
物添加された金絹薄膜
６・・・不純物添加された薄膜層
７・・・１ｄ鞄領域
以上FIG. 1 is a vertical cross-sectional view of the TPT in the present invention, FIG. 2 is a vertical cross-sectional view of the TPT in a conventional structure, and FIG.
The figure is a cross-sectional view of another embodiment of the 1" FT in this). 1...Substrate 2...Gate region 3...
Gate insulating film 4... Channel region 5... Impurity-doped gold silk thin film 6... Impurity-doped thin film layer 7... 1d bag region or more
Claims (3)
膜、チャンネル領域、電極領域を有する薄膜素子におい
て、該電極領域に不純物が添加されていることを特徴と
する薄膜トランジスタ。(1) A thin film transistor comprising a gate region, a gate insulating film, a channel region, and an electrode region provided on an insulating substrate, the electrode region being doped with an impurity.
はそのケイ素化金属であることを特徴とする特許請求の
範囲第１項記載の薄膜トランジスタ。(2) The thin film transistor according to claim 1, wherein the electrode region is made of an impurity-doped high-melting point metal or a silicided metal thereof.
薄膜であることを特徴とする特許請求の範囲第２項記載
の薄膜トランジスタ。(3) The thin film transistor according to claim 2, wherein the channel region is a hydrogenated amorphous silicon thin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2502785A JPS61184882A (en) | 1985-02-12 | 1985-02-12 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2502785A JPS61184882A (en) | 1985-02-12 | 1985-02-12 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61184882A true JPS61184882A (en) | 1986-08-18 |
Family
ID=12154427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2502785A Pending JPS61184882A (en) | 1985-02-12 | 1985-02-12 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61184882A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62115868A (en) * | 1985-11-15 | 1987-05-27 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH02188928A (en) * | 1989-01-17 | 1990-07-25 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPH03297172A (en) * | 1990-04-17 | 1991-12-27 | Nec Corp | Thin film transistor and manufacture thereof |
| KR20010094962A (en) * | 2000-03-31 | 2001-11-03 | 포만 제프리 엘 | Method of forming ohmic contacts using a self doping layer for thin-film transistors |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59181064A (en) * | 1983-03-31 | 1984-10-15 | Toshiba Corp | Semiconductor device |
-
1985
- 1985-02-12 JP JP2502785A patent/JPS61184882A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59181064A (en) * | 1983-03-31 | 1984-10-15 | Toshiba Corp | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62115868A (en) * | 1985-11-15 | 1987-05-27 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH02188928A (en) * | 1989-01-17 | 1990-07-25 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPH03297172A (en) * | 1990-04-17 | 1991-12-27 | Nec Corp | Thin film transistor and manufacture thereof |
| KR20010094962A (en) * | 2000-03-31 | 2001-11-03 | 포만 제프리 엘 | Method of forming ohmic contacts using a self doping layer for thin-film transistors |
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