JPS6213076A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a low resistance silicide film by reducing an impurity density in a silicified polycrystalline silicon film, thereby completing a silicifying reaction at a low temperature in a short time. CONSTITUTION:Insulating films 2a, 2b and a gate insulating film 3 are selectively formed on a silicon substrate 1, polycrystalline silicon films 5a, 5b are formed on the entire surface, and patterned. An oxide film 6 is formed, oxide films 6a, 6b are formed by anisotropically etching on the sides of the film 3 and a gate electrode 5'. A metal film 8 is formed by vacuum depositing, heat treated to silicify the film 8 on the substrate 1 and the film 5b, thereby forming silicide films 9a-9c. To remove unreacted metals 8a-8d and to form lower resistance silicide films, they are heat treated at relatively high temperature. To form a junction, As, P, B, or Sb impurity is ion implanted, and heat treated to form impurity layers 7a, 7b.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing such a semiconductor device.

[Conventional technology]

Figure 2 shows the 1982 IEDM (Inter
national Electron Device M
FIG. 3 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device represented by Xi@. Here N type MO8)
This is an example of a transistor.

In FIG. 2(a), 1 is a silicon substrate, 2 a +
2b is a thick insulating film for element isolation selectively formed on the main surface of the silicon substrate 1 by a thermal oxidation method, etc.; 3 is a relatively thin gate insulating film for a MOS transistor; 4 is a MO transistor.
S) Impurity layer 5 for controlling the threshold voltage of the transistor is a polycrystalline silicon film formed by CVD method etc.
OS) Thermal diffusion method is used to stabilize the threshold voltage of transistors.

Impurities such as phosphorus and hisso are doped into the polycrystalline silicon film 5 by ion implantation or the like to suppress fluctuations in the work function of the polycrystalline silicon. FIG. 2(b) shows a state in which the polycrystalline silicon film 5 has been selectively etched by photolithography and etching.

5' indicates a gate electrode. Furthermore, in this example, the gate insulating film 3 underneath is also selectively removed. Currently, generally V
An anisotropic dry etching method is often used for etching gate electrodes, wiring, and polycrystalline silicon films in LSIs. In FIG. 2(c), 6 is an oxide film formed by CVD method or the like. FIG. 2(d) shows a gate electrode 5' with a steep step formed by anisotropic etching.
The oxide films 6a and 6b that remain on the side surfaces of the gate insulating film 3 are commonly called one frame "one side wall pad or one side spacer". ), then hiso to form the sauce tonying.

Impurity layers 7a and 7b of phosphorus, horn, etc. (also referred to as source implantation) are formed by ion implantation or the like, and then the implanted impurities are activated by heat treatment and damage caused by the implantation to the silicon substrate 1 is removed. Figure 2 (,)
is by sputtering method, CVD method, vacuum evaporation method, etc.
For example, a state in which a metal film 8 such as titanium is formed is shown. Second
9a in figure (f).

9b and 9e are silicide films formed by a silicidation reaction between the metal film 8 and the underlying silicon, and 8a, 8b, 8c, and 8d are unreacted metal films. FIG. 2(g) shows a state in which unreacted metal films 8a to 8d have been removed.

Next, the operation will be explained. The oxide films 6a and 6b, which are called "picture frames", are formed on the side surfaces of the gate insulating film 3 when silicide is formed by heat treatment after the metal film 8 is formed, and the oxide films 6a and 6b are connected to the gate electrode 5'. This is to prevent electrical short circuit between the source and the tunnel layer. When heat treatment for silicidation is first performed at a relatively low temperature with these oxide films 6a and 6b formed,
The metal film 8 in contact with the silicon undergoes a silicidation reaction with the silicon, and an oxide film 6a is formed.

6b and the metal films 88 to 8d on the insulating films 2a and 2b remain unreacted. Therefore, for example, when the metal film 8 is made of titanium, the unreacted metal films 88 to 8d can be selectively removed by using a mixed solution of NH, OH and H2O. At this time, the silicide films 9b and 9a+9C remain as they are on the gate electrode 5' and on the impurity layers 7a to Tb.
Since the heat treatment at the time of formation is performed at a relatively low temperature, the resistance of the silicide films 98 to 9c has not yet decreased to the saturation value. The resistance of the silicide films 9a to 9c is reduced. By the method described above, silicide films 9a to 9c are formed on the gate electrode 5' and the impurity layers of the source/drains 7m and 7b in a self-aligned manner.

[Problem that the invention seeks to solve]

Conventional semiconductor devices are manufactured using the process described above, so if the impurity concentration in the silicon to be silicided is high, the silicide reaction rate will be reduced. Even if the silicide reaction is completed under the conditions, the silicide reaction is not completed on the one with higher concentration, so the unreacted metal film is removed by selective etching, and the thickness of the resulting silicide film is that of impurities. It will be thinner and have a higher resistance value than the one with lower concentration. Such a phenomenon can be solved by increasing the heat treatment temperature and lengthening the heat treatment time for silicidation.

However, in the MO8 field effect transistor, the gate electrode 5' made of polycrystalline silicon and the source electrode 5' are made of polycrystalline silicon.
When simultaneously siliciding the surface of the silicon substrate 1 that will become the tunnel layer, Mo, W, and Ta are used as the silicide.
* If the heat treatment temperature and time are high and long when attempting to form a silicide of a high melting point metal, the oxide films 6a and 6b provided to prevent an electrical short between the source/ton-in layer and the gate electrode 5' may be damaged. Since the metal film on the surface is also silicided and is not removed in the subsequent selective etching process, a short circuit occurs between the source tunnels 7a, 7b and the gate electrode 5', and self-aligned silicide cannot be achieved.

This is because the reaction process of high melting point metal silicide is rate-determined by the diffusion of silicon atoms.

Furthermore, in the conventional method, it is difficult to simultaneously form a low-resistance silicide layer on the polycrystalline silicon film 5 and the silicon substrate 1, which will become the source/in layer, in a self-aligned manner. Ta. In particular, in actual devices, the resistance of the gate electrode wiring film has a large effect on the device operating speed fK, so
If the top of the polycrystalline silicon film 5 is not sufficiently silicided, it will cause problems in terms of device performance.

In addition, in order to solve the above problem, when performing silicidation, do not dope impurities into the polycrystalline silicon film 5 that will become the gate electrode 5' or near the surface of the silicon substrate 1 that will become the source/V-in layer. Even if a method of forming a source-don-in impurity layer after silicidation and implanting impurities to stabilize the work function of the polycrystalline silicon film 5 that will become the gate electrode 5' is used, self-aligned silicide cannot be achieved. In an element that requires a structure, the junction depth between the source electrodes 7a and 7b and the silicon substrate 1 must be shallow, so the implantation energy and amount are also limited. In many cases, it is difficult to dope sufficient impurities to stabilize the work function of the polycrystalline silicon film 5 in contact with the gate insulating film 3.

This invention was made in order to solve the above problems, and it is necessary to stabilize the work function of sufficiently low polycrystalline silicon in the gate electrode wiring part and the surface part of the silicon substrate which will become the source/V-in layer. An object of the present invention is to obtain a semiconductor device having better threshold voltage characteristics.

[Means for solving problems]

When speeding up hydrogenation, silicidation is performed in a state where the concentration of impurities (As, P, B, etc.) near the surface that contribute to the silicide reaction is reduced.

[Effect]

By lowering the concentration, the silicide reaction can be completed at a lower temperature and in a shorter time than when the concentration is high, and a low-resistance silicide film can be obtained.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, 5a is a polycrystalline silicon film formed by a CVD method or the like.

After directly forming a film containing relatively large amounts of As, Sb, B, etc., or forming a polycrystalline silicon film containing no impurities, P, As,
By introducing Sb, B, etc. into the film, a film with high impurity concentration is formed as a result.

5b is a polycrystalline silicon film that does not contain impurities As, P, and B, or even if it does, its concentration is suppressed to 1/2 or less of 5IL. Other symbols are the same as those shown in FIG.

The thickness of the polycrystalline silicon film 5b depends on the thickness of the metal film 8 to be formed later, but since the first heat treatment is performed at a relatively low temperature when forming self-aligned silicide, Since the thickness of silicon that contributes to the silicidation reaction is approximately equal to the thickness of the metal film 8, the polycrystalline silicon film 5b
It is desirable that the thickness of the metal film 8 be greater than or equal to the thickness of the metal film 8.

Next, the manufacturing method will be explained. First, as shown in FIG. 1(a), an insulating film 2 is selectively formed on the main surface of a silicon substrate 1.
A, 2b and gate insulating film 3 are formed, and polycrystalline silicon films 5a and 5b are formed on the entire surface.

Thereafter, as shown in FIG. 1(b), a polycrystalline silicon film 5b is formed.

5a and the gate insulating film 3 are patterned. Then the first
As shown in Figure (C), an oxide film 6 is formed by CVD method etc.
Thereafter, as shown in FIG. 1(d), oxide films 6m and 6b called "6 frame" are formed on both sides of the gate insulating film 3 and the gate electrode 5' using an anisotropic etching process. As shown in FIG. 1(e), the metal film B is formed by vacuum evaporation or the like, and by heat treatment, the metal film B is formed on the silicon substrate 1 and the polycrystalline silicon film 5b as shown in FIG. 1(f).
are silicided to become silicide films 9a, 9c, and 9b. After that, as shown in FIG. 1(g), unreacted metals 8a to
After selectively removing 8d, heat treatment is performed at a relatively high temperature in order to complete the silicide reaction and form a silicide film with lower resistance as shown in FIG. 1(h). And Figure 1 (
As, P, B, Sb to form a bond as in i)
Impurity layers 7a and 7b are formed by ion-implanting impurities such as, and then performing heat treatment.

Note that the above ion implantation may be performed after heat treatment for performing the first silicide reaction or after selectively removing unreacted metal.

In the above manufacturing method of the present invention, the polycrystalline silicon J11 is
Since there is no heat treatment at a high enough temperature to change the impurity concentration distribution of 5a and 5b, the metal film 8 can react with silicon having a low impurity concentration, so that silicidation can be performed in a short time. Further, in this embodiment, since impurity implantation for forming a source tunnel is not performed on the surface of the silicon substrate 1, a silicide film having a similar thickness can be formed on both the gate electrode 5' and the surface of the silicon substrate 10. In this way, by making both the silicidation reaction rates fast and equal, silicide films 98 to 9c having low resistance and excellent self-alignment can be obtained.

Further, even if the impurities in the polycrystalline silicon film 5a are diffused in the subsequent heat treatment, if the original concentration is high, there will be no change in the work function, and the threshold voltage will also be stabilized.

Furthermore, in the above embodiment, the polycrystalline silicon films 5a and 5b having different impurity concentrations on the upper and lower sides were formed, but after forming the polycrystalline silicon films, a high energy voltage condition was applied so that the impurity concentration distribution peak was at a deep position. Impurity ions may also be implanted.

Furthermore, in the above embodiment, Man is used as the metal silicide film.
wl T 81 T etc. were used, but in addition, V,
Nb.

Hf, Cr, Ni, Co, Zr, Pt, P
d, Rh, Ir, etc. may also be used.

〔Effect of the invention〕

As explained above, when a metal silicide film is formed by a direct reaction between a polycrystalline silicon film and a metal film in contact with the polycrystalline silicon film, the impurity concentration distribution in the polycrystalline silicon film is reduced to speed up silicidation. Since the concentration is low, the silicidation reaction rate becomes faster, and there is an advantage that a semiconductor device having a low-resistance silicide film can be obtained.

[Brief explanation of drawings]

FIGS. 1(a) to (i) are cross-sectional views of a semiconductor device showing the main steps of an embodiment of the present invention, and FIGS. 2(a) to Q) show the main steps of a conventional method for manufacturing a semiconductor device. FIG. In the figure, 1 is a silicon substrate, 2a and 2b are thick insulating films, 3 is a gate insulating film, 4 is an impurity layer, 5a and 5b are polycrystalline silicon films, 5' is a gate electrode, 6.6a+6
b is an oxide film, 7a and 7b are source/V-in, 8 is a metal film, 8a to 8d are unreacted metal films, and 9a, 9b, and 9c are silicide films. Note that the same symbols in each figure indicate the same or equivalent parts. Agent Masuo Ookimi (2 others) Procedural amendment band (voluntary) l, Indication of case Patent application No. 153426/1988 2,
Title of the invention Semiconductor device manufacturing method 3, relationship with the amended case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4; Agent address: 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo
, ? In Column 6 of Detailed Description of the Invention in the correct subject specification, "after silicide" in page 6, line 18 of the specification of contents of the amendment, [
It is corrected as "after being silicided". that's all

Claims (4)

[Claims] (1) When forming a metal silicide film by direct reaction between a polycrystalline silicon film and a metal film in contact with it,
A method for manufacturing a semiconductor device, characterized in that the impurity concentration distribution in the polycrystalline silicon film is made low when silicidation is accelerated. (2) The method for manufacturing a semiconductor device according to claim (1), wherein the impurity concentration distribution is such that the impurity concentration on the reaction side of the polycrystalline silicon film is lower than the impurity concentration on the non-reaction side. (3) The method for manufacturing a semiconductor device according to claim (1), wherein one of phosphorus, hiso, antimony, and boron is used as the impurity. (4) As the metal silicide film, any one of molybdenum, tungsten, tantalum, titanium, vanadium, niobium, hafnium, chromium, nickel, cobalt, zirconium, platinum, palladium, rubidium, and iridium
A method of manufacturing a semiconductor device according to claim (1), characterized in that a method of manufacturing a semiconductor device is used.