JPH03297172A - Thin film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To simplify a manufacturing process by employing two layers of high melting point metal silicide and of doped polycrystalline silicon for a source and a drain, and forming on the former a thin film semiconductor active layer, a gate insulating film covering a semiconductor layer, and a metal layer. CONSTITUTION:A high melting point silicide layer 2 that forms a source and a drain is formed and patterned using one including therein many impurity phosphorus atoms. Then, a non-doped polycrystalline silicon film is formed as an active layer into the form of an island, and involved impurity in the layer 2 is diffused outwardly during the film formation and in a successive heat treatment to turn only the regions on the source and the drain into a doped polycrystalline silicon 4. After the formation of a gate insulating film 5, a contact hole penetrating the film 5 and the silicon 4 is formed by etching and thereafter a metal layer 7 is formed to form an electrode pattern. Hereby, a simplified process is ensured and good characteristics are yielded.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to thin film transistors.

[Conventional technology]

In recent years, research into the technology of fabricating thin-film active devices on glass substrates has become active, with the aim of applying it to various applications such as large-area transmission type liquid crystal displays and contact type image sensors. Among these, polycrystalline silicon thin film transistors are attracting attention as the most promising device for fabricating fully thin film devices that also integrate peripheral drive circuits. The structure of such thin film transistors can be broadly divided into a brazed structure and a staggered #4 structure. The forward staggered structure shown in FIG. 3 has the advantage that it can be manufactured through a simpler process than the Brainer structure. A conventional method for manufacturing a transistor with a staggered structure is shown in FIG. A doped polycrystalline silicon layer 6 is formed on a glass substrate 1 and patterned to form sources and drains (FIG. 4(a)). A film of non-doped polycrystalline silicon 3 which will become an active layer is formed on top of this to form an island pattern (FIG. 4(b)). Further, a gate insulating film 5 is formed, and contact holes are formed by etching to penetrate the gate insulating film and non-doped polycrystalline silicon and reach the source/drain (FIG. 4(C)). Thereafter, a metal layer 7 for electrodes is formed and an electrode pattern is formed to complete a staggered thin film transistor (FIG. 4(d)). In this way, there is no need for doping processes such as ion implantation,
Moreover, there are many advantages if two-layer wiring can be formed with low-resistance polycrystalline silicon (doped polycrystalline silicon) 6 for sources and drains and metal layer 7 for electrodes.

[Problem to be solved by the invention]

However, the resistance value obtained with polycrystalline silicon is approximately 100 Ω/hole in terms of sheet resistance, which is considerably higher than that of metal. For this reason, this is not a problem when the degree of integration is low and the length of polycrystalline silicon wiring is short, but as the degree of integration is high and the length of polycrystalline silicon wiring becomes long, wiring resistance becomes a problem, and polycrystalline silicon is not sufficient as a wiring material. This includes the problem that there is no Ordinary metal layers cannot be used as source and drain electrodes because they cannot withstand high-temperature processes. Creating a new metal wiring layer requires an increase in the number of steps, which has the major disadvantage of halving the advantage of the staggered structure, which can be manufactured through a simple process.

[Means to solve the problem]

The gist of this invention is, firstly, a low resistance source/drain provided on an insulating substrate, a thin film semiconductor active layer formed on top of the source/drain, and a gate insulating film formed to cover the semiconductor layer. , a sequential stacker type thin film transistor composed of metal layers, characterized in that two layers of high melting point metal silicide and doped polycrystalline silicon are used as the source and drain.

The second step is to form a high melting point metal silicide film containing impurities on an insulating substrate and pattern it to form sources and drains, and to form an island by forming a non-doped polycrystalline silicon film on the silicide layer. a step of heat-treating this two-layer film to form a doped polycrystalline silicon layer on the source/drain using silicide as a diffusion source;
This method of manufacturing a thin film transistor includes at least the steps of forming a gate insulating film to cover the polycrystalline silicon film and forming a contact hole, and forming a metal layer.

[Effect]

Refractory metal silicides have recently attracted attention as interconnect materials in VLSI technology. It is a material with lower resistance than polycrystalline silicon, and unlike metals, it is stable even at high temperatures, so it can withstand processes such as CVD. If this silicide is used for the lower electrodes, ie, the source and drain, of a staggered polycrystalline silicon thin film transistor, it is effective because it has low resistance and is stable at high temperatures. Since it has a resistivity about an order of magnitude lower than polycrystalline silicon, it is also suitable as a material for wiring electrodes. Conventional polycrystalline silicon has a high resistivity of about 100Ω/unit, which causes problems when the degree of integration increases, but when silicide is used, the resistance is lowered by more than an order of magnitude, making it suitable for devices with a high degree of integration. can also be applied. In addition, high-precision patterning is possible using fluorocarbon-based dry etching, and the selection ratio between polycrystalline silicon and silicon oxide film is high.

As a result, manufacturing is easier than with conventional structures, such as by allowing a larger process margin when forming contact holes and the like.

Recently, attempts to use this silicide as a diffusion source have also been reported. This is a method in which silicide containing impurities such as phosphorus is created and doping is performed using this as a diffusion source. This impurity does not enter the silicon sites in the silicide, so it does not affect the electrical characteristics of the silicide. However, at high temperatures, these impurities tend to diffuse outward, so if a silicon film is formed on silicide and exposed to high temperatures, a doped polycrystalline silicon film can be automatically formed on the silicide. If this is applied to the device manufacturing process, staggered polycrystalline silicon can be formed in a simple process. In other words, by forming the source/drain with silicide containing this impurity, and then forming a film of non-doped polycrystalline silicon and subjecting it to high-temperature heat treatment, doped polycrystalline silicon is formed in a self-aligned manner only near the source/drain, resulting in good ohmic properties. A bond is obtained. This allows the doping process to be omitted.

〔Example〕

The invention will now be described in detail with reference to embodiments shown in the accompanying drawings.

FIGS. 1 and 2 are structural diagrams and process diagrams showing embodiments of the present invention. As shown in FIG. 1, silicide was used for the source and drain. Silicide has a low sheet resistance of less than 10 Ω/hole, so it can be used for wiring. Therefore, as shown in FIG. 1, wiring can be established between the source/drain silicide layer 2 and the gate electrode layer. Third
The conventional two-layer wiring shown in the figure is no longer necessary, making it possible to significantly shorten the process. In addition, the etching rate of this silicide layer using fluorocarbon gas, etc.
Etching is about 10 degrees slower than silicon, oxide films, etc., making it easier to etch contact holes and the like, resulting in an expanded process margin. As this silicide layer, Mo
Six.

Ta5iX, TiSix, WSix, etc. were suitable.

FIGS. 2(a) to 2(e) are manufacturing process diagrams showing one embodiment of the present invention. As shown in FIG. 2(a), a high melting point metal silicide layer 2 forming sources and drains was formed and patterned. This silicide layer can be formed by sputtering or C
The film was formed by a VD method and contained a large amount of phosphorus atoms, which are impurities, inside. Next, a non-doped polycrystalline silicon film, which will become an active layer, was deposited to form an island (Fig. 2 (b)).
The impurity contained in the silicide layer was diffused outward by the C heat treatment, and only the region above the source/drain became doped polycrystalline silicon 4 (FIG. 2(C)). Gate insulating film 5
A contact hole was formed through the gate insulating film and doped polycrystalline silicon by etching.
Figure 2(d)). Thereafter, a metal layer 7 was formed and an electrode pattern was formed (FIG. 2(e)).

This method allows transistors to be manufactured in a simple process,
Good characteristics could be obtained. As a result, as shown in FIG. 5, conventional doping processes such as forming a doped polycrystalline silicon layer were required, but with the manufacturing process of the present invention, transistors can be manufactured with a simple process without the need for doping processes. Became.

〔Effect of the invention〕

As described above in detail, polycrystalline silicon thin film transistors and functional devices using the same can be manufactured with good reproducibility through simple steps using the thin film transistor structure and manufacturing method according to the present invention.

[Brief explanation of drawings]

FIG. 1 is a structural diagram showing an embodiment of the present invention, FIG. 2 is a schematic manufacturing process diagram showing an embodiment of the present invention, and FIGS. 3 and 4 show the structure and manufacturing method of a conventional polycrystalline thin film transistor. The figure shown in FIG. 5 is a diagram showing a conventional manufacturing method for obtaining the structure of the present invention. DESCRIPTION OF SYMBOLS 1...Glass substrate, 2...High melting point metal silicide layer (source/drain), 3...Non-doped polycrystalline silicon (active layer) 4...Doped polycrystalline silicon, 5
...gate insulating film, 6...source/drain, 7.
...Metal layer.

Claims (1)

[Claims] 1. A low-resistance source/drain provided on an insulating substrate, a thin film semiconductor active layer formed on the top thereof, a gate insulating film formed to cover the semiconductor layer, and a metal layer. 1. A staggered thin film transistor constructed of a staggered thin film transistor, characterized in that two layers of high melting point metal silicide and doped polycrystalline silicon are used as the source and drain. 2. A step of forming a high melting point metal silicide film containing impurities on an insulating substrate and patterning it to form a source/drain, and a step of forming a non-doped polycrystalline silicon film on the silicide layer to form an island. Then, a process of heat treating this two-layer film to form a doped polycrystalline silicon layer on the source/drain using silicide as a diffusion source, forming a gate insulating film to cover the polycrystalline silicon layer, and forming a contact hole. 1. A method for manufacturing a thin film transistor, comprising at least a step of forming a metal layer and a step of forming a metal layer.