JPH0344425B2 - - Google Patents

Info

Publication number
JPH0344425B2
JPH0344425B2 JP60117112A JP11711285A JPH0344425B2 JP H0344425 B2 JPH0344425 B2 JP H0344425B2 JP 60117112 A JP60117112 A JP 60117112A JP 11711285 A JP11711285 A JP 11711285A JP H0344425 B2 JPH0344425 B2 JP H0344425B2
Authority
JP
Japan
Prior art keywords
diffusion layer
drain
well
type
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60117112A
Other languages
English (en)
Other versions
JPS61276252A (ja
Inventor
Junichi Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP60117112A priority Critical patent/JPS61276252A/ja
Publication of JPS61276252A publication Critical patent/JPS61276252A/ja
Publication of JPH0344425B2 publication Critical patent/JPH0344425B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0927—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising a P-well only in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は相補型MOS半導体装置（以下CMOS
トランジスタという）に関し、特に高耐圧を有す
るＮチヤネルMOSトランジスタの構造に関する。
〔従来の技術〕
従来、CMOSトランジスタを構成するＮチヤ
ネルMOSトランジスタは第２図に示すように、
Ｎ型基板１０にＰウエル９が形成され、Ｐウエル
９内に深さ約0.5〜1.0μのソース拡散層１，ドレ
イン拡散層２，チヤネルストツパー７が配置さ
れ、そして厚さ約300〜800Åのゲート酸化膜１２
上に厚さ4000〜7000Åのポリシリコンのゲート電
極３が形成され、絶縁膜として厚さ約1μのフイ
ールド酸化膜８及びゲート電極を覆う厚さ約200
〜1000Åの酸化膜１１が形成された構造となつて
いる。
〔発明が解決しようとする問題点〕
ＮチヤネルMOSトランジスタは、CMOSトラ
ンジスタ回路内において、Ｐウエル９及びソース
拡散層１に対しドレイン拡散層２に＋の電圧が印
加され、ゲート電極３の電位を変化させることに
より、動作させることができる。
上記従来構造のＮチヤネルMOSトランジスタ
を有するCMOS ICは、5V以下の電源ラインで使
用されるのが一般的であるが、最近20V程度の耐
圧を有するCMOS ICが要求されてきている。し
かしながらこの様な高耐圧のCMOS ICは下記の
理由により従来構造での実現は難かしい。
(1) ドレイン耐圧を上げるためドレイン接合を深
くすると、ドレイン逆バイアスのとき空乏層が
ソース側にまで伸び、耐圧が低下する。そのた
めチヤネル長を大きくとる必要があり、微細化
ができない欠点がある。
(2) ドレイン逆バイアスの場合、ドレインのゲー
ト酸化膜直下で電界が集中し、ホールがＰウエ
ル内に注入される。この注入電流が多くなると
ソース，Ｐウエルドレイン間でnpnバイポーラ
トランジスタの動作が生じ、大電流により素子
の破壊が起る欠点がある。
本発明の目的は上記欠点を除去し、高耐圧の
CMOS半導体装置を提供することにある。
〔問題点を解決するための手段〕
本発明のCMOS半導体装置はＰウエル領域に
形成されたＮ型のソース拡散層及びドレイン拡散
層と、このソース拡散層を囲んでＰウエル領域内
に形成されたP+型拡散層と、ドレイン拡散層の
少なくともチヤネル領域側に形成されたN-型拡
散層とを含んでなるＮチヤンネルMOSトランジ
スタを有するものである。
〔実施例〕
次に、本発明の実施例について図面を参照して
説明する。
第１図は本発明の一実施例の断面図である。
第１図において、Ｎ型基板１０上には表面濃度
が５×1015個／cm3程度のＰウエル６が形成されて
おり、このＰウエル６内にはＮ型のソース拡散層
１及びドレイン拡散層２が形成されている。そし
てこのソース拡散層１はＰウエル６内より高濃度
のP+型拡散層４（表面濃度〜１×1016個／cm3）で
囲まれており、一方ドレイン拡散層２は低濃度の
N-型拡散層５（表面濃度〜１×1017個／cm3）と
ゲート側で接続されている。
尚、ソース拡散層１及びドレイン拡散層２の深
さは0.3〜1.0μ、P+型拡散層４の深さは1.0〜3.0μ、
N-型拡散層５の深さは1.0〜2.0μである。また、
ソース拡散層１とドレイン拡散層２の間のチヤネ
ル長は３〜5μであり、チヤネル部において、ソ
ース拡散層１のゲート側端部からP+型拡散層４
のゲート下縁端までの距離は1.0〜3.0μ、ドレイ
ン拡散層２のゲート側端部からN-型拡散層５の
ゲート下縁端までの距離は1.0〜3.0μに構成され
ている。
このように構成された本発明の実施例によれば
次のような改良点がある。
(1) N-型拡散層５によりドレイン耐圧を上げる
ことができる。
(2) 従来構造ではドレイン拡散層２とＰウエル９
による接合が逆バイアスされると空乏層は殆ん
どＰウエル９側に伸るが、本発明による構造に
おいては、N-型拡散層５側にも空乏層が伸び
るためチヤネル長を長くせず高耐圧化が可能と
なる。
(3) 更にソース側のP+型拡散層４が、上記空乏
層のストツパーとして働く。
(4) ドレイン側からホールがＰウエル内に注入さ
れた場合、P+型拡散層４によりホールを吸収
することができる。
〔発明の効果〕
以上説明した様に、本発明によればＮチヤネル
MOSトランジスタの高耐圧化が可能となり、
20V程度の耐圧を有するCMOS半導体装置が得ら
れるのでその効果は大きい。
【図面の簡単な説明】
第１図は本発明の一実施例の断面図、第２図は
従来のCMOS半導体装置の断面図である。 １……ソース拡散層、２……ドレイン拡散層、
３……ゲート電極、４……P+型拡散層、５……
N-型拡散層、６……Ｐウエル、７……チヤネル
ストツパー、８……フイールド酸化膜、９……Ｐ
ウエル、１０……Ｎ型基板、１１……ゲート絶縁
膜、１２……ゲート酸化膜。

Claims (1)

    【特許請求の範囲】
  1. １ Ｐウエル領域に形成されたＮ型のソース拡散
    層及びドレイン拡散層と、該ソース拡散層を囲ん
    でＰウエル領域内に形成されたP+型拡散層と、
    前記ドレイン拡散層の少くともチヤネル領域側に
    形成されたN-型拡散層とを含んでなるＮチヤン
    ネルMOSトランジスタを有することを特徴とす
    るCMOS半導体装置。
JP60117112A 1985-05-30 1985-05-30 Ｃｍｏｓ半導体装置 Granted JPS61276252A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60117112A JPS61276252A (ja) 1985-05-30 1985-05-30 Ｃｍｏｓ半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60117112A JPS61276252A (ja) 1985-05-30 1985-05-30 Ｃｍｏｓ半導体装置

Publications (2)

Publication Number Publication Date
JPS61276252A JPS61276252A (ja) 1986-12-06
JPH0344425B2 true JPH0344425B2 (ja) 1991-07-05

Family

ID=14703712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60117112A Granted JPS61276252A (ja) 1985-05-30 1985-05-30 Ｃｍｏｓ半導体装置

Country Status (1)

Country Link
JP (1) JPS61276252A (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02307272A (ja) * 1989-05-22 1990-12-20 Matsushita Electron Corp 半導体装置
US5744372A (en) 1995-04-12 1998-04-28 National Semiconductor Corporation Fabrication of complementary field-effect transistors each having multi-part channel
US6127700A (en) * 1995-09-12 2000-10-03 National Semiconductor Corporation Field-effect transistor having local threshold-adjust doping

Also Published As

Publication number Publication date
JPS61276252A (ja) 1986-12-06

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