JPH0333068Y2 - - Google Patents

Info

Publication number
JPH0333068Y2
JPH0333068Y2 JP1985146750U JP14675085U JPH0333068Y2 JP H0333068 Y2 JPH0333068 Y2 JP H0333068Y2 JP 1985146750 U JP1985146750 U JP 1985146750U JP 14675085 U JP14675085 U JP 14675085U JP H0333068 Y2 JPH0333068 Y2 JP H0333068Y2
Authority
JP
Japan
Prior art keywords
heat dissipation
resin
stud
packages
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1985146750U
Other languages
English (en)
Japanese (ja)
Other versions
JPS6255354U (en:Method
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985146750U priority Critical patent/JPH0333068Y2/ja
Publication of JPS6255354U publication Critical patent/JPS6255354U/ja
Application granted granted Critical
Publication of JPH0333068Y2 publication Critical patent/JPH0333068Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
JP1985146750U 1985-09-26 1985-09-26 Expired JPH0333068Y2 (en:Method)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985146750U JPH0333068Y2 (en:Method) 1985-09-26 1985-09-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985146750U JPH0333068Y2 (en:Method) 1985-09-26 1985-09-26

Publications (2)

Publication Number Publication Date
JPS6255354U JPS6255354U (en:Method) 1987-04-06
JPH0333068Y2 true JPH0333068Y2 (en:Method) 1991-07-12

Family

ID=31059500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985146750U Expired JPH0333068Y2 (en:Method) 1985-09-26 1985-09-26

Country Status (1)

Country Link
JP (1) JPH0333068Y2 (en:Method)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7772036B2 (en) * 2006-04-06 2010-08-10 Freescale Semiconductor, Inc. Lead frame based, over-molded semiconductor package with integrated through hole technology (THT) heat spreader pin(s) and associated method of manufacturing

Also Published As

Publication number Publication date
JPS6255354U (en:Method) 1987-04-06

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