JPH0332214B2 - - Google Patents
Info
- Publication number
- JPH0332214B2 JPH0332214B2 JP61308923A JP30892386A JPH0332214B2 JP H0332214 B2 JPH0332214 B2 JP H0332214B2 JP 61308923 A JP61308923 A JP 61308923A JP 30892386 A JP30892386 A JP 30892386A JP H0332214 B2 JPH0332214 B2 JP H0332214B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- protective film
- insulating protective
- stress
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30892386A JPS63164344A (ja) | 1986-12-26 | 1986-12-26 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30892386A JPS63164344A (ja) | 1986-12-26 | 1986-12-26 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63164344A JPS63164344A (ja) | 1988-07-07 |
JPH0332214B2 true JPH0332214B2 (enrdf_load_stackoverflow) | 1991-05-10 |
Family
ID=17986906
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP30892386A Granted JPS63164344A (ja) | 1986-12-26 | 1986-12-26 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63164344A (enrdf_load_stackoverflow) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5314845A (en) * | 1989-09-28 | 1994-05-24 | Applied Materials, Inc. | Two step process for forming void-free oxide layer over stepped surface of semiconductor wafer |
JPH03133131A (ja) * | 1989-10-18 | 1991-06-06 | Mitsubishi Electric Corp | 半導体装置 |
JP2822656B2 (ja) * | 1990-10-17 | 1998-11-11 | 株式会社デンソー | 半導体装置およびその製造方法 |
US7576003B2 (en) * | 2006-11-29 | 2009-08-18 | International Business Machines Corporation | Dual liner capping layer interconnect structure and method |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57149752A (en) * | 1981-03-11 | 1982-09-16 | Mitsubishi Electric Corp | Structure of multilayer wiring |
-
1986
- 1986-12-26 JP JP30892386A patent/JPS63164344A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS63164344A (ja) | 1988-07-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |