JPH03284866A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPH03284866A JPH03284866A JP2086136A JP8613690A JPH03284866A JP H03284866 A JPH03284866 A JP H03284866A JP 2086136 A JP2086136 A JP 2086136A JP 8613690 A JP8613690 A JP 8613690A JP H03284866 A JPH03284866 A JP H03284866A
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- resin
- lead frame
- semiconductor chip
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims abstract description 34
- 229920005989 resin Polymers 0.000 claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 238000000465 moulding Methods 0.000 abstract description 2
- 230000000630 rising effect Effects 0.000 abstract 3
- 238000010586 diagram Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910000906 Bronze Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
表面に搭載した半導体チップとともに樹脂により被覆さ
れるダイバンドを有するリードフレームに関し、
樹脂との間の熱抵抗を小さくすることのできるリードフ
レームの提供を目的とし、
〔産業上の利用分野〕
本発明は、リードフレーム、特に樹脂との間の熱抵抗を
小さくすることのできるリードフレームに関する。[Detailed Description of the Invention] [Summary] The present invention relates to a lead frame having a die band covered with a resin together with a semiconductor chip mounted on the surface thereof, and an object of the present invention is to provide a lead frame that can reduce the thermal resistance between the lead frame and the resin. , [Industrial Application Field] The present invention relates to a lead frame, and particularly to a lead frame that can reduce thermal resistance between the lead frame and a resin.
搭載した半導体チップとともにリードフレームのダイパ
ッドとを樹脂により被覆して構成した樹脂封止型半導体
装置（以下、半導体装置と呼称）では、半導体装置をプ
リント基板にはんだ付け、特に半導体装置をペースト状
のはんだで仮付けした状態のプリント基板をコンヘヤ式
の加熱炉内を通過させてはんだ付け（リフロ一方式のは
んだ付け）する際の熱により樹脂との密着性を低下させ
ないようなリードフレームが要求されている。In a resin-sealed semiconductor device (hereinafter referred to as a semiconductor device), which is constructed by coating a mounted semiconductor chip and a die pad of a lead frame with resin, the semiconductor device is soldered to a printed circuit board, and in particular, the semiconductor device is soldered to a printed circuit board. There is a need for a lead frame that does not reduce the adhesion to the resin due to the heat generated when a printed circuit board that has been temporarily attached with solder is passed through a conveyor-type heating furnace for soldering (reflow one-way soldering). ing.
次に、従来のリードフレームについて図面を参照しなが
ら説明する。Next, a conventional lead frame will be described with reference to the drawings.
第２図は、従来のリードフレームを説明するための図で
、同図（ａ）はリードフレームの要部平面図、同図（ｂ
）はリードフレームのＡ−Ａ線断面図、同図（ｃ）は従
来のリードフレームを使用した半導体装置の断面図であ
る。FIG. 2 is a diagram for explaining a conventional lead frame. FIG.
) is a cross-sectional view taken along the line A-A of the lead frame, and FIG. 3(c) is a cross-sectional view of a semiconductor device using a conventional lead frame.
尚、同じ部品・材料に対しては全図を通して同じ記号を
付与しである。Note that the same symbols are given to the same parts and materials throughout the drawings.
即ち、従来のリードフレームは、同図（ａ）及び同図（
ｂ）に示すように、リードフレームのダイパッド２１の
一部を開口して形成したスリット２２を設けて構成して
いた。That is, the conventional lead frame is shown in FIG.
As shown in b), a slit 22 formed by opening a part of the die pad 21 of the lead frame was provided.
ところが、従来のリードフレームを使用した第２図の（
ｃ）図の半導体装置は、ダイパッド２１と樹脂１３との
密着性を良（するために当該ダイパッド２１にスリット
２２を設けていた。However, when using a conventional lead frame (see Figure 2),
c) In the semiconductor device shown in the figure, a slit 22 is provided in the die pad 21 in order to improve the adhesion between the die pad 21 and the resin 13.
このようなスリット２２をダイパッド２１に設けること
により、ダイパッド２１と樹脂１３との密着性は良くな
るものの、ダイパッド２１と樹脂１３との接触面積が小
さくなってダイパッド２１と樹脂１３間の熱抵抗が大き
くなることが避けられなかった。By providing such a slit 22 in the die pad 21, the adhesion between the die pad 21 and the resin 13 is improved, but the contact area between the die pad 21 and the resin 13 is reduced, and the thermal resistance between the die pad 21 and the resin 13 is reduced. Growing up was inevitable.
従って、このような半導体装置を使用すると、半導体チ
ップ１０自身の発熱により該半導体チップ１０の温度が
上昇し、半導体装置の電気的特性値を悪化させたり、ま
た半導体装置の信頼度を低下させるという問題があった
。Therefore, when such a semiconductor device is used, the temperature of the semiconductor chip 10 increases due to the heat generated by the semiconductor chip 10 itself, which deteriorates the electrical characteristics of the semiconductor device and reduces the reliability of the semiconductor device. There was a problem.
本発明は、このような問題を解決するためになされたも
ので、その目的はダイパッドと樹脂間の熱抵抗を小さく
することのできる半導体装置の提供にある。The present invention was made to solve these problems, and its purpose is to provide a semiconductor device that can reduce the thermal resistance between the die pad and the resin.
なお、図において、１４は半導体装ツブ１０のボンディ
ングパソド（図示せず）とリードフレームの外部リード
２３とを電気的に接続する金線である。In the figure, reference numeral 14 denotes a gold wire that electrically connects the bonding pad (not shown) of the semiconductor chip 10 and the external lead 23 of the lead frame.
前記目的は、第１図に示す如く表面に搭載した半導体チ
ップ１０とともに樹脂１３により被覆されるダイパッド
１１を有するリードフレームにおいて、ダイパッド１１
に切り込み部を設け、該切り込み部を裏面側に凸状にな
るように形成した切り起こし１２を設けたことを特徴と
するリードフレームにより達成される。The purpose is to provide a die pad 11 in a lead frame having a die pad 11 covered with resin 13 together with a semiconductor chip 10 mounted on the surface as shown in FIG.
This is achieved by a lead frame characterized in that a notch is provided at the top of the lead frame, and a cut-and-raised part 12 is provided in which the notch is formed so as to be convex on the back surface side.
本発明のリードフレームは、ダイパッド１１の裏面側、
すなわち半導体チップ１０を搭載する表面と反対側に切
り起こし１２を設けている。In the lead frame of the present invention, the back side of the die pad 11,
That is, the cut and raised portion 12 is provided on the opposite side to the surface on which the semiconductor chip 10 is mounted.
従って、リードフレームの切り起こし１２は、樹脂１３
に食い込むようにして樹脂１３と密着し、また切り起こ
し１２を切り起こした際にダイパッド１１に形成される
開口は、樹脂１３を入り込ませるようにして樹脂１３と
密着する。Therefore, the cut and raise 12 of the lead frame is made with resin 13.
The opening formed in the die pad 11 when the cut-and-raised part 12 is cut and raised is brought into close contact with the resin 13 so as to allow the resin 13 to enter therein.
斯クシて、本発明のリードフレームは、ダイパッド１１
と樹脂１３との密着性を向上させるとともに、ダイパッ
ド１１と樹脂１３間との密着面積を低下することがない
ために、ダイバンド１１と樹脂１３間の熱抵抗も大きく
することはない。Thus, the lead frame of the present invention has die pad 11
Since the adhesion between the die band 11 and the resin 13 is improved, and the adhesion area between the die pad 11 and the resin 13 is not reduced, the thermal resistance between the die band 11 and the resin 13 is not increased.
以下、本発明の一実施例を図面を参照しながら説明する
。An embodiment of the present invention will be described below with reference to the drawings.
第１図は、本発明の一実施例のリードフレームを説明す
るための図であって、同図（ａ）はリードフレームの要
部平面図、同図（ｂ）はリードフレームのＢ−Ｂ線断面
図、同図（ｃ）はリードフレームのＣ−Ｃ線断面図、同
図（ｄ）は本発明の一実施例のリードフレームを使用し
た半導体装置の断面図である。FIG. 1 is a diagram for explaining a lead frame according to an embodiment of the present invention, in which FIG. 1(a) is a plan view of main parts of the lead frame, and FIG. FIG. 3(c) is a sectional view taken along the line C--C of the lead frame, and FIG. 3(d) is a sectional view of a semiconductor device using the lead frame according to an embodiment of the present invention.
すなわち、本発明の一実施例のリードフレームは、同図
（ａ）、同図（ｂ）及び同図（ｃ）に示すようにリード
フレームのダイパッド１１の一部を“コ”の状に切り込
んだ後に、“コ”の状に切断した部分の未切断部分をほ
ぼ直角にダイパッド１１の裏面側に屈曲させた“切り起
こし１２”を複数設けて構成したものである。That is, in the lead frame of one embodiment of the present invention, a part of the die pad 11 of the lead frame is cut into a "U" shape as shown in FIGS. After that, a plurality of "cut and raised portions 12" are provided by bending the uncut portions of the "U" shaped portions toward the back side of the die pad 11 at approximately right angles.
この切り起こし１２は、フープ状の金属板、例えば燐青
銅板を抜き金型によりリードフレームを製造する際に同
時に形成したものである。The cut-and-raised portion 12 is formed at the same time as a hoop-shaped metal plate, for example, a phosphor bronze plate, is punched out and a lead frame is manufactured using a die.
そして、この切り起こし１２は、ダイパッド１１の裏面
に対して垂直方向の長さが５００μｍ、またダイパッド
１１の裏面と平行方向の幅が５００μｍとなるように構
成したものである。The cut and raised portion 12 is configured to have a length of 500 μm in a direction perpendicular to the back surface of the die pad 11 and a width of 500 μm in a direction parallel to the back surface of the die pad 11.
斯くして、モールド成型をして表面に搭載した半導体チ
ップ１０とともにダイパッド１１を樹脂１３により被覆
すると、リードフレームの切り起こし１２は樹脂１３に
食い込むようにして樹脂１３と密着し、また切り起こし
１２を切り起こした際にダイパッド１１に形成される開
口は、樹脂１３を入り込ませるようにして樹脂１３と密
着することとなる。In this way, when the die pad 11 is covered with the resin 13 along with the semiconductor chip 10 mounted on the surface by molding, the cut and raised portions 12 of the lead frame bite into the resin 13 and come into close contact with the resin 13, and the cut and raised portions 12 The opening formed in the die pad 11 when the die pad 11 is cut and raised will be in close contact with the resin 13 so that the resin 13 can enter therein.
従って、本発明のリードフレームは、ダイパッド１１と
樹脂１３との密着性を向上させるとともに、ダイパッド
１１と樹脂１３間の熱抵抗も大きく下げることとなる。Therefore, the lead frame of the present invention not only improves the adhesion between the die pad 11 and the resin 13, but also greatly reduces the thermal resistance between the die pad 11 and the resin 13.
この結果、本発明のリードフレームを採用した同図（ｄ
）に示す半導体装置においては、使用時に半導体チップ
１０自身の発熱により該半導体チップ１０の温度が上昇
しないため、半導体装置の電気的特性値のシフトが発生
することもなく、また半導体装置の信顛度も向上するこ
ととなる。As a result, the same figure (d) employing the lead frame of the present invention
In the semiconductor device shown in ), the temperature of the semiconductor chip 10 does not rise due to the heat generated by the semiconductor chip 10 itself during use, so there is no shift in the electrical characteristic values of the semiconductor device, and the reliability of the semiconductor device is improved. This will also improve the degree of
以上の説明から明らかなように本発明によれば、樹脂と
密着性も良く、且つ樹脂との間の熱抵抗を小さくするこ
とのできるリードフレームを提供することが可能となる
。As is clear from the above description, according to the present invention, it is possible to provide a lead frame that has good adhesion to the resin and can reduce the thermal resistance between the lead frame and the resin.
従って、本発明のリードフレームを採用した半導体装置
においては、使用時に半導体チップの温度も少なくなる
ために、半導体装置の電気的特性値のシフトが発生する
こともなく、また半導体装置の信転度も向上することと
なる。Therefore, in a semiconductor device employing the lead frame of the present invention, the temperature of the semiconductor chip decreases during use, so there is no shift in the electrical characteristic values of the semiconductor device, and the reliability of the semiconductor device also increases. will also improve.
第１図は、本発明の一実施例のリードフレームを説明す
るための図、
第２図は、従来のリードフレームを説明するための図で
ある。
図において、
１０は半導体チップ、
１１はダイパッド、
１２は切り起こし、
１３は樹脂、
１４は金線をそれぞれ示す。
＋ｂ＋ ソーＬ゛フ（−乙ｔｙ＋Ｂ−ＢＩＡ１ｆｄわ図
（Ｃ） ソーＶ’ｎ−１，ｐ Ｃ−Ｃｇａケｉυ必ｔｃ
ｈオ禍≦ｇＦ１ｒ−ＩＣ；１ｌＪｔｐ＋９−にワＬ−Ｌ
ｅｆＰ吊ｔｒ、４導＃ＩＣｆｆ、ｌｆｆｎｍシト発明め
一突オ酸例バリードアし４をｔえ８斤Ｔメリｑｆｊり第
１図FIG. 1 is a diagram for explaining a lead frame according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining a conventional lead frame. In the figure, 10 is a semiconductor chip, 11 is a die pad, 12 is a cut and raised part, 13 is a resin, and 14 is a gold wire. +b+ So L゛fu (-Bty+B-BIA1fdwa figure (C) So V'n-1,p C-Cgakeiυmustc
h o misfortune≦gF1r-IC; 1lJtp+9-niwa L-L
efP hanging tr, 4 conductor #ICff, lffnm site invention, one-shot acid example barrier door, 4, t8 catty, T meri qfj Figure 1
Claims (1)
１３）により被覆されるダイパッド（１１）を有するリ
ードフレームにおいて、 前記ダイパッド（１１）に切り込み部を設け、該切り込
み部を裏面側に凸状になるように形成した切り起こし（
１２）を設けたことを特徴とするリードフレーム。[Claims] Along with the semiconductor chip (10) mounted on the surface, the resin (
13) A lead frame having a die pad (11) covered with a die pad (11), wherein the die pad (11) is provided with a cut portion, and the cut portion is formed to have a convex shape on the back surface side.
12) A lead frame characterized by being provided with.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2086136A JPH03284866A (en) | 1990-03-30 | 1990-03-30 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2086136A JPH03284866A (en) | 1990-03-30 | 1990-03-30 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03284866A true JPH03284866A (en) | 1991-12-16 |
Family
ID=13878304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2086136A Pending JPH03284866A (en) | 1990-03-30 | 1990-03-30 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03284866A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016134604A (en) * | 2015-01-22 | 2016-07-25 | エスアイアイ・セミコンダクタ株式会社 | Semiconductor device and method of manufacturing the same |
-
1990
- 1990-03-30 JP JP2086136A patent/JPH03284866A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016134604A (en) * | 2015-01-22 | 2016-07-25 | エスアイアイ・セミコンダクタ株式会社 | Semiconductor device and method of manufacturing the same |
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