GB2147457A - Encapsulated semiconductor device with composite conductive leads - Google Patents

Encapsulated semiconductor device with composite conductive leads Download PDF

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Publication number
GB2147457A
GB2147457A GB8325898A GB8325898A GB2147457A GB 2147457 A GB2147457 A GB 2147457A GB 8325898 A GB8325898 A GB 8325898A GB 8325898 A GB8325898 A GB 8325898A GB 2147457 A GB2147457 A GB 2147457A
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United Kingdom
Prior art keywords
semiconductor device
stub
conductive leads
filamentary
portions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB8325898A
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GB8325898D0 (en
Inventor
Peter Irwin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Electronics UK Ltd
Original Assignee
Philips Electronic and Associated Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronic and Associated Industries Ltd filed Critical Philips Electronic and Associated Industries Ltd
Priority to GB8325898A priority Critical patent/GB2147457A/en
Publication of GB8325898D0 publication Critical patent/GB8325898D0/en
Publication of GB2147457A publication Critical patent/GB2147457A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

A semiconductor device, eg having a TO-220 outline, comprises a semiconductor element embedded in an encapsulating package (13). A plurality of conductive leads which are electrically connected to the element extend from the encapsulation (13). The conductive leads comprise flat strips formed from a relatively compact lead frame and themselves form stub-like projections (6b, 7b, 8b) outside the encapsulation (13). The conductive leads also comprise separate filamentary portions such as copper or copper-containing wires (15, 16, 17) attached, eg by welding, to the projections (6b, 7b, 8b) respectively. The joints may be coated with plastics 18, 19, 20. <IMAGE>

Description

SPECIFICATION Semiconductor device This invention relates to a semiconductor device comprising a semiconductor element embedded in an encapsulating package, wherein a plurality of conductive leads extending from within said package are electrically connected to said semiconductor element, said conductive leads respectively comprising flat strips formed formed from a portion of a unitary lead frame.
In the semiconductor industry the mass production of encapsulated semiconductor devices having external electrical connections is facilitated by employing a lead frame in the form of a patterned metallic strip comprising a plurality of interconnected leads. The lead frame provides the conductive lead structure for a plurality of devices which can be separated towards the end of device manufacture.
A semiconductor device having the features mentioned in the opening paragraph is known from British Patent No. 1,105,207. As disclosed in that patent specification the conductive leads of each device are in the form of three mutually parallel flat strips. The exposed portions of each strip, i.e. external to the encapsulating package, is much longer than the encapsulated portion.
Making a lead frame by patterning a strip of metal involves discarding a proportion of lead frame material. The amount of material discarded is dependent on the length of the conductive leads formed from the lead frame.
As it is usual for lead frames to be made of copper or copper-containing materials which are relatively expensive the financial loss due to discarded material can be significant.
A further disadvantage of long conductive leads formed from a lead frame is that they are prone to damage during assembly of the device.
According to the present invention there is provided a semiconductor device comprising a semiconductor element embedded in an encapsulating package, wherein a plurality of conductive leads extending from within said package are electrically connected to said semiconductor element, said conductive leads respectively comprising flat strips formed from a portion of a unitary lead frame, characterised in that each flat strip presents a stub-like projection outside the package, and each conductive lead further comprises a separate filamentary portion attached to said projection.
A semiconductor device in accordance with the invention thus employs a two-part lead format. The parts of the conductive leads which are formed from the lead frame are relatively short, thereby presenting a stub-like projection from the encapsulation, and this has the advantage that the lead frame can be relatively compact. Not only does this result in a significant cost saving in lead frame material but also in encapsulating material because it is possible to increase the capacity of moulds used in the encapsulation process. That is to say, more devices can be encapsulated per unit area occupied by the mould.
Another advantage of devices in accordance with the invention is that the attachment of the filamentary portions to the stub-like projections can be carried out at a relatively late stage of device assembly. For the major part of the assembly process, therefore, the conductive leads are relatively short so that they are less likely to be damaged.
The relative lengths of the stub-like projections and the filamentary portions will depend on particular applications and requirements.
However the saving in lead frame material increases as the length of the stub-like projections decreases. Preferably the filamentary portion is longer than the stub-like projection.
Also, it is preferable that the filamentary portion is narrower than the stub-like projection. This provides at the area where the filamentary portion meets the stub-like projection a shoulder which facilitates mounting and assembly of devices in a printed circuit board by acting as an abutment when the device is inserted into appropriately dimensioned locating holes in the printed circuit board.
The filamentary portions can be formed from wire made of copper or copper alloy which, to facilitate soldering, may be coated with a different metal such as, for example, nickel or silver provided by plating, or tin provided by dipping. This coating can be provided more uniformly on the filamentary portions of a device in accordance with the invention than on cropped portions of a lead frame as in the prior art where sharp edges or burrs may result in an uneven coating.
Because the filamentary portions are separate from the stub-like projections the material of the filamentary portions may be selected independently of the lead frame material allowing a material to be chosen which is more compatible with the preferred requirements for conductive leads without being dictated by the requirements for the lead frame material.
The filamentary portions can readily be attached to the stub-like projections by welding, for example using laser or resistance welding.
If desired the weld may be covered with a coating of, for example, a plastics or resinous insulating material which enhances appearance and increases the creepage path. An individual coating may be provided for each conductive lead or, alternatively, a single coating may be provided in the form of a block which covers the welds of all the conductive leads together.
An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings, in which, Figure 1 is a plan view of part of a lead frame for use in making a semiconductor device in accordance with the invention, and Figure 2 is a plan view of a semiconductor device in accordance with the invention including a portion of the lead frame in Fig. 1.
Fig. 1 shows two similar portions of a unitary lead frame 1 which typically comprises twenty such portions for making twenty individually packaged semiconductor devices. The lead frame may be formed from a milled, rolled or coined strip of copper 240mm long, 35mm wide, and 0.7mm thick. The strip is patterned by known chemical etching or stamping techniques. The lead frame shown in Fig. 1 is for making three lead devices having a TO-220 outline and comprises two parallel rails 2, 3 running the full length of the lead frame 1. Between the rails there is a mounting area 4 for a semiconductor element such as a transistor 5 formed in a die of silicon typically 3mm x 3mm and 300 micrometres thick. The transistor is electrically and thermally connected in known manner to the support 4 which also acts as a heat sink.
Three conductive lead portions in the form of substantially parallel flat strips 6,7,8 approximately 6 mm long extend from the area of the support 4 to the rail 2. The lead portions 6,7,8 are orthogonal to the rails 2 and 3. The centre lead portion 7 may be for example 0.7mm wide and is integral with the support 4 for making electrical connection to the back surface of the transistor 5. The two outer lead portions 6 and 8 may be 1.3mm wide and adjacent the support 4 terminate in wider portions 6a and 8a respectively. There is a gap of approximately 0.5mm between the portions 6a, 8a and the support 4.The lead portions 6 and 8 are electrically connected to the transistor in known manner with wire bonds 9 and 10 respectively extending from the portions 6a, 8a to contact areas 11, 12 respectively on the front surface of the transistor 5.
The transistor 5 is embedded in a block of plastics material to form an encapsulating packag#e 13 represented by a dot and dash line in Fig. 1. The encapsulating material is provided in known manner using a transfer moulding technique. However, as mentioned earlier, compared with prior art devices a greater economy in moulding can be achieved because the short lead portions of the lead frame enable more devices to be encapsulated in a mould of a given area.
The lead frame portions 6,7,8 protrude from within the package 13 to form stub-like projections 6b, 7b, 8b. These projections may extend for example 4.5mm outside the package 13.
The lead frame is cropped as shown by the broken lines in Fig. 1 to form individual components in preparation for the next stage of assembly. Thus rail 3 is cropped transversely to its length twice between adjacent frame portions and at the other rail 2 the leads 6,7,8 are cropped immediately adjacent the rail 2 in a direction extending parallel to the rails.
To each of the projections 6b,7b,8b is attached a wire 1 5,1 6,1 7 respectively (see Fig. 2) made for example of copper or copper alloy and, if desired, plated with nickel or silver or dipped in tin to facilitate soldering.
The wires 1 5,16,1 7 may have a circular cross-section with a diameter of, for example, 0.7mm. Alternatively, they may be flat strips, for example 0.5mm thick and 0.7mm wide.
The overall length of each wire may be, for example, 12mm. At the area of attachment. ie the join between the wires and the stub-like projections, the wires 1 5,1 6,1 7 may overlap the stub-like projections 6b,7b,8b by 3mm.
Thus the total length of the conductive leads outside the encapsulating package 13 is 13.5mm.
The wires 1 5,1 6,1 7 may suitably be attached to the projections 6b,7b,8b using metal-joining techniques which are well known in their own right such as laser or resistance welding.
The wires 1 5,1 6,1 7 may be presented for attachment to the rest of the device in a mass production situation by arranging that they are temporarily attached in groups of three with the appropriate spacing on a strip of adhesive tape. The wires can be fed onto the tape from three separate spools and cropped to the appropriate length once they are stuck on the tape. The tape can then be progressed for a further group of three wires to be fixed tempo- rarily thereto. In this manner the wires can be presented to the stub-like projections of the near-complete device, already correctly spaced in groups of three and the adhesive tape can be removed after the welding operation has been completed.
If desired, the encapsulated device can be finished by covering the conductive leads at the area of the weld with individual coatings 1 8,1 9,20 of plastics or resinous material. This helps to enhance the appearance of the completed device and also increases the creepage path.
In view of the above description it will be evident that many modifications are possible within the scope of the invention. In particular the semiconductor device may comprise more or less than three conductive leads and may have an outline other than that designated by TO-220. Also, the encapsulated semiconductor element need not be a transistor, but instead it may, for example, be a diode or a thyristor. Moreover, instead of covering the joins between the filamentary portions and the stub-like projections with individual coatings for each conductive lead a single coating may be provided in the form of a block covering the joins of all the conductive leads together.

Claims (8)

1. A semiconductor device comprising a semiconductor element embedded in an encapsulating package, wherein a plurality of conductive leads extending from within said package are electrically connected to said semiconductor element, said conductive leads respectively comprising flat strips formed from a portion of a unitary lead frame, characterised in that each flat strip presents a stub-like projection outside the package, and each conductive lead further comprises a separate filamentary portion attached to said projection.
2. A semiconductor device as claimed in Claim 1, characterised in that the filamentary portion is longer than the stub-like projection.
3. A semi-conductor device as claimed in Claim 1 or Claim 2, characterised in that the filamentary portion is narrower than the stublike projection.
4. A semiconductor device as claimed in any of the preceding claims, characterised in that the filamentary portions are attached to the stub-like projections by welding.
5. A semiconductor device as claimed in any of the preceding claims, characterised in that the filamentary portions and the stub-like projections are made of different materials.
6. A semiconductor device as claimed in any of the preceding claims, characterised in that the filamentary portions are formed from copper or copper-containing wire.
7. A semiconductor device as claimed in any of the preceding claims, characterised in that each conductive lead is provided with a coating which covers at least the join between the filamentary portion and the stub-like projection.
8. A semiconductor device substantially as herein described with reference to Figs. 1 and 2 of the accompanying drawing.
GB8325898A 1983-09-28 1983-09-28 Encapsulated semiconductor device with composite conductive leads Withdrawn GB2147457A (en)

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Application Number Priority Date Filing Date Title
GB8325898A GB2147457A (en) 1983-09-28 1983-09-28 Encapsulated semiconductor device with composite conductive leads

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Application Number Priority Date Filing Date Title
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GB2147457A true GB2147457A (en) 1985-05-09

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5001547A (en) * 1983-10-21 1991-03-19 Sgs Microelettronica S.P.A. Method and apparatus for improving thermal coupling between a cooling plate of a semiconductor package housing and a heat sink
EP0789507A3 (en) * 1996-02-08 1998-02-25 Bayerische Motoren Werke Aktiengesellschaft, Patentabteilung AJ-3 Encapsulated electronic controlling device and method of fabricating the same
DE10142472A1 (en) * 2001-08-31 2002-10-31 Infineon Technologies Ag Electronic high voltage and power component comprises external contact pins and/or external contact lug protruding from a housing and partially surrounded by a heat conducting protective layer based on an organic ceramic

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1113217A (en) * 1964-10-26 1968-05-08 Matsushita Electronics Corp Method of manufacturing semiconductor devices
GB2093401A (en) * 1981-01-17 1982-09-02 Sanyo Electric Co Composite film

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1113217A (en) * 1964-10-26 1968-05-08 Matsushita Electronics Corp Method of manufacturing semiconductor devices
GB2093401A (en) * 1981-01-17 1982-09-02 Sanyo Electric Co Composite film

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5001547A (en) * 1983-10-21 1991-03-19 Sgs Microelettronica S.P.A. Method and apparatus for improving thermal coupling between a cooling plate of a semiconductor package housing and a heat sink
EP0789507A3 (en) * 1996-02-08 1998-02-25 Bayerische Motoren Werke Aktiengesellschaft, Patentabteilung AJ-3 Encapsulated electronic controlling device and method of fabricating the same
DE10142472A1 (en) * 2001-08-31 2002-10-31 Infineon Technologies Ag Electronic high voltage and power component comprises external contact pins and/or external contact lug protruding from a housing and partially surrounded by a heat conducting protective layer based on an organic ceramic

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