JP2501950B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2501950B2 JP2501950B2 JP2298826A JP29882690A JP2501950B2 JP 2501950 B2 JP2501950 B2 JP 2501950B2 JP 2298826 A JP2298826 A JP 2298826A JP 29882690 A JP29882690 A JP 29882690A JP 2501950 B2 JP2501950 B2 JP 2501950B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor device
- layer
- ground
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49883—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Description
【発明の詳細な説明】 ［産業上の利用分野］ この発明は半導体装置に係り、特に数百本以上のピン
数の、多Pin半導体装置の構造に関するものである。Description: TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to the structure of a multi-pin semiconductor device having several hundreds or more pins.
［従来の技術］ 安価な超多Pinパッケージとして、“TAB（tapeautoma
ted bonding）”と呼ばれるテープキャリア形の半導体
装置が使用されている。第４図および第５図には従来の
この種の半導体装置の構造を示した。第４図は樹脂によ
って形成される樹脂封止部であるパッケージ本体（７）
（第５図参照）のうちの半導体装置上部に形成される上
部樹脂部分（８）を透視して示した透視正面図、第５図
は第４図の線Ｖ−Ｖに沿った断面図である。半導体素子
（１）の表面上に形成された複数の電極（２）が、絶縁
テープ（３）上に形成されたリード（４）のインナリー
ド部（５）に電気的に接続され、リード（４）のアウタ
リード（６）がパッケージ本体（７）の外部に導出する
ように半導体素子（１）およびインナリード（５）が樹
脂からなるパッケージ本体（７）により封止されてい
る。[Prior Art] As an inexpensive ultra-high pin package, "TAB (tapeautoma
A tape carrier type semiconductor device called "ted bonding)" is used. FIGS. 4 and 5 show the structure of a conventional semiconductor device of this type. FIG. 4 shows a resin formed by resin. Package body (7) that is the sealing part
A transparent front view showing the upper resin portion (8) formed on the upper part of the semiconductor device (see FIG. 5), and FIG. 5 is a sectional view taken along the line VV in FIG. is there. A plurality of electrodes (2) formed on the surface of the semiconductor element (1) are electrically connected to an inner lead portion (5) of a lead (4) formed on an insulating tape (3), and a lead ( The semiconductor element (1) and the inner leads (5) are sealed by the package body (7) made of resin so that the outer lead (6) of 4) is led out of the package body (7).
このような半導体装置の動作時には、半導体素子
（１）から熱が発生する。この熱はリード（４）および
パッケージ本体（７）を通して半導体装置外部へ拡散さ
れる。During operation of such a semiconductor device, heat is generated from the semiconductor element (1). This heat is diffused to the outside of the semiconductor device through the lead (4) and the package body (7).
［発明が解決しようとする課題］ 従来の半導体装置は以上のように構成されていたが、
半導体素子の高集積度化に伴い発熱量は増大するが、パ
ッケージ本体を構成するエポキシ等の樹脂は熱伝導率が
低いので、半導体素子で発生した熱は効率よく半導体装
置の外部へ放出されずに半導体装置内に残ってしまう。
このため発熱量の大きい半導体素子を用いると半導体素
子が昇温して誤動作を起こす等、半導体装置の信頼度が
低下するという課題があった。さらに、多Pinパッケー
ジの場合、リードが長くなるためにインダクタンスが大
きくなり、動作時の雑音や半導体装置の応答速度が遅く
なる等、電気特性が低下するという課題もあった。ま
た、樹脂よりも熱伝導性が優れているセラミック材で、
多層構造のパッケージ本体を形成すれば、半導体装置の
放熱性および応答速度を向上させることができるが、セ
ラミック材は著しく高価なために、半導体装置の製造コ
ストが高くなるという課題があった。[Problems to be Solved by the Invention] Although the conventional semiconductor device is configured as described above,
Although the amount of heat generated increases as the degree of integration of semiconductor elements increases, the heat generated by semiconductor elements is not efficiently released to the outside of the semiconductor device because the resin such as epoxy that constitutes the package body has low thermal conductivity. And remain in the semiconductor device.
Therefore, when a semiconductor element that generates a large amount of heat is used, there is a problem that the reliability of the semiconductor device is lowered, such as the temperature of the semiconductor element increasing and malfunctioning. Further, in the case of the multi-pin package, there is a problem that the electrical characteristics are deteriorated such that the lead becomes long and the inductance becomes large, the noise during operation and the response speed of the semiconductor device become slow. Also, with a ceramic material that has better thermal conductivity than resin,
Forming a package body having a multi-layered structure can improve the heat dissipation and response speed of the semiconductor device, but there is a problem that the manufacturing cost of the semiconductor device increases because the ceramic material is extremely expensive.
この発明は上記の課題を解決するためになされたもの
で、放熱性および電気特性が優れていて、しかも安価な
半導体装置を得ることを目的とする。The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor device which has excellent heat dissipation and electrical characteristics and is inexpensive.
［課題を解決するための手段］ 上記の目的に鑑み、この発明は、半導体素子を樹脂封
止して形成された半導体装置であって、表面に複数の電
極を有する半導体素子と、内端側が半導体素子の複数の
電極のそれぞれ所定の電極に接続され外端側が半導体装
置外部に延びる、少なくとも１分の接地リードおよび電
源リード並びに各種信号リードを含むリード手段と、高
熱伝導材料からなる放熱層と、この放熱層上に形成され
た絶縁材層と、リード手段の接地リードおよび電源リー
ド並びに半導体素子の数および位置に従って絶縁材層上
に平面状に形成されたそれぞれ少なくとも１枚の接地層
および電源層と、半導体素子を接地層上に電気的接続を
伴って固定し、また接地リードおよび電源リードを接地
層および電源層へそれぞれ電気的に接続する電気的接続
手段と、リード手段の各リードの外端側および放熱層の
少なくとも一部を露出させて各部分を一体に封止する樹
脂封止部と、を備えた半導体装置にある。[Means for Solving the Problems] In view of the above object, the present invention is a semiconductor device formed by resin-sealing a semiconductor element, wherein a semiconductor element having a plurality of electrodes on the surface and an inner end side Lead means including at least one minute of ground lead, power supply lead, and various signal leads connected to respective predetermined electrodes of a plurality of electrodes of the semiconductor element and extending to the outside of the semiconductor device; and a heat dissipation layer made of a high heat conductive material. An insulating material layer formed on the heat dissipation layer, and at least one grounding layer and a power supply formed on the insulating material layer in a plane according to the number and position of the grounding lead and the power supply lead of the lead means and the semiconductor element. Layer and the semiconductor element are fixed on the ground layer with electrical connection, and the ground lead and the power lead are electrically connected to the ground layer and the power layer, respectively. A semiconductor device is provided with an electrical connection means and a resin sealing portion that exposes at least a part of the outer end side of each lead of the lead means and the heat dissipation layer and integrally seals each part.
［作用］ この発明においては、半導体素子で発生した熱が半導
体素子から放熱層に伝導し、放熱層から半導体装置の外
部に放出される。また、パッケージ内に表面積の大きい
電源層と接地層が形成され、これらに電源リードおよび
接地リードがそれぞれ接続されているため、半導体装置
の電源系が低インダクタンスとなり電気特性が改善され
る。[Operation] In the present invention, the heat generated in the semiconductor element is conducted from the semiconductor element to the heat dissipation layer, and is radiated from the heat dissipation layer to the outside of the semiconductor device. Further, since the power supply layer and the ground layer having a large surface area are formed in the package and the power supply lead and the ground lead are respectively connected to them, the power supply system of the semiconductor device has a low inductance and the electrical characteristics are improved.
［実施例］ 以下、この発明の一実施例を図について説明する。第
１図ないし第３図はこの発明の半導体装置の一実施例を
示す図であり、従来のものと同一符号で示された部分は
同一、もしくは相当部分を示す。第１図は樹脂によって
形成されるパッケージ本体（７）（第２図参照）のうち
の半導体装置上部に形成される上部樹脂部分（８）を透
視し、かつ絶縁テープ（３）の一部を破断して示した半
導体装置の透視正面図、第２図は第１図の線II−IIに沿
った断面図、第３図は接地層である接地板（11）および
電源層である電源板（12）から下の部分の斜視図であ
る。放熱層である放熱体（９）は熱伝導率の高い材料、
例えば銅（Cu）材料からなり、その上にエポキシ系の樹
脂からなる絶縁材層（10）が形成されている。さらにこ
の絶縁材層（10）の上にはそれぞれ銅箔からなる接地板
（11）および電源板（12）が平面状に形成されている。
これらの接地板（11）および電源板（12）の数および形
状は、半導体素子（１）や接地リード（14）および電源
リード（15）の数およびその位置に従って決定される。
この実施例のものにおいては、半導体素子（１）が絶縁
材層（10）の中央部分に位置しており、また接地リード
（14）が半導体素子（１）に対して互い反対側になる位
置にそれぞれ設けられ、電源リード（15）が接地リード
（14）と直行する方向の互いに反対側になる位置にそれ
ぞれ設けられている。従って接地板（11）が絶縁材層
（10）上の中央から両側の接地リード（14）の下方に延
びるように設けられ、電源板（12）の接地板（11）の両
側に電源リード（15）の下方に延びるように形成されて
いる。この接地板（11）上には半導体素子（１）が導電
性樹脂（13）により固定され、半導体素子（１）の裏面
は接地板（11）に電気的に接続されている。また、接地
板（11）には接続縁テープ（３）に設けられた貫通穴
（3a）を介して接地リード（14）が導電性樹脂（13）に
より電気的に接続される。電源板（12）には同様に絶縁
テープ（３）に設けられた貫通穴（3a）を介して電源リ
ード（15）が導電性樹脂（13）により電気的に接続され
る。半導体素子（１）の表面に設けられた複数の電極
（２）には、接地リード（14）、電源リード（15）およ
び信号リード（16）のインナリード（５）がそれぞれ接
続されている。そして上記各部分がエポキシ樹脂により
樹脂封止され、図示したようにパッケージ本体（７）を
形成している。[Embodiment] An embodiment of the present invention will be described below with reference to the drawings. 1 to 3 are views showing an embodiment of a semiconductor device of the present invention, in which parts designated by the same reference numerals as those of the conventional one are the same or corresponding parts. FIG. 1 shows the upper resin portion (8) of the package body (7) (see FIG. 2) formed of resin, which is formed on the upper portion of the semiconductor device, and shows a part of the insulating tape (3). FIG. 2 is a perspective front view of the semiconductor device cut away, FIG. 2 is a sectional view taken along line II-II in FIG. 1, and FIG. 3 is a ground plate (11) as a ground layer and a power plate as a power layer. FIG. 12 is a perspective view of a portion below (12). The radiator (9), which is a heat dissipation layer, is made of a material having high thermal conductivity,
For example, a copper (Cu) material is formed, and an insulating material layer (10) made of an epoxy resin is formed thereon. Further, a ground plate (11) and a power supply plate (12) each made of copper foil are formed on the insulating material layer (10) in a planar shape.
The numbers and shapes of the ground plate (11) and the power supply plate (12) are determined according to the numbers and positions of the semiconductor element (1), the ground lead (14) and the power supply lead (15).
In this embodiment, the semiconductor element (1) is located in the central portion of the insulating material layer (10), and the ground lead (14) is on the opposite side of the semiconductor element (1). And the power supply leads (15) are provided at positions opposite to each other in the direction orthogonal to the ground leads (14). Therefore, the ground plate (11) is provided so as to extend from the center of the insulating material layer (10) to below the ground leads (14) on both sides, and the power leads (11) are provided on both sides of the ground plate (11) of the power plate (12). It is formed so as to extend below 15). The semiconductor element (1) is fixed on the ground plate (11) by a conductive resin (13), and the back surface of the semiconductor element (1) is electrically connected to the ground plate (11). Further, the ground lead (14) is electrically connected to the ground plate (11) by the conductive resin (13) through the through hole (3a) provided in the connection edge tape (3). Similarly, the power supply lead (15) is electrically connected to the power supply plate (12) by the conductive resin (13) through the through hole (3a) provided in the insulating tape (3). An inner lead (5) of a ground lead (14), a power supply lead (15) and a signal lead (16) is connected to the plurality of electrodes (2) provided on the surface of the semiconductor element (1). Each of the above parts is resin-sealed with an epoxy resin to form a package body (7) as shown in the figure.
このような半導体装置の動作時においては、半導体素
子（１）で発生した熱が主として熱伝導率の良い放熱体
（９）へ伝導され、半導体装置の外部へ放出される。放
熱体（９）と接地板（11）は縁材材層（10）によって電
気的に絶縁されているため、放熱体（９）には半導体素
子（１）の裏面電位がかからない。このため半導体装置
を基板実装する際、放熱体（９）が他の部品あるいは基
板に接触しても、電気的短絡等の問題が発生することは
ない。さらに、放熱体（９）の一部がパッケージ本体
（７）の外部に露出しているため、放熱体（９）に外部
放熱フィン（図示せず）を容易に取り付けることができ
るので、消費電力の極めて大きい半導体素子（１）に適
用することが可能である。また、面積の広い接地板（1
1）および電源板（12）に接地リード（14）および電源
リード（14）をそれぞれ電気的に接続したことにより、
実質的にリードの幅を広げたことになり、この結果、電
源から接地へ通り抜ける半導体装置内の電源系インダク
タンスを小するようにした。これにより雑音を少なくす
ることができ、電気的特性が向上する。During the operation of such a semiconductor device, the heat generated in the semiconductor element (1) is mainly conducted to the heat radiator (9) having a high thermal conductivity and radiated to the outside of the semiconductor device. Since the radiator (9) and the ground plate (11) are electrically insulated by the edge material layer (10), the back surface potential of the semiconductor element (1) is not applied to the radiator (9). Therefore, when the semiconductor device is mounted on the substrate, even if the heat radiator (9) comes into contact with other components or the substrate, a problem such as an electrical short circuit does not occur. Furthermore, since a part of the heat radiator (9) is exposed to the outside of the package body (7), an external heat radiation fin (not shown) can be easily attached to the heat radiator (9), resulting in power consumption. It is possible to apply to a semiconductor device (1) having an extremely large size. Also, a large area ground plate (1
1) and the power supply plate (12) are electrically connected to the ground lead (14) and the power supply lead (14), respectively,
This means that the width of the lead is substantially widened, and as a result, the inductance of the power supply system in the semiconductor device that passes from the power supply to the ground is reduced. As a result, noise can be reduced and electrical characteristics are improved.
なお、上記実施例のものは半導体素子の各電極とイン
ナリードの先端が直接接続されているが、各電極とイン
ナリードが金属細線で接続された半導体装置においても
この発明は適用可能である。Although the electrodes of the semiconductor element and the tips of the inner leads are directly connected to each other in the above embodiment, the present invention is also applicable to a semiconductor device in which the electrodes and the inner leads are connected to each other by a fine metal wire.
［発明の効果］ 以上のようにこの発明によれば、半導体素子で発生す
る熱を半導体装置外部に拡散させるための放熱体を設け
たこと、および面積の大きい接地板および電源板を半導
体装置内に設け、これに接地リードおよび電源リードを
電気的にそれぞれ接続して、実質的にリード幅を広げて
電源系のインダクタンスを小さくしたことにより、放熱
性および電気特性の優れた半導体装置が得られるという
効果がある。[Effects of the Invention] As described above, according to the present invention, a heat radiator for diffusing heat generated in a semiconductor element to the outside of the semiconductor device is provided, and a large-area ground plate and power supply plate are provided in the semiconductor device. A semiconductor device having excellent heat dissipation and electrical characteristics can be obtained by electrically connecting the grounding lead and the power supply lead to each of them, and substantially widening the lead width to reduce the inductance of the power supply system. There is an effect.
第１図はこの発明の一実施例による半導体装置の上部樹
脂部分を透視して示した透視正面図、第２図は第１図の
線II−IIに沿った断面図、第３図は接地板および電源板
から下の部分の斜視図、第４図は従来の半導体装置の上
部樹脂部分を透視して示した透視正面図、第５図は第４
図の線Ｖ−Ｖに沿った断面図である。 各図において、（１）は半導体素子、（２）は電極、
（３）は絶縁テープ、（3a）は貫通穴、（４）はリー
ド、（５）はインナリード、（６）はアウタリード、
（７）はパッケージ本体、（８）はエポキシ樹脂、
（９）は放熱体、（10）は絶縁材層、（11）は接地板、
（12）は電源板、（13）は導電性樹脂、（14）は接地リ
ード、（15）は電源リード、（16）は信号線リードであ
る。 尚、図中、同一符号は同一又は相当部分を示す。FIG. 1 is a perspective front view showing an upper resin portion of a semiconductor device according to an embodiment of the present invention as seen through, FIG. 2 is a sectional view taken along line II-II of FIG. 1, and FIG. FIG. 4 is a perspective view of a portion below the ground plane and the power supply plate, FIG. 4 is a perspective front view showing a top resin portion of a conventional semiconductor device, and FIG.
FIG. 5 is a cross-sectional view taken along the line VV in the figure. In each figure, (1) is a semiconductor element, (2) is an electrode,
(3) is an insulating tape, (3a) is a through hole, (4) is a lead, (5) is an inner lead, (6) is an outer lead,
(7) is the package body, (8) is epoxy resin,
(9) is a radiator, (10) is an insulating material layer, (11) is a ground plate,
(12) is a power board, (13) is a conductive resin, (14) is a ground lead, (15) is a power lead, and (16) is a signal line lead. In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (1)
体装置であって、 表面に複数の電極を有する半導体素子と、 内端側が上記半導体素子の複数の電極のそれぞれ所定の
電極に接続され外端側が半導体装置外部に延びる、少な
くとも１本の接地リードおよび電源リード並びに各種信
号リードを含むリード手段と、 高熱伝導材料からなる放熱層と、 この放熱層上に形成された絶縁材層と、 上記リード手段の接地リードおよび電源リード並びに上
記半導体素子の数および位置に従って上記絶縁材層上に
平面状に形成されたそれぞれ少なくとも１枚の接地層お
よび電源層と、 上記半導体素子を上記接地層上に電気的接続を伴って固
定し、また上記接地リードおよび電源リードを上記接地
層および電源層へそれぞれ電気的に接続する電気的接続
手段と、 上記リード手段の各リードの外端側および放熱層の少な
くとも一部を露出させて上記各部分を一体に封止する樹
脂封止部と、 を備えた半導体装置。1. A semiconductor device formed by resin-sealing a semiconductor element, comprising: a semiconductor element having a plurality of electrodes on its surface; and an inner end side connected to a predetermined electrode of each of the plurality of electrodes of the semiconductor element. A lead means including at least one ground lead, a power supply lead, and various signal leads whose outer end extends to the outside of the semiconductor device; a heat dissipation layer made of a highly heat conductive material; and an insulating material layer formed on the heat dissipation layer. A ground lead and a power lead of the lead means, and at least one ground layer and a power layer respectively formed in a plane on the insulating material layer according to the number and position of the semiconductor element, and the semiconductor element being the ground layer. An electrical connection that is fixed with an electrical connection on top and that electrically connects the ground lead and the power lead to the ground layer and the power layer, respectively. Stage and a semiconductor device and a resin sealing portion for sealing together said respective portions to expose at least a portion of the outer end side and the heat radiating layer of each lead of the lead means.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2298826A JP2501950B2 (en) | 1990-11-06 | 1990-11-06 | Semiconductor device |
| FR9104257A FR2668854B1 (en) | 1990-11-06 | 1991-04-08 | RESIN - CONDITIONED SEMICONDUCTOR DEVICE. |
| DE4129160A DE4129160C2 (en) | 1990-11-06 | 1991-09-02 | Semiconductor arrangement in a plastic housing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2298826A JP2501950B2 (en) | 1990-11-06 | 1990-11-06 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04171848A JPH04171848A (en) | 1992-06-19 |
| JP2501950B2 true JP2501950B2 (en) | 1996-05-29 |
Family
ID=17864721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2298826A Expired - Lifetime JP2501950B2 (en) | 1990-11-06 | 1990-11-06 | Semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2501950B2 (en) |
| DE (1) | DE4129160C2 (en) |
| FR (1) | FR2668854B1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5255430A (en) * | 1992-10-08 | 1993-10-26 | Atmel Corporation | Method of assembling a module for a smart card |
| JP2677242B2 (en) * | 1995-04-27 | 1997-11-17 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| US7741706B2 (en) | 2006-09-29 | 2010-06-22 | Microsemi Corporation | Plastic surface mount large area power device |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0740600B2 (en) * | 1987-04-30 | 1995-05-01 | 三菱電機株式会社 | Semiconductor device |
| JP2641869B2 (en) * | 1987-07-24 | 1997-08-20 | 三菱電機株式会社 | Method for manufacturing semiconductor device |
| JPH01132142A (en) * | 1987-08-05 | 1989-05-24 | Mitsubishi Electric Corp | Package structure of semiconductor device |
| JPH01225328A (en) * | 1988-03-04 | 1989-09-08 | Mitsubishi Electric Corp | Semiconductor device |
| JP2651427B2 (en) * | 1988-04-22 | 1997-09-10 | 株式会社日立製作所 | Method for manufacturing semiconductor device |
| JPH0263131A (en) * | 1988-08-29 | 1990-03-02 | Mitsubishi Electric Corp | Semiconductor package |
| JPH07114215B2 (en) * | 1989-01-20 | 1995-12-06 | 富士通株式会社 | Resin mold type semiconductor device |
| JPH0810744B2 (en) * | 1989-08-28 | 1996-01-31 | 三菱電機株式会社 | Semiconductor device |
-
1990
- 1990-11-06 JP JP2298826A patent/JP2501950B2/en not_active Expired - Lifetime
-
1991
- 1991-04-08 FR FR9104257A patent/FR2668854B1/en not_active Expired - Fee Related
- 1991-09-02 DE DE4129160A patent/DE4129160C2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE4129160A1 (en) | 1992-05-07 |
| JPH04171848A (en) | 1992-06-19 |
| FR2668854B1 (en) | 1996-08-30 |
| DE4129160C2 (en) | 1996-09-05 |
| FR2668854A1 (en) | 1992-05-07 |
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