JPH0263131A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH0263131A JPH0263131A JP63214313A JP21431388A JPH0263131A JP H0263131 A JPH0263131 A JP H0263131A JP 63214313 A JP63214313 A JP 63214313A JP 21431388 A JP21431388 A JP 21431388A JP H0263131 A JPH0263131 A JP H0263131A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor
- semiconductor element
- tape
- carrier tape
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 239000002184 metal Substances 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000011888 foil Substances 0.000 claims abstract description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 239000011889 copper foil Substances 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 5
- 238000005452 bending Methods 0.000 abstract description 4
- 238000001721 transfer moulding Methods 0.000 abstract description 2
- 238000006073 displacement reaction Methods 0.000 abstract 1
- 238000007789 sealing Methods 0.000 description 11
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000012050 conventional carrier Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- LZZYPRNAOMGNLH-UHFFFAOYSA-M Cetrimonium bromide Chemical compound [Br-].CCCCCCCCCCCCCCCC[N+](C)(C)C LZZYPRNAOMGNLH-UHFFFAOYSA-M 0.000 description 1
- 241000270666 Testudines Species 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/79—Apparatus for Tape Automated Bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は銅箔パターンを表面に有するポリイミド等可
撓性絶縁フィルム（以下キャリアテープと呼ぶ）を用い
てＴＡＢ法により形成される樹脂封止形半導体装置のパ
ッケージに関するものである。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a resin sealing film formed by the TAB method using a flexible insulating film such as polyimide (hereinafter referred to as carrier tape) having a copper foil pattern on its surface. The present invention relates to a package for a shaped semiconductor device.
現在、半導体産業で主に用いられている半導体素子と外
部の間の電気的接続方法である金属細線接合法（ワイヤ
ボンディング法）に代って、ポリイミド等可撓性絶縁フ
ィルム上に設けた銅箔パターンにより、電気的接合を得
る方法ＣＴＡＢ法：Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂ
ｏｎｄｉｎｇ 法）が採用されはじめている。In place of the metal wire bonding method (wire bonding method), which is the electrical connection method between semiconductor elements and the outside that is currently mainly used in the semiconductor industry, copper wire bonding on a flexible insulating film such as polyimide CTAB method: Tape Automated B
onding method) is beginning to be adopted.
従来のＴＡＢ法について第９図（＆）（ｂ）を用いて説
明する。The conventional TAB method will be explained using FIG. 9(&)(b).
図において、（１）はキャリアテープの基材となるテー
プで、ポリイミド等の可撓性を有する絶縁材料により長
尺フィルム状に形成され、このテープ（υには以下に示
す様な穴が形成されている。（２）はテープ（１）の幅
方向中央部に穿設され、後述する半導体素子（３）が設
置される部位に相当するセンタデバイス孔（Ｃｅｎｔｅ
ｒ ｄｅｖｉａｅ ｈｏｌｅ）、（４）はテープ（１］
の幅方向側縁部分に所定間隔をおいて穿設されテープ（
１）と半導体素子（３）との接合時に粗い位置決めを行
つためノスプロケットホール（Ｓｐｒｏｃｋｅｔ ｈｏ
ｌｓ）、（５）はセンタデバイス孔（２）の周囲を取り
囲むように穿設され後述するアウターリードボンディン
グ（Ｏｕｔｅｒ １ｅａｄ Ｂｏｎｄｉｎｇ）時におい
て使用される複数のアウターリード孔（Ｏｕｃｅｒ １
ｅａｄ ｈｏｌｅ）で、このアウターリード孔（５）は
センタデバイス孔（２）の四隅部に該当する部分に形成
されている架橋部（６）を介して連設されている。（７
）はテープ（１）表面の所定箇所に形成された銅等の導
電性材料からなる複数本のリードで、センタデバイス孔
（２）内に内方端が臨むインナーリード部（７−ｍ）と
アウターリード孔（５）を介して外方に延設されたアウ
ターリード部（７−ｂ）とから構成され、また（７−ｏ
）はインナーリード（７−１）と半導体素子（３）との
接続不良半導体素子の不良等をインナーリードボンディ
ング後に調べるためのテストパッド部とで構成される。In the figure, (1) is a tape that serves as the base material of the carrier tape, and is formed into a long film shape from a flexible insulating material such as polyimide.This tape (υ) has holes as shown below. (2) is a center device hole (Cente device hole) which is bored in the center of the tape (1) in the width direction and corresponds to the part where the semiconductor element (3) described later is installed.
r deviae hole), (4) is tape (1)
The tape (
A sprocket hole is provided for rough positioning when bonding the semiconductor element (1) and the semiconductor element (3).
ls) and (5) are a plurality of outer lead holes (Outer 1) which are bored so as to surround the center device hole (2) and are used during outer lead bonding, which will be described later.
The outer lead hole (5) is connected to the center device hole (2) through bridge portions (6) formed at the four corners of the center device hole (2). (7
) is a plurality of leads made of conductive material such as copper formed at predetermined locations on the surface of the tape (1), and has an inner lead portion (7-m) whose inner end faces into the center device hole (2). The outer lead part (7-b) extends outward through the outer lead hole (5), and the outer lead part (7-o
) is composed of a test pad section for checking for poor connection between the inner lead (7-1) and the semiconductor element (3), or for defects in the semiconductor element after inner lead bonding.
＋８１はこのリード（７）のリードサポート部である。+81 is a lead support portion of this lead (7).
（９）は半導体素子（３）とインナーリード（７Ｋ）の
間に存在する突起電極（バンブ）で１通常半導体素子（
３）の表面に形成されている。(9) is a protruding electrode (bump) existing between the semiconductor element (3) and the inner lead (7K).
3) is formed on the surface.
次に、この様に構成されたキャリアテープに半導体素子
（３）を実装する方法について説明する。Next, a method of mounting the semiconductor element (3) on the carrier tape configured as described above will be explained.
先ず、第１０図（ａ）に示すテープ（１）のセンタデバ
イス孔（２）内に半導体素子（３）を置き、半導体素子
（３）上のバンブ（９）がインナーリード部（７ａ）の
所定の位置に対向するように半導体素子（３）又はキャ
リアテープを位置決めする。次に、この半導体素子（３
）のバンブ【９１とインナーリード部（７ａ）を熱圧着
することにより接続する。これにより、半導体素子（３
）を搭載したキャリアテープが形成される。そして、こ
の様にして得られたキャリアテープを第１０図（ｂ）に
示す。First, the semiconductor element (3) is placed in the center device hole (2) of the tape (1) shown in FIG. The semiconductor element (3) or the carrier tape is positioned so as to face a predetermined position. Next, this semiconductor element (3
)'s bump [91] and the inner lead part (7a) are connected by thermocompression bonding. As a result, the semiconductor element (3
) is formed. The carrier tape thus obtained is shown in FIG. 10(b).
最近、このキャリアテープを用いた半導体装置において
、第１１図（ａ）に示す様なキャリアテープと第１１図
（′ｂ）および（６）に示す様な金属キャップａＯを組
み合わせトランスファー封止により封止したパッケージ
が開発された（特願昭６２−３８５５５号）。第１１図
（ｂ）は金属キャップの平面図、第１１図（４＋）は側
面図である。第１２図はキャリアテープと金属キャップ
αＧとを組み合わせたパッケージの封止後の上面図、第
１３図は封止後の側面図である。第１４図は上記パッケ
ージの側面図で、第１２図Ａ−０−Ｂ 線で切り取った
パッケージの断面図を示す（Ａ−０は断面図）。Recently, in semiconductor devices using this carrier tape, a carrier tape as shown in FIG. 11(a) and a metal cap aO as shown in FIG. 11('b) and (6) are combined and sealed by transfer sealing. A new package was developed (Japanese Patent Application No. 62-38555). FIG. 11(b) is a plan view of the metal cap, and FIG. 11(4+) is a side view. FIG. 12 is a top view after sealing of a package in which the carrier tape and metal cap αG are combined, and FIG. 13 is a side view after sealing. FIG. 14 is a side view of the package, and shows a sectional view of the package taken along line A-0-B in FIG. 12 (A-0 is a sectional view).
図中、（ロ）は封止樹脂、（６）はダイボンド剤である
。In the figure, (b) is a sealing resin, and (6) is a die bonding agent.
従来のキャリアテープと金属キャップを組み合わせたパ
ッケージは第１３図に示す様に、上下方向（２方向）で
の構造の対称性が整合していないため１周囲の温度変化
に伴い、パッケージに反りが生じる。つまり、上下方向
（２方向）での構造を考えると、上から封止樹脂、半導
体素子、キャップの３層構造（半導体素子とキャップを
接続するグイボンド剤を含めると４層構造）になってお
り、各材質、材料の物性値が表１に示す様に異なるため
、第１４図（ａ）〜（（＋）に示す様にパッケージの温
度の違いにより反りが生ずる。第１４図ではパッケージ
封止温度を１８０℃とし、全型中、又は１８０℃で反り
が発生しないものとした。As shown in Figure 13, in a conventional package that combines a carrier tape and a metal cap, the symmetry of the structure in the vertical direction (two directions) is not consistent, so the package warps as the surrounding temperature changes. arise. In other words, when considering the structure in the vertical direction (two directions), it has a three-layer structure from the top: the sealing resin, the semiconductor element, and the cap (four-layer structure if you include the Guibond agent that connects the semiconductor element and the cap). , each material and the physical property values of the materials are different as shown in Table 1, so warping occurs due to the difference in package temperature as shown in Fig. 14 (a) to ((+). In Fig. 14, package sealing The temperature was set at 180°C, and it was assumed that no warping occurred in the entire mold or at 180°C.
上記パッケージの反りは外観的に不具合であるだけでな
く、半導体素子に応力がかかることから製品の信頼性に
も大きく影響するという問題点を有していた。The above-mentioned warpage of the package not only causes a problem in appearance, but also has a problem in that stress is applied to the semiconductor element, which greatly affects the reliability of the product.
この発明は上記のような問題点を解消するためになされ
たもので、半導体素子の裏面電位を金属細線、金属箔等
の曲げ強度の余り大きくない材質で取り、かつ半導体素
子の裏面も封止することにより、パッケージの上下方向
（２方向）での対称性を保つことにより、温度変化によ
る反りの少ない半導体パッケージを得ることを目的とす
る。This invention was made in order to solve the above-mentioned problems, and the back surface potential of the semiconductor element is taken by a material such as thin metal wire or metal foil that does not have very high bending strength, and the back surface of the semiconductor element is also sealed. By doing so, the object is to maintain the symmetry of the package in the vertical direction (two directions), thereby obtaining a semiconductor package that is less warped due to temperature changes.
この発明による半導体パッケージは第１１図、第１３図
に示す様な従来のパッケージで用いたキャップに代え、
金属細線や金属箔等の曲げ強度の余り強くない材質を用
いて半導体素子の裏面とテープを電気的に接続すると共
に、上記キャップの様にテープの裏側の全面を覆ってい
ないという特徴を生かして、半導体素子のおもての面だ
けでなく裏面をも封止樹脂により封止したものである。The semiconductor package according to the present invention replaces the cap used in conventional packages as shown in FIGS. 11 and 13.
The tape is electrically connected to the back side of the semiconductor element by using a material with low bending strength, such as thin metal wire or metal foil, and it takes advantage of the feature that it does not cover the entire back side of the tape like the cap above. , in which not only the front surface but also the back surface of the semiconductor element is sealed with a sealing resin.
この発明における半導体パッケージは金属細線や金属箔
により半導体素子の裏面とキャリアテープ表面のリード
の一部を電気的に接続すると共に、トランスファーモー
ルド法により封止する際に半導体素子の裏面をも封止し
、パッケージの上下方向（２方向）での対称性を保つこ
とにより、温度ｙ化による反りの少ない半導体パッケー
ジを得る様にする。また、従来のパッケージの反りを減
らすためキャップの裏面をも封止したパッケージと比べ
た場合、半導体の裏面とテープキャリア表面のリードの
一部を接続する材料の強度（曲げ強度）が従来のキャッ
プよりも小さいため、上記材料による半導体パッケージ
の対称性のずれの効果が小さく、従来のパッケージのキ
ャップの裏面を封止したパッケージと比べてより反りが
減少する。The semiconductor package of this invention not only electrically connects the back side of the semiconductor element and part of the leads on the surface of the carrier tape using thin metal wires or metal foil, but also seals the back side of the semiconductor element when it is sealed by transfer molding. However, by maintaining the symmetry of the package in the vertical direction (two directions), it is possible to obtain a semiconductor package that is less likely to warp due to temperature increase. In addition, when compared to a conventional package in which the back side of the cap is also sealed to reduce warpage, the strength (bending strength) of the material connecting the back side of the semiconductor and part of the leads on the tape carrier surface is lower than that of the conventional cap. Since the cap is smaller than the above, the effect of the symmetry shift of the semiconductor package due to the above material is small, and warpage is reduced more than in a conventional package in which the back side of the cap is sealed.
以下、この発明の一実施例を図について説明する。第１
図から第４図において、図中符号（１）から（２）は前
記従来のものと同一につき説明は省略する。An embodiment of the present invention will be described below with reference to the drawings. 1st
4, reference numerals (1) to (2) in the drawings are the same as those of the prior art, and therefore their explanation will be omitted.
図中、（至）は金属細線または金属箔テープで、この実
施例では金属箔テープの場合を示す。（至）はテープ（
１］のリードサポート部（８）に設けられた穴で、■は
リード（７）の一部分で上記穴（至）を通ってテープ（
１）の表面から裏面へ曲げられリードと電気的に接続し
た部分をリードの裏面に設ける働きをする接続リードで
ある。（へ）は導電性ペーストを示す。In the figure, (to) is a thin metal wire or a metal foil tape, and this example shows the case of a metal foil tape. (to) is the tape (
1] is the hole provided in the lead support part (8), and ■ is a part of the lead (7) that passes through the hole (to) and the tape (
1) This is a connection lead that is bent from the front surface to the back surface and serves to provide a portion electrically connected to the lead on the back surface of the lead. (f) indicates conductive paste.
第２図はこの発明の一実施例である金属キャップαＯの
代りに金属箔テープ（至）を用いて半導体素子（３）の
裏面とリード（７）の一部を電気的に接続した半導体パ
ッケージに用いられるキャリアテープの上面図であり、
本実施例ではテープ（１］に設けるスルーホールの代り
にテープサポート部（８１の接続リードα◆の下に穴（
財）を設け、接続リードＱ４を上記穴（至）に折り曲げ
て、リード（７）と電気的に接続された部分をテープサ
ポート部（８）のリードと反対側に設けた。第３図は第
２図に示した半導体パッケージに用いられるキャリアテ
ープの下面図である。第４図は第２図及び第３図で示し
たキャリアテープを封止した後にリードカットした半導
体パッケージであり、第１図は第４図Ａ−０−Ｂ線にお
ける一部断面を示す側面図である。FIG. 2 shows an embodiment of the present invention, a semiconductor package in which the back surface of the semiconductor element (3) and a part of the lead (7) are electrically connected using a metal foil tape instead of the metal cap αO. It is a top view of the carrier tape used for
In this embodiment, instead of the through hole provided in the tape (1), there is a hole (
The connection lead Q4 was bent into the hole (end), and the part electrically connected to the lead (7) was provided on the opposite side of the tape support part (8) from the lead. FIG. 3 is a bottom view of the carrier tape used in the semiconductor package shown in FIG. 2. FIG. 4 shows a semiconductor package in which the carrier tape shown in FIGS. 2 and 3 is sealed and leads are cut, and FIG. 1 is a side view showing a partial cross section taken along line A-0-B in FIG. 4. It is.
第２図、第３図に示したキャリアテープを用いた低圧ト
ランスファー法で封止した場合第１図に示した様に、パ
ッケージの上下方向での対称性が保たれるため、従来の
第１４図に示した様な温度変化に伴うパッケージの反り
が起こり難くなる。When sealed by the low-pressure transfer method using the carrier tape shown in Figures 2 and 3, the symmetry of the package in the vertical direction is maintained as shown in Figure 1. The package becomes less likely to warp due to temperature changes as shown in the figure.
なお、上記実施例ではキャリアテープの表裏の導通を得
るために前記の様な方法を用いた場合を示したが、キャ
リアテープの表裏の導通はスルーホールａｌｌを用いて
、テープ作成時のプロセス中に得ても良い。また、テー
プ（１］の裏面にも銅箔のパターン（ロ）を設けて上記
パターンを介して半導体素子の裏面とキャリアテープの
リード（７）を電気的に接続しても良い。In addition, in the above example, the case where the above-mentioned method was used to obtain conduction between the front and back sides of the carrier tape was shown, but the conduction between the front and back sides of the carrier tape was achieved by using through holes all during the tape production process. You can also get it. Further, a copper foil pattern (b) may be provided on the back surface of the tape (1), and the back surface of the semiconductor element and the lead (7) of the carrier tape may be electrically connected via the pattern.
第５図から＠８図は上記方法を用いたこの発明の他の実
施例を示す。第５図はこの発明の他の実施例である半導
体パッケージで用いられるキャリアテープの上面図、第
６図は第５図に示した半導体パッケージに用いられるキ
ャリアテープの下面図、第７図は第５図及び第６図で示
したキャリアテープを封止した後にリードカットした半
導体パッケージ、第８図は第７図Ａ−０−Ｂ線における
一部断面を示す側面図である。Figures 5 to 8 show other embodiments of the invention using the above method. FIG. 5 is a top view of a carrier tape used in a semiconductor package according to another embodiment of the present invention, FIG. 6 is a bottom view of a carrier tape used in a semiconductor package shown in FIG. 5, and FIG. FIG. 8 is a side view showing a partial cross section taken along the line A-0-B in FIG. 7, showing the semiconductor package shown in FIGS. 5 and 6 in which leads are cut after sealing with the carrier tape.
図中、ａユはスルーホール、（ロ）は裏面パターンであ
る。In the figure, ayu is a through hole, and (b) is a backside pattern.
を記この発明の他の実施例である半導体パッケージは前
記この発明の一実施例と同様の効果がある。A semiconductor package according to another embodiment of the present invention has the same effects as the above embodiment of the present invention.
以上のようにこの発明によれば、半導体素子の裏面に電
気的に接続する部分の形状を金属細線又は金属箔状にし
たので、従来のパッケージ又は従来のパッケージの裏面
をも封止したパッケージに比べ、温度変化に伴うパッケ
ージの反りを少なくできる。As described above, according to the present invention, the shape of the part electrically connected to the back surface of the semiconductor element is made into a metal thin wire or metal foil shape, so that it can be used as a conventional package or a package that also seals the back surface of the conventional package. In comparison, package warpage due to temperature changes can be reduced.
第１図（ａ） （ｂ）は仁の発明の一実施例である半導
体パッケージの部分断面側面図およびｂ部拡大断面図、
第２図はこの発明の一実施例である半導体パッケージの
１面図、第３図は第２図の下面図、第４図は第２図、第
３図で示したキャリアテープを封止した後リードカット
した状態の半導体パッケージの上面図、第５図はこの発
明の他の実施例である半導体パッケージで用いたキャリ
アテープの上面図、第６図は第５図の半導体パッケージ
の下面図、第７図は第５図、第６図で示したキャリアテ
ープを封止した後リードカットしたこの発明の他の実施
例である半導体パッケージの上面図、第８図は第７図の
Ａ−０−Ｂ線における部分断面側面図、Ｉ！９図（１ｍ
） （ｂ）は従来のキャリアテープを示す半導体パッケ
ージの・上面図およびその断面図、第１０図はキャリア
テープと半導体素子を接合してキャリアテープを作成す
るプロセスを説明したそれぞれ斜視図、第１１図（亀）
はキャリアテープに金属キャップを接続し、半導体素子
の裏面とキャリアテープのリードの一部を電気的に接続
し、半導体素子の裏面電位を一定にする等の必要がある
半導体素子にもＴＡＢ技術を適用させた従来のキャリア
テープの上面図、第１１図（ｂ） （（＋）は第１１図
（ａ）の金属キャップの上面図および側面図、第１２図
は第１１図のキャリアテープと金属キャップを接続して
作成したテープキャリアを封止した後リードカットした
従来のパッケージの上面図で、第１３図は第１２図のＡ
−０−Ｂ線における半導体パッケージの部分断面側面図
、第１４図（ａ）〜（（＋）は従来の半導体パッケージ
の温度変化による反りの発生状態を説明した部分断面側
面図である。
図中、（１）はキャリアテープ、（２）はセンタデバイ
ス孔、（３）は半導体素子％（４）はスプロケットホー
ル、（５１はアウターリード孔、（６）は架橋部％（７
）はリード、（７ａ）はインナーリード、 （７ｂ）Ｇ
！７ウター１１−）’、（７６）はテストパッド、（８
１はリードサポート部、（９）はバンブ、αＧは金属キ
ャップ、（ロ）は封止樹脂、（２）はグイボンド剤、（
至）は金属箔テープ、Ｑ４は接続リード、（ト）は導電
性ペースト、ａ・はスルーホール、ｏｎは裏面パターン
％（至）はサポートテープに開けた穴である。
なお、図中、同一符号は同一、又は相当部分を示す。
ｔｌ、’ ｆｒ−） ？−７’＋＝ １９げｒ：フ′
ム第４図
第６図
１／、°ズルー不−１し
ｌ７．°裏面ハ・７−〉
第７図
ｌ
第９図
口
口
口
口
４、スフ１０ケットホール
（Ｃ）
ｆ０1(a) and 1(b) are a partial cross-sectional side view and an enlarged cross-sectional view of part b of a semiconductor package which is an embodiment of Jin's invention,
Fig. 2 is a front view of a semiconductor package which is an embodiment of the present invention, Fig. 3 is a bottom view of Fig. 2, and Fig. 4 is a sealing of the carrier tape shown in Figs. 2 and 3. 5 is a top view of a carrier tape used in a semiconductor package according to another embodiment of the present invention; FIG. 6 is a bottom view of the semiconductor package of FIG. 5; FIG. 7 is a top view of a semiconductor package which is another embodiment of the present invention in which the carrier tape shown in FIGS. 5 and 6 is sealed and the leads are cut, and FIG. 8 is a top view of a semiconductor package shown in FIG. - Partial cross-sectional side view at line B, I! Figure 9 (1m
) (b) is a top view and a cross-sectional view of a semiconductor package showing a conventional carrier tape; FIG. 10 is a perspective view illustrating the process of bonding a carrier tape and a semiconductor element to create a carrier tape; Figure (turtle)
TAB technology can also be applied to semiconductor devices that require a metal cap to be connected to the carrier tape, electrically connecting the back side of the semiconductor device to a portion of the leads of the carrier tape, and maintaining a constant potential on the back side of the semiconductor device. A top view of the conventional carrier tape applied, FIG. 11(b) ((+) is a top view and a side view of the metal cap in FIG. 11(a), and FIG. 12 is the carrier tape and metal cap in FIG. 11. Figure 13 is a top view of a conventional package in which the tape carrier made by connecting a cap is sealed and the leads are cut.
A partial cross-sectional side view of a semiconductor package taken along the line -0-B, and FIGS. 14(a) to ((+) are partial cross-sectional side views illustrating how warpage occurs due to temperature changes in a conventional semiconductor package. , (1) is the carrier tape, (2) is the center device hole, (3) is the semiconductor element% (4) is the sprocket hole, (51 is the outer lead hole, (6) is the bridge portion% (7)
) is lead, (7a) is inner lead, (7b) G
! 7 outer 11-)', (76) is the test pad, (8
1 is a lead support part, (9) is a bump, αG is a metal cap, (B) is a sealing resin, (2) is a Guibond agent, (
(to) is a metal foil tape, Q4 is a connection lead, (g) is a conductive paste, a/ is a through hole, on is a back pattern % (to) is a hole made in the support tape. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. tl,' fr-)? -7'+=19ger:fu'
Figure 4, Figure 6, Figure 1/, °Zero error, 17. °Back side C・7-> Figure 7 l Figure 9 Mouth Mouth Mouth 4, Sufu 10 socket hole (C) f0
Claims (1)
ターンを設けたキャリアテープの一部にスルーホール又
は相当の機能を持つ部分を設け、上記銅箔パターンの一
部と電気的に接続された部分を上記銅箔パターンの反対
側に作成し、キャリアテープと半導体素子を接続した後
に、金属細線・金属箔等導電性材料により半導体素子の
裏面と上記銅箔パターンの反対側に作成した部分とを電
気的に接続することにより、半導体素子の裏面とキャリ
アテープ上の銅箔パターンとを電気的に接続することを
特徴とする半導体パッケージ。(1) A through hole or a part with a corresponding function is provided in a part of the carrier tape with a copper foil pattern used in a semiconductor device using the TAB method, and it is electrically connected to a part of the copper foil pattern. A part is created on the opposite side of the copper foil pattern, and after connecting the carrier tape and the semiconductor element, a part is created on the back side of the semiconductor element and the opposite side of the copper foil pattern using a conductive material such as thin metal wire or metal foil. A semiconductor package characterized in that the back surface of a semiconductor element and a copper foil pattern on a carrier tape are electrically connected by electrically connecting them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63214313A JPH0263131A (en) | 1988-08-29 | 1988-08-29 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63214313A JPH0263131A (en) | 1988-08-29 | 1988-08-29 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0263131A true JPH0263131A (en) | 1990-03-02 |
Family
ID=16653681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63214313A Pending JPH0263131A (en) | 1988-08-29 | 1988-08-29 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0263131A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2668854A1 (en) * | 1990-11-06 | 1992-05-07 | Mitsubishi Electric Corp | SEMICONDUCTOR DEVICE CONDITIONED IN THE RESIN. |
-
1988
- 1988-08-29 JP JP63214313A patent/JPH0263131A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2668854A1 (en) * | 1990-11-06 | 1992-05-07 | Mitsubishi Electric Corp | SEMICONDUCTOR DEVICE CONDITIONED IN THE RESIN. |
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