JPS6151948A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPS6151948A JPS6151948A JP59174378A JP17437884A JPS6151948A JP S6151948 A JPS6151948 A JP S6151948A JP 59174378 A JP59174378 A JP 59174378A JP 17437884 A JP17437884 A JP 17437884A JP S6151948 A JPS6151948 A JP S6151948A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- resin
- resin mold
- mold layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は樹脂封止型半導体装置、特にピン・グリッド・
アレイ（Ｐｉｎ Ｇｒｉｄ Ａｒｒａｙ：以下ＰＧ
Ａと略す）タイプの外囲器構造をもった樹脂封止型半導
体装置に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a resin-sealed semiconductor device, particularly a pin/grid/
Array (Pin Grid Array: hereinafter referred to as PG)
This invention relates to a resin-sealed semiconductor device having a type of envelope structure (abbreviated as A).
（発明の技術的音頭）
高密度実装か可能な半導体装置として、第２図（Ａ）（
Ｂ）に示すＰＧＡタイプの外囲器にパッケージされたし
のが知られている。同図（Ａ＞は断面図、同図（［３）
は裏面図である。(Technical introduction of the invention) As a semiconductor device capable of high-density packaging, as shown in Fig. 2 (A) (
It is known that the resin is packaged in a PGA type envelope shown in B). The same figure (A> is a sectional view, the same figure ([3)
is a back view.
これらの図に、１３いて、１はセラミック製の筺体であ
る。該筺）本には凹部が形成されてあり、この凹部底面
には半導体チップ２かダイボンデインクされ、開口部は
金属製の蓋体３でハーメデックシールされている。また
、セラミック筐体１にはメタライス層による配線パター
ン４が形成されている。該配線パターン４の一端部は、
ボンディングワイヤを介して半導体ペレット表面の内部
端子に接続されている。また、配線パターン４の他端部
はセラミック筺体１の裏面に導き出され、露出されてい
る。この露出部分には、外部引出し電極としてリードピ
ン５・・・がロウ付けされている。なお、第２図（８）
に示すように、これらのリードピン５・・・はセラミッ
ク筺体１のＴ面周、縁部に所定間隔で設けられ、洛子状
のピン配置になっているところからＰＧＡタイプと称さ
れているく以下、上記１ノη釆のＰＧＡパッケージをセ
ラミックＰＧＡと呼ぶことにする）。In these figures, 13 and 1 are ceramic casings. A recess is formed in the case, a semiconductor chip 2 is die-bonded on the bottom of the recess, and the opening is hermetically sealed with a metal lid 3. Further, a wiring pattern 4 made of a metal rice layer is formed on the ceramic casing 1. One end of the wiring pattern 4 is
It is connected to an internal terminal on the surface of the semiconductor pellet via a bonding wire. Further, the other end of the wiring pattern 4 is led out to the back surface of the ceramic casing 1 and exposed. Lead pins 5 are brazed to this exposed portion as external extraction electrodes. In addition, Figure 2 (8)
As shown in , these lead pins 5 are provided at predetermined intervals on the circumference and edge of the T surface of the ceramic casing 1, and are called PGA type because of their lozenge-shaped pin arrangement. (Hereinafter, the PGA package of the above-mentioned No. 1 type will be referred to as a ceramic PGA).
上記のセラミックＰＧＡは、多層あるいは単層のセラミ
ック仮にタングステン、モリブデン等の全屈を印刷し、
焼成して所要のリードパターンを形成した後、リードピ
ンをロウ接合したものである。The above ceramic PGA is made by printing a multi-layer or single-layer ceramic material such as tungsten or molybdenum.
After firing to form the required lead pattern, the lead pins are soldered together.
（背狽技術の問題点）
上記従来のセラミックＰＧＡは通常アルミナ・セラミッ
クを焼成して作製され、その製造には多くの複雑な工程
が必要とされる。しかも、これらの工程の中に１，１高
温でのロウ接合作業等の自動化の困難な工程が多いｌζ
め、大ｍ生産することが難しく、パッケージのコストは
田脂封止型半導体装置に比較して５１８以上の高価もの
となる欠点があった。(Problems with backlash technology) The conventional ceramic PGA described above is usually produced by firing alumina ceramic, and its manufacture requires many complicated steps. Moreover, many of these processes are difficult to automate, such as brazing work at high temperatures.
Therefore, it is difficult to produce in large quantities, and the cost of the package is 518 times higher than that of a resin-sealed semiconductor device.
また、リードフレームを用いて’８１ ＦＢする・田脂
月止型パッケージの場合には１フレームに復数個の半導
体装置を作製し、後で分離するといった多数個取りの製
造方法が可能であるのに対して、セラミックＰＧＡの製
）青では１個づつ取ｊ及わざるを１ｑないという問題が
ある。この問題もセラミックＰＧＡ製造工程の自動化を
？’Ｊ ２ｆｔにし、半導体装置の組立製造コストを８
価なものにする原因となっている。In addition, in the case of '81 FB using a lead frame, a multi-chip manufacturing method in which several semiconductor devices are manufactured in one frame and separated later is possible. On the other hand, with ceramic PGA (blue), there is a problem in that each one has to be taken out. Is this problem also about automation of the ceramic PGA manufacturing process? 'J 2ft, reducing the assembly manufacturing cost of semiconductor devices by 8.
This is what makes it expensive.
〔発明の目的）
本発明は上記＄１青に鑑みてなされたもので、ＰＧＡタ
イプのピン配置が可能な樹脂封止パッケージによる半導
体装置を提供し、リードフレームを用いた複数個取りの
製造方法および！Ｂｌ造工程の自動化を可能とし、ＰＧ
Ａパッケージによる半導体装置のパッケージコスト低減
を図ることを目的とするものである。[Object of the Invention] The present invention has been made in view of the above-mentioned $1 blue, and provides a semiconductor device with a resin-sealed package that allows PGA type pin arrangement, and a manufacturing method of multiple devices using a lead frame. and! Enables automation of Bl manufacturing process, and PG
The purpose of this is to reduce the packaging cost of semiconductor devices using the A package.
本発明（こよる樹脂封止型半導体装置は、金属製のダイ
パッド部上に固着された半導体ペレットと、該半導体ペ
レットの周囲に前記ダイパッドｇから離間して一端部を
配置すると共に、前記ダイバンド部に略平行に外方に向
けて延設された金泥製の内部リードと、該内部リードの
一端部と前記半導体ペレット表面に形成されている内部
端子とを接続するポジディングワイヤと、該ボンディン
グワイヤ、前記内部リード、前記半導体ペレット及び前
記ダイパッド部を封止する樹脂モールド層と、該樹脂モ
ルド層の頂面および裏面の片面または両面から前記内部
リードに達して穿設されたピン穴と、該ピン穴内に嵌入
さ札て前記内部リードに接続され、且つ前記１ｂ１脂モ
一ルド層の頂面または裏面から外方に突出させて設置）
られたリードピンとを具備したことを特徴とするもので
ある。The present invention (resin-sealed semiconductor device according to the present invention) includes a semiconductor pellet fixed on a metal die pad portion, one end portion of which is disposed around the semiconductor pellet at a distance from the die pad g, and the die band portion an internal lead made of gold clay that extends outward substantially parallel to the surface of the semiconductor pellet; a posiding wire that connects one end of the internal lead to an internal terminal formed on the surface of the semiconductor pellet; and the bonding wire. , a resin mold layer that seals the internal leads, the semiconductor pellet, and the die pad portion; pin holes formed to reach the internal leads from one or both sides of the top and bottom surfaces of the resin mold layer; (inserted into a pin hole and connected to the internal lead, and protruded outward from the top or back surface of the 1b1 fat mold layer)
The device is characterized in that it is equipped with a lead pin.
上記溝成からなる樹脂封止型半導体装置は、内部リード
及びピン穴を所定の配置とすることにより、リードピン
の配置をＰＧＡタイプとすることができる。In the resin-sealed semiconductor device having the groove structure, the lead pins can be arranged in a PGA type by arranging the internal leads and pin holes in a predetermined manner.
しかも、上記リードピンの構造および内部リードが樹脂
モールド層側壁からそのまま外部リードとして延出され
ていないことを除けば、本発明の樹脂封止型半導体装置
は通常の樹脂封止型半導体装置と同様の（ｊ１１造を有
しているから、リードフレームを用いた複数個取りによ
る製造方法や製造工程の自動化等による大ｍ生産が可能
となる。且つ、パッケージ材わ１である樹脂がセラミッ
クに比較して大幅に安価で０ることも寄与する結果、セ
ラミックＰＧＡのらのに比較して著しく址画なＰＧＡパ
ッケージの半導体装置を冑ることが可能となる。Moreover, except for the structure of the lead pins and the fact that the internal leads do not directly extend from the side wall of the resin mold layer as external leads, the resin-sealed semiconductor device of the present invention is similar to a normal resin-sealed semiconductor device. (Since it has a J11 structure, large-scale production is possible through a manufacturing method using multiple pieces using a lead frame and automation of the manufacturing process.In addition, the resin used as the packaging material is less expensive than ceramic. As a result, it is possible to manufacture a semiconductor device in a PGA package, which is significantly more compact than a ceramic PGA.
第１図（Ａ）は本発明の一実施例になる樹脂封止型半導
体装置を示す断面図であり、同図（Ｂ）はその裏面図で
ある。これらの図において、１１は金属製の薄板からな
るダーｒパッドで、該ダイパッド上には導電性接着剤層
１２を介してＩＣ等の半導体ペレット１３がマウントさ
れている。該半導体ベレン１〜１３の周囲には、全屈製
薄板からなる内部リード１４・・・が前記ダイパッド１
１に略平行に配設されている。これら内部リード１４・
・・の夫々は、ボンディングワイヤ１５を介して前記半
導体ペレット１３の表面に形成された内部端子（ポンデ
ィングパッド）に接続されている。そして、上記のよう
にして組立てられた前記ダイパッド１１、半導体ベレン
１〜１３、内部リード１４・・・、ボンディングワイヤ
・・・１５を封止する樹脂モールド膚１６が形成されて
いる。該樹脂モールド膚１６には、その頂面から裏面に
至って貫通したピン孔が各内部リード１４・・・に対応
して形成されており、該ピン孔は内部リード部分１４を
も貫通して形成されている。これらのピン孔には夫々リ
ードピン１７か１５（脂モールド層１６の頂面側から打
込んで嵌入され、内部リード１４に接続された状［県で
樹脂モールド層］６の裏面から突出されている。FIG. 1(A) is a sectional view showing a resin-sealed semiconductor device according to an embodiment of the present invention, and FIG. 1(B) is a back view thereof. In these figures, reference numeral 11 denotes a die pad made of a thin metal plate, and a semiconductor pellet 13 such as an IC is mounted on the die pad via a conductive adhesive layer 12. Around the semiconductor bellens 1 to 13, internal leads 14 made of fully bent thin plates are connected to the die pad 1.
1 and is arranged substantially parallel to 1. These internal leads 14.
... are connected to internal terminals (bonding pads) formed on the surface of the semiconductor pellet 13 via bonding wires 15. Then, a resin mold skin 16 is formed to seal the die pad 11, the semiconductor beads 1 to 13, the internal leads 14, and the bonding wires 15 assembled as described above. A pin hole penetrating from the top surface to the back surface of the resin mold skin 16 is formed corresponding to each internal lead 14, and the pin hole is formed to also penetrate the internal lead portion 14. has been done. Lead pins 17 or 15 (driven into the top side of the resin mold layer 16 and fitted into these pin holes, respectively) are connected to the internal leads 14 and protrude from the back surface of the resin mold layer 6. .
こうして樹脂し一ルド層１６の裏面から突出さ机たリー
ドピン１７・・・は、第１図（Ｂ）に示すようにＰＧＡ
タイプに配置されている。The lead pins 17, which are made of resin and protrude from the back surface of the lead layer 16, are PGA
placed in type.
上記実施例になる（在り脂月止型半導体装置は、第３図
（Ａ）に示すようなリードフレーム２ｏを用いて製造す
ることができる。このリードフレーム２０は金泥製の薄
板を所定のパターン形状に加工したもので、グイパッド
部およびリードパターンが外枠２１に連結されている。The above-mentioned embodiment can be manufactured by using a lead frame 2o as shown in FIG. 3(A). It is processed into a shape, and the lead pad portion and lead pattern are connected to the outer frame 21.
また、内部リード１４となるリード部分のリードピンを
打込む位置にはピン孔が穿設されてあり、この点を除け
ば通常のフラットパッケージ用リードフレームに類似し
た形状を有している。Further, a pin hole is provided at a position where a lead pin is driven into the lead portion that will become the internal lead 14, and except for this point, the lead frame has a shape similar to a normal lead frame for a flat package.
上記リードフレーム２０を用いて第１図＜Ａ）（Ｂ）の
実施例になる樹脂封止型半導体装置を製造する方法につ
いて説明すると、まず、通常の樹脂封止型半弓１ホ装置
を１川造する場合と同様、ダイパッド部上に半導体ペレ
ット１３をマウントした後、ワイヤボンディングを行な
う。続いてエポキシ樹脂等の封止樹脂によるトランスフ
ァーモールドを行ない、第３図（Ｂ）に示すように所定
の領域を樹脂モールド層１６で封止する。その際、図示
のように樹脂モールド層１６にはピン孔１８・・・を形
成する。これは、そのようなモールド金型を用いること
で容易に形成することができる。To explain the method of manufacturing the resin-sealed semiconductor device according to the embodiment of FIGS. As in the case of manufacturing, wire bonding is performed after mounting the semiconductor pellet 13 on the die pad portion. Subsequently, transfer molding is performed using a sealing resin such as epoxy resin, and a predetermined area is sealed with a resin mold layer 16 as shown in FIG. 3(B). At that time, pin holes 18 are formed in the resin mold layer 16 as shown in the figure. This can be easily formed using such a mold.
次いで、リードフレームの各リードパターンを樹脂モー
ルド層１６の側壁に沿って切断する。第３図（Ｃ）はこ
の状態を示す断面図である。Next, each lead pattern of the lead frame is cut along the side wall of the resin mold layer 16. FIG. 3(C) is a sectional view showing this state.
その後、樹脂モールド届１６に形成されているピン孔１
８・・・の上方開口部から外部リードピン１７・・・を
打込むことにより、第１図（Ａ）（Ｂ）の（を造を有す
るＰＧＡタイプの樹脂封止型半導体装置が１３られる。After that, the pin hole 1 formed in the resin mold report 16 is
A PGA type resin-sealed semiconductor device 13 having the structure shown in Figs.
このように、上記実施例に示したＰＧＡタイプの樹脂封
止型半導体装置はパッケージ材料が従来のセラミックＰ
Ｇ△に比較して極めて安価であるのみならず、例えばＤ
ＩＲパッケージのような通常の樹脂封止型半導体装置の
場合と同様、リードフレームを用いた多数個取り方式を
採用し、且つ製造工程を自動化して人里生産することが
できる。In this way, the PGA type resin-sealed semiconductor device shown in the above embodiment uses the conventional ceramic P as the package material.
Not only is it extremely cheap compared to G△, but also, for example, D
As in the case of ordinary resin-sealed semiconductor devices such as IR packages, a multi-piece manufacturing method using a lead frame is adopted, and the manufacturing process is automated to enable manual production.
従って、ＰＧＡタイプの外囲器コストを大幅に低減する
ことが可能となる。Therefore, it is possible to significantly reduce the cost of the PGA type envelope.
なあ、上記第１図の実施例では外部リードピン１７・・
・が樹脂モールド層１６を厚さ方向に貫通して設けられ
ているが、この外部リードピン１７・・・は樹脂モール
ドｆＶＪ１６の裏面側から内部リード１４に達してに入
するようにしてもよい。第３図＜Ａ）（Ｂ）ｉ；Ｌこの
ような実施例とその製造方法を説明するための図である
。同図（Ａ）に示すように、この実施例では樹脂モール
ド工程を行なう際、樹脂モールド層１６の裏面から各内
部リード１４に達するピン孔１８′を形成する。そして
、樹脂モールド層１６の裏面からこのピン孔１８′内に
外部リード１７を嵌入し、内部リード１４（〔接続させ
る。これにより、同図（ＩＥ３）に示すＰＧＡタイプの
樹脂封止型半導体装置が１０られる。By the way, in the embodiment shown in FIG. 1 above, the external lead pin 17...
* are provided to penetrate the resin mold layer 16 in the thickness direction, but the external lead pins 17 may be inserted by reaching the internal leads 14 from the back side of the resin mold fVJ16. FIG. 3<A)(B)i;L FIG. 3 is a diagram for explaining such an embodiment and its manufacturing method. As shown in FIG. 2A, in this embodiment, pin holes 18' reaching each internal lead 14 are formed from the back surface of the resin mold layer 16 during the resin molding process. Then, the external lead 17 is fitted into this pin hole 18' from the back surface of the resin mold layer 16, and the internal lead 14 ([connected] is formed. is given 10.
この第４図（Ａ＞（Ｂ）の実施例でも基本的には第１図
の実施例と同じ効果を（与ることができる。The embodiment shown in FIG. 4 (A>(B) can also basically provide the same effect as the embodiment shown in FIG. 1.
なお、この第４図（Ａ＞（Ｂ）の実施例の場合。In addition, in the case of this embodiment of FIG. 4 (A>(B)).
外部リードピン１７と内部リード１４との間に導電ｉ１
接着剤を介して固着するようにするのが望ましい。また
、この実Ｍ例に用いるリードフレームでは、その内部リ
ード部にピン孔を穿設する必要がない。Conductive i1 between external lead pin 17 and internal lead 14
It is preferable to fix it using an adhesive. Further, in the lead frame used in this practical example, there is no need to drill pin holes in the internal lead portion.
（発明の効果）
以上詳述したように、本発明によればＰＧＡタイプのピ
ン配置が可能な樹脂封止パッケージによる半導体装置を
提供でき、リードフレームを用いた複数個取りの製造方
法および製造工（呈の自動化によってＰＧΔパッケージ
による半導体装置のパッケージコストの大幅な低ばか可
能となる等、顕著な効果が僻られるものである。(Effects of the Invention) As described in detail above, according to the present invention, it is possible to provide a semiconductor device with a resin-sealed package that allows PGA type pin arrangement, and a method and process for manufacturing multiple pieces using a lead frame. (Automation of the display will bring about significant effects, such as a significant reduction in the packaging cost of semiconductor devices using the PGΔ package.
第１図（Ａ）は本発明の一実施例になる樹脂封止型半導
体装置を示す断面図であり、同図（Ｂ）はその裏面図、
第２図（Ａ）は従来のセラミックＰＧＡパッケージによ
る半導体装置を示す断面図であり、同図（Ｂ）はその裏
面図、第３図（Ａｌｌは第１図（Δ）（Ｂ）の樹脂封止
型半導体装置を製造する際に用いるリードフレームの一
１列を示す平面図であり、同図（Ｂ）（Ｃ）はその製造
工程を示す説明図、第４図（Ａ＞（Ｂ）は本発明の他の
実施例になる（ム（脂封止型半導体装置とその製造方法
を説明するための断面図である。
１１・・・ダイパッド、１２・・・導電性後管剤層、１
３・・・半導体ベレッｌ−１１４・・・内部リード、１
５・・・ボンディングワイヤ、１６・・・樹脂モールド
居、１７・・・外部リードピン、１８．１８’・・・ピ
ン孔、２０・・・リードフレーム、２１・・・外枠。
出願人代理人 弁理士 鈴江武彦
（〕
＼Ｔ ＼ＪFIG. 1(A) is a sectional view showing a resin-sealed semiconductor device according to an embodiment of the present invention, and FIG. 1(B) is a back view thereof,
FIG. 2(A) is a cross-sectional view showing a semiconductor device using a conventional ceramic PGA package, FIG. 2(B) is a back view thereof, and FIG. 4 is a plan view showing 11 rows of lead frames used when manufacturing a static semiconductor device; FIGS. 4(B) and 4(C) are explanatory diagrams showing the manufacturing process; 11 is a cross-sectional view for explaining a fat-sealed semiconductor device and its manufacturing method. 11... Die pad, 12... Conductive back tube material layer, 1
3...Semiconductor bellet l-114...Internal lead, 1
5... Bonding wire, 16... Resin molding, 17... External lead pin, 18.18'... Pin hole, 20... Lead frame, 21... Outer frame. Applicant's agent Patent attorney Takehiko Suzue (〕 ＼T ＼J
Claims (3)
ットと、該半導体ペレットの周囲に前記ダイパッド部か
ら離間して一端部を配置すると共に、前記ダイパッド部
に略平行に外方に向けて延設された金属製の内部リード
と、該内部リードの一端部と前記半導体ペレット表面に
形成されている内部端子とを接続するボンディングワイ
ヤと、該ボンディングワイヤ、前記内部リード、前記半
導体ペレット及び前記ダイパッド部を封止する樹脂モー
ルド層と、該樹脂モルド層の頂面および裏面の片面また
は両面から前記内部リードに達して穿設されたピン穴と
、該ピン穴内に嵌入されて前記内部リードに接続され、
且つ前記樹脂モールド層の頂面または裏面から外方に突
出させて設けられたリードピンとを具備したことを特徴
とする樹脂封止型半導体装置。(1) A semiconductor pellet fixed on a metal die pad, one end disposed around the semiconductor pellet apart from the die pad, and extending outward approximately parallel to the die pad. a bonding wire connecting one end of the internal lead to an internal terminal formed on the surface of the semiconductor pellet; the bonding wire, the internal lead, the semiconductor pellet, and the die pad; a resin mold layer for sealing the resin mold layer; a pin hole drilled from one or both of the top and bottom surfaces of the resin mold layer to reach the internal lead; and a pin hole inserted into the pin hole and connected to the internal lead. is,
A resin-sealed semiconductor device further comprising a lead pin provided to protrude outward from the top surface or the back surface of the resin mold layer.
亙つて貫通して設けられていることを特徴とする特許請
求の範囲第１項記載の樹脂封止型半導体装置。(2) The resin-sealed semiconductor device according to claim 1, wherein the lead pin is provided to penetrate the entire thickness of the resin mold layer.
前記内部リードに達して嵌入されていることを特徴とす
る特許請求の範囲第１項記載の樹脂封止型半導体装置。(3) The resin-sealed semiconductor device according to claim 1, wherein the lead pin reaches the internal lead from one side of the resin mold layer and is fitted therein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59174378A JPS6151948A (en) | 1984-08-22 | 1984-08-22 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59174378A JPS6151948A (en) | 1984-08-22 | 1984-08-22 | Resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6151948A true JPS6151948A (en) | 1986-03-14 |
Family
ID=15977563
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59174378A Pending JPS6151948A (en) | 1984-08-22 | 1984-08-22 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6151948A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5726493A (en) * | 1994-06-13 | 1998-03-10 | Fujitsu Limited | Semiconductor device and semiconductor device unit having ball-grid-array type package structure |
| EP3933896A1 (en) * | 2020-06-29 | 2022-01-05 | Infineon Technologies Austria AG | Power module with metal substrate |
-
1984
- 1984-08-22 JP JP59174378A patent/JPS6151948A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5726493A (en) * | 1994-06-13 | 1998-03-10 | Fujitsu Limited | Semiconductor device and semiconductor device unit having ball-grid-array type package structure |
| EP3933896A1 (en) * | 2020-06-29 | 2022-01-05 | Infineon Technologies Austria AG | Power module with metal substrate |
| US11404336B2 (en) | 2020-06-29 | 2022-08-02 | Infineon Technologies Austria Ag | Power module with metal substrate |
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