JPH1074795A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH1074795A
JPH1074795A JP8228917A JP22891796A JPH1074795A JP H1074795 A JPH1074795 A JP H1074795A JP 8228917 A JP8228917 A JP 8228917A JP 22891796 A JP22891796 A JP 22891796A JP H1074795 A JPH1074795 A JP H1074795A
Authority
JP
Japan
Prior art keywords
wiring
ground
hole
semiconductor chip
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8228917A
Other languages
Japanese (ja)
Other versions
JP2825084B2 (en
Inventor
Michitaka Urushima
路高 漆島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8228917A priority Critical patent/JP2825084B2/en
Priority to US08/921,145 priority patent/US6046495A/en
Publication of JPH1074795A publication Critical patent/JPH1074795A/en
Application granted granted Critical
Publication of JP2825084B2 publication Critical patent/JP2825084B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/645Inductive arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985Flexible insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors

Abstract

PROBLEM TO BE SOLVED: To improve the electric characteristic of the grounding wiring of a package and to reduce the manufacturing cost of the wiring by reducing the length of the wiring and, at the same time, to improve the heat radiating property of the wiring by radiating the heat generated form the wiring to a printed board. SOLUTION: ATAEI (tape automated bonding) tape carrying a ground layer 3 connected to a grounding conductor is provided in the device hole l of a base film 4 and a resin sealing hole 28 is provided at the center of the layer 3 for fixing a semiconductor chip 2 and the base film 4. Then a package in which ground wiring 8 is connected to a ground pad electrode 13 is sealed with a resin 6. The inductance of the wiring 8 is reduced and the heat radiating property of the wiring 8 is improved by shorting the length of the wiring 8 by forming the wiring 8 in the chip 2 by cutting the package after heat radiating and grourlding bumps 5 are formed in a hole f6rmed in the cover resist 9 of the ground layer 3 and arranging and sticking each cut package on and to a mounting substrate.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置およびそ
の製造方法に関し、特にTABテープを用いてバンプに
より基板に実装された半導体装置およびその製造方法に
関する。
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device mounted on a substrate by bumps using a TAB tape and a method of manufacturing the same.

【0002】[0002]

【従来の技術】従来のこの種の半導体装置としては、本
発明者の提案した特開平8―31869号公報に記載し
たものがある。この半導体装置は、図3に示すように、
ポリイミド等の絶縁性ベースフィルム4に半導体チップ
2を固定することにより製作される。具体的には、ベー
スフィルム4の幅方向の両側に、このベースフィルム4
を搬送し、位置決めするためのスプロケットホール15
が設けられており、このスプロケットホール15を利用
してベースフィルム4をその長手方向に移送することが
できる。またベースフィルム4には、半導体チップ2を
位置ずけるための開口部、すなわちデバイスホール1が
その内側に設けられ、このデバイスホール1の外側には
カットホール16が形成されている。
2. Description of the Related Art A conventional semiconductor device of this type is disclosed in Japanese Patent Application Laid-Open No. 8-31869 proposed by the present inventors. This semiconductor device, as shown in FIG.
It is manufactured by fixing the semiconductor chip 2 to an insulating base film 4 such as polyimide. Specifically, the base film 4 is provided on both sides in the width direction of the base film 4.
Sprocket hole 15 for conveying and positioning
The base film 4 can be transported in the longitudinal direction by using the sprocket holes 15. An opening for positioning the semiconductor chip 2, that is, a device hole 1 is provided inside the base film 4, and a cut hole 16 is formed outside the device hole 1.

【0003】このデバイスホール1とカットホール16
との間のベースフィルム4上には区画されたランド17
が形成されており、半導体チップ2と電気的に接続した
インナリード18に配線されている。またランド17上
には、外部接続電極部材として半田などにより形成され
たボール状のバンプ10が形成されている。
The device hole 1 and the cut hole 16
Land 17 on base film 4 between
Are formed, and are wired to the inner leads 18 electrically connected to the semiconductor chip 2. On the land 17, a ball-shaped bump 10 formed of solder or the like is formed as an external connection electrode member.

【0004】また図の破線で示すように、バンプ10以
外の区画された周辺領域はカバーレジスト9により被覆
されており、このカバーレジスト9によってインナリー
ド18等が汚染されるのを防止している。なお半導体チ
ップ2はその周辺部のインナリード18と共に樹脂封止
される。最終的には、ベースフィルム4をカットホール
16の部分から切り取ることにより、半導体チップ2と
ベースフィルム部材とからなる半導体装置を構成するこ
とができる。
As shown by the broken lines in the figure, the peripheral region defined other than the bumps 10 is covered with a cover resist 9 to prevent the inner leads 18 and the like from being contaminated by the cover resist 9. . Note that the semiconductor chip 2 is resin-sealed together with the inner leads 18 at the periphery thereof. Finally, by cutting the base film 4 from the cut hole 16, a semiconductor device including the semiconductor chip 2 and the base film member can be formed.

【0005】この構成の半導体装置は、ランド17の上
のバンプ10が直接プリント基板20に実装することが
できるため、実質的にベースフィルム部材をパッケージ
部に使用できる。従ってセラミックパッケージ等からな
る半導体装置に比べて安価となる利点がある。またイン
ナリード18の配線領域をカットホール16の内部だけ
に限定できるため、小形化にためにも有利である。
In the semiconductor device having this configuration, since the bumps 10 on the lands 17 can be directly mounted on the printed circuit board 20, a base film member can be substantially used for the package portion. Therefore, there is an advantage that the cost is lower than that of a semiconductor device including a ceramic package or the like. In addition, since the wiring area of the inner lead 18 can be limited only to the inside of the cut hole 16, it is advantageous for miniaturization.

【0006】さらに、別の従来例として放熱性を向上さ
せたものが、図4に示される。これは、デバイスホール
1内にインナリード18と同一面の配線によって吊られ
ている吊りリード22に放熱用バンプ25を形成してプ
リント基板20の側に放熱したり、放熱板24、ヒート
シンク21を取り付けることにより放熱性を向上させて
いた。
FIG. 4 shows another conventional example in which heat dissipation is improved. This is because the heat dissipation bumps 25 are formed on the suspension leads 22 suspended by the wiring on the same surface as the inner leads 18 in the device hole 1 to dissipate heat to the printed circuit board 20 side. The heat dissipation was improved by attaching.

【0007】[0007]

【発明が解決しようとする課題】上述した半導体装置
は、インナリード18と半田バンプ10とが同一面上に
配置されでいるため、例えばパッケージの外側に配置さ
れた端子は、その配線長が長くなり、インダクタンス
(L)等の電気特性が劣ることになる。特に高速化が進
むグランド配線は、短かく配線してノイズの影響を低減
しないと誤動作を生ずるという問題もある。このため配
線長を出来るだけ短かくしてその電気特性を向上させる
必要がある。そのため、例えばベースフィルムの裏面に
メタルが配設された2メタルTABテープを用い、グラ
ンド配線をスルーホールにより接続し、接地を強化して
電気特性を向上させる方法もある。しかし、この2メタ
ルテープを用いるとTABテープのコストが高くなり、
その実用化が困難となる問題がある。
In the above-described semiconductor device, since the inner leads 18 and the solder bumps 10 are arranged on the same surface, for example, terminals arranged outside the package have long wiring lengths. As a result, electrical characteristics such as inductance (L) are deteriorated. In particular, there is a problem that a malfunction of the ground wiring, in which the speed is increased, may occur unless the influence of noise is reduced by short wiring. For this reason, it is necessary to make the wiring length as short as possible to improve its electrical characteristics. Therefore, for example, there is a method of using a two-metal TAB tape in which metal is provided on the back surface of a base film, connecting ground wiring by through holes, and strengthening the ground to improve electrical characteristics. However, using this two-metal tape increases the cost of the TAB tape,
There is a problem that its practical use is difficult.

【0008】本発明の目的は、このような問題を解決
し、安価な構成で、配線長を出来るだけ短かくしてその
電気特性を向上させた半導体装置およびその製造方法を
提供することにある。
An object of the present invention is to provide a semiconductor device which solves such a problem, has an inexpensive configuration, has a short wiring length as much as possible, and has improved electrical characteristics, and a method of manufacturing the same.

【0009】[0009]

【課題を解決するための手段】本発明の構成は、半導体
チップを接続するデバイスホールを有するフィルムキァ
リアテープに、前記半導体チップの電極の接合されるイ
ンナリードおよびこのインナリードと同一平面上に外部
接続にため設けられたランドを有するTABテープを用
いた半導体装置において、前記デバイスホール内部に前
記インナリードと同一平面上に接地用配線とされた第1
の金属箔を設け、前記半導体チップのパッド電極と前記
インナリードとを接続し、前記ランドおよび前記第1の
金属箔をバンプを介して実装基板に接合したことを特徴
とする。
SUMMARY OF THE INVENTION The present invention is directed to a film carrier tape having a device hole for connecting a semiconductor chip, an inner lead to which an electrode of the semiconductor chip is joined, and an external lead on the same plane as the inner lead. In a semiconductor device using a TAB tape having lands provided for connection, a first grounding wiring is provided inside the device hole on the same plane as the inner lead.
And a pad electrode of the semiconductor chip is connected to the inner lead, and the land and the first metal foil are joined to a mounting board via bumps.

【0010】また本発明の半導体装置の製造方法の構成
は、半導体チップを搭載するフィルムキャリアテープの
デバイスホールに、接地接続される接地配線をもつTA
Bテープを形成し、前記接地配線の中央に樹脂封入孔を
形成し、接地用パッド電極に接地配線を接続して前記樹
脂封入孔から樹脂を注入して前記半導体チップを樹脂封
止し、前記接地配線のカバーレジストを開孔した穴部に
バンプを形成した後、前記半導体チップごとのパッケー
ジに切断し、このパッケージを実装用基板に接合するこ
とにより、前記接地配線を前記半導体チップ内部に形成
したことを特徴とする。
The method of manufacturing a semiconductor device according to the present invention is characterized in that a TA having a ground wire connected to the ground is provided in a device hole of a film carrier tape on which a semiconductor chip is mounted.
Forming a B tape, forming a resin sealing hole at the center of the ground wiring, connecting a ground wiring to a ground pad electrode, injecting resin from the resin sealing hole, and sealing the semiconductor chip with a resin; After forming bumps in the holes formed by opening the cover resist of the ground wiring, the package is cut into packages for each of the semiconductor chips, and this package is bonded to a mounting substrate to form the ground wirings inside the semiconductor chip. It is characterized by having done.

【0011】[0011]

【発明の実施の形態】以下本発明について図面を参照し
て説明する。図1は本発明の一実施の形態の半導体装置
を示す平面図およびそのA―A断面図である。本実施形
態の製造工程は、まずベースフィルム4のデバイスホー
ル1の内部に、グランド線(接地線)と接続されるグラ
ンド層3を有するTABテープを形成する。ここでグラ
ンド層3の中央部には、半導体チップ2とベースフィル
ム4とを固定し、かつ半導体チップ2の表面保護をする
樹脂6をコートする樹脂封入穴28が形成されている。
ただし半導体チップ2が小さく、例えば5mmsq程度
であると、デバイスホール1内のインナリード18の開
口部から樹脂を注入すれば、毛細管現象でグランド層3
と半導体チップ2との間に樹脂6が注入可能となるた
め、封入穴28を設けなくともよい場合がある。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention, and a sectional view taken along line AA of FIG. In the manufacturing process of the present embodiment, first, a TAB tape having a ground layer 3 connected to a ground line (ground line) is formed inside the device hole 1 of the base film 4. Here, a resin encapsulating hole 28 for fixing the semiconductor chip 2 and the base film 4 and coating the resin 6 for protecting the surface of the semiconductor chip 2 is formed in the center of the ground layer 3.
However, when the semiconductor chip 2 is small, for example, about 5 mmsq, if the resin is injected from the opening of the inner lead 18 in the device hole 1, the ground layer 3 is formed by capillary action.
Since the resin 6 can be injected between the semiconductor chip 2 and the semiconductor chip 2, the sealing hole 28 may not be required.

【0012】次いでグランドのパッド電極13にグラン
ド配線8を接続し、樹脂6により樹脂封止を行なう。こ
のような構成により、グランド配線が半導体チップ2の
中に含まれるため、その配線長を短かくでき、線路のイ
ンダクタンスを低減することができる。この樹脂6が硬
化する時、グランド層3が金属箔のみであると多少たわ
みができることがあるが、この場合には、補強用のレジ
スト29を予め金属箔下部に形成しておくと良い。この
レジスト29は、グランド層3の上面に形成したレジス
トと同一のものを用いれば熱膨張のバランスがとれる。
Next, the ground wiring 8 is connected to the ground pad electrode 13 and resin sealing is performed with the resin 6. With such a configuration, since the ground wiring is included in the semiconductor chip 2, the wiring length can be shortened, and the inductance of the line can be reduced. When the resin 6 cures, the ground layer 3 may be slightly bent if the ground layer 3 is made of only a metal foil. In this case, a reinforcing resist 29 is preferably formed in advance under the metal foil. If the resist 29 is the same as the resist formed on the upper surface of the ground layer 3, the thermal expansion can be balanced.

【0013】次にグランド層3の上にカバーレジスト9
の開口を設けて形成した穴に放熱、グランド用バンプ5
を形成する。この時デバイスホール1の外部のバンプ1
0と同時に形成することもできる。ここで放熱、グラン
ド用バンプ5を形成しないでパッケージを完成させ、プ
リント基板に実装する際に、導電性のある放熱性の接着
樹脂をグランド層3とプリント基板との間に形成する構
造でもよい。具体的には、プリント基板には接着樹脂を
ディスペンスし、その後パッケージをのせリフローして
接合する。
Next, a cover resist 9 is formed on the ground layer 3.
Heat radiation and ground bumps 5
To form At this time, bump 1 outside device hole 1
It can be formed simultaneously with 0. Here, when the package is completed without forming the heat radiation and ground bumps 5 and mounted on a printed circuit board, a structure in which a conductive heat-radiating adhesive resin is formed between the ground layer 3 and the printed circuit board may be used. . Specifically, an adhesive resin is dispensed on the printed circuit board, and then the package is placed thereon and reflowed for joining.

【0014】ここで前述した補強用レジスト29があれ
ば、グランド層3の金属箔にインナリード18につなが
るパターンを独立に形成することが容易となるため、グ
ランド層3の内部ランドが全てグランドに配線しなくて
もよくる。つまり、デバイスホール1の外部のランド1
7と同様に、デバイスホール1の内部のグランド層3に
もグランド、電源、信号線を独立して配線できるため、
より自由度が多くなり最適化が図られる。
Here, if the reinforcing resist 29 described above is used, it is easy to independently form a pattern connected to the inner lead 18 on the metal foil of the ground layer 3, so that all the internal lands of the ground layer 3 are grounded. There is no need to wire. That is, land 1 outside device hole 1
7, the ground, power and signal lines can also be independently routed on the ground layer 3 inside the device hole 1.
The degree of freedom is increased and optimization is achieved.

【0015】このように形成したパッケージは、電気特
性が向上すると共に、低コストで製作することができ
る。このパッケージを実装用基板に実装することで、半
導体チップ2から発熱した熱をより効果的にプリント基
板側に放熱することができるという特徴もある。
The package thus formed can be manufactured at low cost while improving the electrical characteristics. By mounting this package on a mounting substrate, there is also a feature that heat generated from the semiconductor chip 2 can be more effectively radiated to the printed circuit board side.

【0016】図2は本発明の第2の実施形態の平面図お
よびそのB―B,C―C,D―D断面図である。本実施
形態では、図2(a)に示すように、デバイスホール1
の外部のランド17の外周部にもグランド層11を形成
し、このデバイスホール1の内部のグランド層3に接続
した構造としている。またデバイスホール1の外部のグ
ランド層11はインナリード18に延びる配線間に全て
通した構造としている。この構造により、配線のインダ
クタンスを著しく低減することができ、これが1/2以
下になることが実験により確かめられた。例えば40m
msqのパッケージで、従来の構造では最大で25nH
あったものが、本実施形態では最大で7nHまで低減す
ることができた。
FIG. 2 is a plan view of a second embodiment of the present invention and sectional views taken along lines BB, CC, and DD. In the present embodiment, as shown in FIG.
The ground layer 11 is also formed on the outer peripheral portion of the land 17 outside, and is connected to the ground layer 3 inside the device hole 1. Further, the ground layer 11 outside the device hole 1 has a structure in which the ground layer 11 is entirely passed between wirings extending to the inner leads 18. With this structure, it was confirmed by experiments that the inductance of the wiring could be remarkably reduced, and this was reduced to half or less. For example, 40m
msn package, up to 25nH with conventional structure
However, in the present embodiment, it was possible to reduce the maximum to 7 nH.

【0017】また図2(b)に示したように、デバイス
ホール1の内部のグランド層3の下部にベースフィルム
4を残し、その下に設けた接着層12に半導体チップ2
を接着してインナリード18のみを樹脂6でコートした
構造としてもよい。この構造では樹脂6をグランド層3
内部から注入する必要がないため、安定した平坦性が得
られる。
As shown in FIG. 2B, the base film 4 is left under the ground layer 3 inside the device hole 1, and the semiconductor chip 2 is attached to the adhesive layer 12 provided thereunder.
May be bonded so that only the inner leads 18 are coated with the resin 6. In this structure, the resin 6 is connected to the ground layer 3
Since there is no need to implant from inside, stable flatness can be obtained.

【0018】[0018]

【発明の効果】以上説明したように本発明によれば、グ
ランド配線を短かくすることができるので、その電気特
性を改善することができると共に、従来のパッケージよ
りも低コストで製作することが可能となり、さらにプリ
ント基板に発熱を放熱できるため放熱性も著しく改善す
ることができるという効果がある。
As described above, according to the present invention, the length of the ground wiring can be shortened, so that its electric characteristics can be improved, and it can be manufactured at a lower cost than a conventional package. In addition, since heat can be radiated to the printed circuit board, heat radiation can be significantly improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施形態を示す平面図およびそ
のA―A部の断面図である。
FIG. 1 is a plan view showing a first embodiment of the present invention and a cross-sectional view taken along the line AA of FIG.

【図2】本発明の第2の実施形態を示す平面図およびそ
のB―B,C―C,D―D部の断面図である。
FIG. 2 is a plan view showing a second embodiment of the present invention and a cross-sectional view taken along the lines BB, CC, and DD.

【図3】従来例の半導体装置を説明する平面図およびそ
のA―A部の断面図である。
FIG. 3 is a plan view illustrating a conventional semiconductor device and a cross-sectional view taken along the line AA of FIG.

【図4】従来例の他の半導体装置を説明する断面図およ
びその平面図である。
FIG. 4 is a sectional view and a plan view illustrating another conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 デバイスホール 2 半導体チップ 3 内部グランド層(接地配線) 4 ベースフィルム 5 バンプ(放熱、接地用) 6 樹脂 7 接着材 8 グランド配線 9 カバーレジスト 10 バンプ 11 外部グランド層(接地配線) 12 接着層 13 パッド電極 14 カバーレジスト塗布線 15 スプロケットホール 16 カットホール 17 ランド 18 インナリード 19 OLBパッド 20 プリント基板 21 ヒートシンク 22 吊りリード 23 放熱性接着剤 24 放熱板 25 放熱用バンプ 26 放熱用OLBパッド 27 貫通孔 28 樹脂封入穴 29 補強用レジスト DESCRIPTION OF SYMBOLS 1 Device hole 2 Semiconductor chip 3 Internal ground layer (ground wiring) 4 Base film 5 Bump (for heat radiation and grounding) 6 Resin 7 Adhesive material 8 Ground wiring 9 Cover resist 10 Bump 11 External ground layer (ground wiring) 12 Adhesive layer 13 Pad electrode 14 Cover resist coating line 15 Sprocket hole 16 Cut hole 17 Land 18 Inner lead 19 OLB pad 20 Printed circuit board 21 Heat sink 22 Suspended lead 23 Heat dissipation adhesive 24 Heat sink 25 Heat dissipation bump 26 Heat dissipation OLB pad 27 Through hole 28 Resin sealing hole 29 Reinforcement resist

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップを接続するデバイスホール
を有するフィルムキァリアテープに、前記半導体チップ
の電極の接合されるインナリードおよびこのインナリー
ドと同一平面上に外部接続にため設けられたランドを有
するTABテープを用いた半導体装置において、前記デ
バイスホール内部に前記インナリードと同一平面上に接
地用配線とされた第1の金属箔を設け、前記半導体チッ
プのパッド電極と前記インナリードとを接続し、前記ラ
ンドおよび前記第1の金属箔をバンプを介して実装基板
に接合したことを特徴とする半導体装置。
1. A film carrier tape having a device hole for connecting a semiconductor chip, a TAB having an inner lead to which an electrode of the semiconductor chip is joined and a land provided for external connection on the same plane as the inner lead. In a semiconductor device using a tape, a first metal foil serving as a ground wiring is provided on the same plane as the inner lead inside the device hole, and a pad electrode of the semiconductor chip is connected to the inner lead; A semiconductor device, wherein the land and the first metal foil are joined to a mounting board via bumps.
【請求項2】 デバイスホール内部の第1の金属箔と半
導体チップが実装される基板との間が、導電性部材によ
り接続された請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the first metal foil inside the device hole and the substrate on which the semiconductor chip is mounted are connected by a conductive member.
【請求項3】 ランド周辺部に、接地用配線の第2の金
属箔が形成され、この第2の金属箔がデバイスホール内
部の金属箔と接続するよう配線された請求項1または2
記載の半導体装置。
3. A ground wiring second metal foil is formed around the land, and the second metal foil is wired so as to be connected to the metal foil inside the device hole.
13. The semiconductor device according to claim 1.
【請求項4】 半導体チップを搭載するフィルムキャリ
アテープのデバイスホールに、接地接続される接地配線
をもつTABテープを形成し、前記接地配線の中央に樹
脂封入孔を形成し、接地用パッド電極に接地配線を接続
して前記樹脂封入孔から樹脂を注入して前記半導体チッ
プを樹脂封止し、前記接地配線のカバーレジストを開孔
した穴部にバンプを形成した後、前記半導体チップごと
のパッケージに切断し、このパッケージを実装用基板に
接合することにより、前記接地配線を前記半導体チップ
内部に形成したことを特徴とする半導体装置の製造方
法。
4. A TAB tape having a ground wire connected to the ground is formed in a device hole of a film carrier tape on which a semiconductor chip is mounted, a resin sealing hole is formed in the center of the ground wire, and a ground pad electrode is formed. After connecting a ground wiring and injecting a resin from the resin sealing hole to seal the semiconductor chip with a resin and forming a bump in the hole where the cover resist of the ground wiring is opened, a package for each of the semiconductor chips is formed. And bonding the package to a mounting substrate to form the ground wiring inside the semiconductor chip.
JP8228917A 1996-08-29 1996-08-29 Semiconductor device and manufacturing method thereof Expired - Fee Related JP2825084B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP8228917A JP2825084B2 (en) 1996-08-29 1996-08-29 Semiconductor device and manufacturing method thereof
US08/921,145 US6046495A (en) 1996-08-29 1997-08-29 Semiconductor device having a tab tape and a ground layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8228917A JP2825084B2 (en) 1996-08-29 1996-08-29 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH1074795A true JPH1074795A (en) 1998-03-17
JP2825084B2 JP2825084B2 (en) 1998-11-18

Family

ID=16883887

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8228917A Expired - Fee Related JP2825084B2 (en) 1996-08-29 1996-08-29 Semiconductor device and manufacturing method thereof

Country Status (2)

Country Link
US (1) US6046495A (en)
JP (1) JP2825084B2 (en)

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US6953709B2 (en) 2001-07-31 2005-10-11 Renesas Technology Corp. Semiconductor device and its manufacturing method
US7193320B2 (en) 2002-05-30 2007-03-20 Fujitsu Limited Semiconductor device having a heat spreader exposed from a seal resin

Also Published As

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JP2825084B2 (en) 1998-11-18

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