JPH03265166A - Semiconductor device having iil - Google Patents
Semiconductor device having iilInfo
- Publication number
- JPH03265166A JPH03265166A JP2064753A JP6475390A JPH03265166A JP H03265166 A JPH03265166 A JP H03265166A JP 2064753 A JP2064753 A JP 2064753A JP 6475390 A JP6475390 A JP 6475390A JP H03265166 A JPH03265166 A JP H03265166A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- iil
- semiconductor device
- type
- amplification factor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title description 8
- 238000002955 isolation Methods 0.000 claims abstract description 11
- 238000000926 separation method Methods 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 230000003321 amplification Effects 0.000 abstract description 12
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 6
- 230000002950 deficient Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 102000003712 Complement factor B Human genes 0.000 description 4
- 108090000056 Complement factor B Proteins 0.000 description 4
- 210000000988 bone and bone Anatomy 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000009933 burial Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Landscapes
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はバイポーラ型ＬＳＩにおける論理素子（Ｉｎ
ｔｅｇｒａｔｅｄ Ｉｎｊｅｃｔｉｏｎ Ｌｏｇｉｃ
；以下、ＩＩＬと記す）を有する半導体装置に関するも
のである。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to logic elements (In
integrated injection logic
; hereinafter referred to as IIL).
第２図は従来のＩＩＬの構造の示す平面図、第３図は第
２図のＡ−Ａ 部の断面模式図であり、図において、１
はシリコン基板、２はｎ′″型埋型埋散拡散層はｐ゛型
型埋骨分離層４はｎ−型エビエミツタ層、５はｐ゛゛上
面分離層、６はフィールド酸化膜、７はｐ゛ベース層８
はｎ゛コレクフ層９は金属配線、１０は最終保護膜、１
１はヘース電極、１２はインジェクタ電極である。なお
、第２図では金属配線１０の図示は省略している。FIG. 2 is a plan view showing the structure of a conventional IIL, and FIG. 3 is a schematic cross-sectional view of the section A-A in FIG.
2 is a silicon substrate, 2 is an n''' type buried diffusion layer, p' type buried bone isolation layer 4 is an n- type emitter layer, 5 is a p' top surface isolation layer, 6 is a field oxide film, and 7 is a p゛Base layer 8
9 is the metal wiring, 10 is the final protective film, 1
1 is a heath electrode, and 12 is an injector electrode. Note that in FIG. 2, illustration of the metal wiring 10 is omitted.
次に従来のＴＩＬの動作について説明する。Next, the operation of the conventional TIL will be explained.
第４図は第２図に示すコレクタＣ１及びＣ２におけるコ
レクタ電流と電流増幅率Ｂ ＠ｆ ｆの関係を示したも
のである。図よりコレクタＣ１の電流増幅率Ｂ ｍｆｆ
１よりもコレクタＣ２の電流増幅率Ｂｅｆｆ２の方が大
きく、性能が良いということがわかる。FIG. 4 shows the relationship between collector current and current amplification factor B@ff in collectors C1 and C2 shown in FIG. 2. From the figure, the current amplification factor B mff of collector C1
It can be seen that the current amplification factor Beff2 of the collector C2 is larger than that of 1, indicating that the performance is better.
この原因として、ヘースｐ″層７からｐ゛型型埋骨分離
層３びｐ“型上面分離層５に流れ出る電流の存在が考え
られる。また第５図には第２図に示すコレクタＣ１の電
流増幅率とヘースｐ″層７とｐ゛型型埋骨分離層３びｐ
゛型上面分ｌｉ１層５との距離Ｌ１の関係を示したもの
であり、Ｌ、が小さいほどＢ ｍｆｆＺも小さくなって
おり、この原因も前述した内容と同一である。The reason for this is considered to be the presence of a current flowing from the hair p'' layer 7 to the p'' type buried bone separation layer 3 and the p'' type top separation layer 5. FIG. 5 also shows the current amplification factor of the collector C1 shown in FIG.
This figure shows the relationship between the distance L1 from the top surface of the ゛-type li1 layer 5, and the smaller L, the smaller BmffZ becomes, and the reason for this is the same as described above.
従来のＩＩＬは以上のように構成されているので、ｐ゛
型型埋骨分離層３びｐ゛゛上面分離層５に最も近接した
ベースｐ°層７内に形成されるＩＩＬはその電流増幅率
Ｂａｔｘが小さく、ＩＩＬが正常に動作しないという問
題があった。また、この問題を回避するためにｎ゛゛チ
ャネルカット層を形成することも考えられるが、ウェハ
プロセスの処理工程の増大とパターン面積の増大が起こ
るという問題点があった。Since the conventional IIL is configured as described above, the IIL formed in the base p° layer 7 closest to the p゛ type bone separation layer 3 and the p゛ top surface separation layer 5 has a current amplification factor of There was a problem that Batx was small and IIL did not work properly. Furthermore, in order to avoid this problem, it may be possible to form an n-channel cut layer, but this has the problem of increasing the number of processing steps in the wafer process and increasing the pattern area.
この発明は上記のような問題点を解消するためになされ
たもので、ウェハプロセスの処理工程を追加することな
く、高い電流増幅率のＩＩＬを形成することができるＩ
ＩＬを有する半導体装置を得ることを目的とする。This invention was made to solve the above-mentioned problems, and it is possible to form an IIL with a high current amplification factor without adding any processing steps in the wafer process.
The object is to obtain a semiconductor device having an IL.
〔課題を解決するための手段〕
この発明に係るＩＩＬを有する半導体装置は、ＰＮ分離
領域に近接するベース層に形成されるＩＩＬを回路とし
て使用せず、ダミーパターンとして使用するようにした
ものである。[Means for Solving the Problems] A semiconductor device having an IIL according to the present invention is such that the IIL formed in the base layer near the PN isolation region is not used as a circuit but is used as a dummy pattern. be.
この発明におけるＩＬＬを有する半導体装置は、分離領
域に近接するベース層に形成されるＩＩＬを使用しない
ので、第４図に示すように高電流増幅率Ｂ ｍｆｆｔが
保持され、ＩＩＬ回路の誤動作等がなく、素子の不良率
の低減が図れる。Since the semiconductor device having the ILL according to the present invention does not use the IIL formed in the base layer close to the isolation region, a high current amplification factor B mfft is maintained as shown in FIG. 4, and malfunctions of the IIL circuit are prevented. Therefore, it is possible to reduce the defective rate of elements.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例によるＩＩＬを有する半導体
装置を示しており、図において、各符号は第３図と同一
または相当部分である。ｐ゛型型埋骨分離Ｎ３ｐ゛゛上
面分離層５に並列するｐ゛ベース層７（第１図中裂でハ
ンチングしである部分）に形成されるＩＩＬは回路とし
て用いず、ダミーとして用いることにより、常に第４図
に示す高電流増幅率Ｂ 、ｆｔｚが保たれ、ｎ゛゛チャ
ネルカット層を形成する等のウェハプロセスの処理工程
を増すことなく、特性の向上、不良率の低減を図ること
ができる。FIG. 1 shows a semiconductor device having an IIL according to an embodiment of the present invention, and in the figure, each reference numeral is the same or a corresponding part as in FIG. 3. By using the IIL formed on the p' base layer 7 (the part with the hunting part in the center of Fig. 1) parallel to the p' type burial bone separation N3p' upper surface separation layer 5 as a dummy instead of as a circuit, , the high current amplification factor B, ftz shown in Fig. 4 is always maintained, and the characteristics can be improved and the defective rate reduced without increasing the number of processing steps in the wafer process such as forming a channel cut layer. can.
以上のように、この発明によれば、ＰＮ分離領域に近接
したベース層に形成されるＩＩＬは回路として用いず、
ダミーパターンとすることにより、ウェハプロセスの処
理工程の増大を起こすことなく、高電流増幅率のＩＩＬ
が得られ、精度が高く不良率の低い半導体装置が得られ
る効果がある。As described above, according to the present invention, the IIL formed in the base layer close to the PN isolation region is not used as a circuit,
By using a dummy pattern, IIL with a high current amplification rate can be achieved without increasing the number of processing steps in the wafer process.
This has the effect of providing a semiconductor device with high precision and a low defective rate.
第１図はこの発明の一実施例によるＩＩＬを有する半導
体装置を示す平面図、第２図は従来のＩＩＬを有する半
導体装置を示す平面図、第３図は第２図のＡ−Ａ ’の
断面模式図、第４図はコレクタ電流と電流増幅率の関係
を示す図、第５図はヘースー分離間距離Ｌ１と電流増幅
率の関係を示す図である。
１はシリコン基板、２はｎ゛゛埋込拡散層、３はｐ゛゛
埋込分離層、４はｎ−型エビエミツタ層、５はｐ゛゛上
面分離層、６はフィールド酸化膜、７はｐ゛ヘース層８
はｎ“コレクタ層、９は金属配線、１０は最終保護膜、
１１はベース電極、１２はインジェクタ電極である。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a plan view showing a semiconductor device having an IIL according to an embodiment of the present invention, FIG. 2 is a plan view showing a conventional semiconductor device having an IIL, and FIG. 3 is a plan view taken along line A-A' in FIG. A schematic cross-sectional view, FIG. 4 is a diagram showing the relationship between the collector current and the current amplification factor, and FIG. 5 is a diagram showing the relationship between the distance L1 between the hexagonal separations and the current amplification factor. 1 is a silicon substrate, 2 is an n-buried diffusion layer, 3 is a p-buried isolation layer, 4 is an n-type emitter layer, 5 is a p-top isolation layer, 6 is a field oxide film, and 7 is a p-base. layer 8
is the n" collector layer, 9 is the metal wiring, 10 is the final protective film,
11 is a base electrode, and 12 is an injector electrode. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
る論理素子（ＩｎｔｅｇｒａｔｅｄＩｎｊｅｃｔｉｏｎ
Ｌｏｇｉｃ；以下、ＩＩＬと記す）を有する半導体装置
において、 上記ＩＩＬのうち、上記ＰＮ分離領域に近接した領域の
ベース層に形成されたＩＩＬをダミーパターンとしたこ
とを特徴とするＩＩＬを有する半導体装置。(1) Logic elements (Integrated Injection) formed in bipolar ICs with PN separation structure
Logic (hereinafter referred to as IIL), characterized in that, among the IILs, an IIL formed in a base layer in a region close to the PN isolation region is made into a dummy pattern. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2064753A JPH03265166A (en) | 1990-03-14 | 1990-03-14 | Semiconductor device having iil |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2064753A JPH03265166A (en) | 1990-03-14 | 1990-03-14 | Semiconductor device having iil |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03265166A true JPH03265166A (en) | 1991-11-26 |
Family
ID=13267250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2064753A Pending JPH03265166A (en) | 1990-03-14 | 1990-03-14 | Semiconductor device having iil |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03265166A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5468983A (en) * | 1993-03-03 | 1995-11-21 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of manufacturing the same |
-
1990
- 1990-03-14 JP JP2064753A patent/JPH03265166A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5468983A (en) * | 1993-03-03 | 1995-11-21 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of manufacturing the same |
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