JPH05218453A - Electrostatic induction type semiconductor device - Google Patents

Abstract

PURPOSE:To enable an electrostatic induction type semiconductor device to be enhanced in resistance to a reverse surge voltage between a gate and a source and improved in backward breakdown strength between a drain and a source. CONSTITUTION:A peripheral isolation P-type semiconductor region 47 of the same impurity concentration and thickness with a P-type gate region 37 is formed under a source bonding pad region 39a located above an N--type epitaxial layer 33 as being isolated from a P-type gate region 37 and electrically connected to a source electrode 39. The peripheral isolation P-type semiconductor region 47 is made to serve as the anode region of a reverse diode between a drain and a source formed of the N--type epitaxial layer 33 and the region 47. A junction composed the peripheral isolation P-type semiconductor region 47, the N--type epitaxial layer 33, and an adjacent P-type gate region 37a is formed to serve as a punch-through diode which is punched through under a lower voltage than the breakdown voltage of a PN junction between a P-type channel region 35 and an N<+>-type source region 36.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic induction type semiconductor device which is required to have a high breakdown voltage and a high current amplification factor.
The present invention relates to an electrostatic induction semiconductor device having a structure in which punch through diodes are added between sources.

[0002]

2. Description of the Related Art Generally, static induction transistors (Static
Induction Transistor (hereinafter referred to as SIT) is characterized by a high current amplification factor, but its source region has a particularly fine structure compared to other semiconductor regions.

FIG. 3 is a sectional view showing an internal structure of a main part of a semiconductor chip constituting a conventional normally-off type SIT. As shown in the figure, the semiconductor chip 11 constituting the conventional SIT includes an N ⁺ type silicon substrate 12 and an N ⁺ type silicon substrate 12.
^The N ⁻ type epitaxial layer 13 formed by performing epitaxial growth above the ⁺ type silicon substrate 12 is formed as a mother body.

Then, in the upper part of the semiconductor chip 11,
A silicon oxide film (S _i O ₂ ) 14 having a predetermined thickness formed by oxidizing the surface of the N ⁻ type epitaxial layer 13 as an insulating film.
Are selectively formed. Repeating the formation and removal of the silicon oxide film 14, the N by selectively applying it from above, for example, ion implantation or the like ^- in the upper layer of the type epitaxial layer 13, comprising a P-type impurity at a low concentration P ^- A plurality of type channel regions 15 are arranged at predetermined intervals, and the upper layer portion of each of the plurality of P ⁻ type channel regions 15 also contains a high concentration of N type impurities by ion implantation or the like. The N ⁺ type source region 16 is formed.

A P-type gate region 17 containing a P-type impurity at a medium concentration is also formed by ion implantation or the like so as to surround each P ^- type channel region 15 in which the N ⁺ type source region 16 is formed. The P ⁻ type channel region 15 is continuously arranged so as to surround the P ⁻ type channel region 15. A main current path is formed in each P ⁻ type channel region 15 between the P type gate regions 17 which are adjacent to each other with the N ⁺ type source regions 16 interposed therebetween.

Here, of the P-type gate regions 17 (hereinafter, referred to as peripheral P-type gate regions) at positions around each P ⁻ -type channel region 15 and each N ⁺ -type source region 16,
Part of the silicon oxide film 14 on one peripheral P-type gate region 17a is removed by etching or the like, and vacuum evaporation or the like is performed on the exposed surface of the peripheral P-type gate region 17a and the silicon oxide film 14 on the periphery thereof. The gate electrode 18 is installed using aluminum, for example, by
The mold gate region 17a and the gate electrode 18 are electrically connected.

Further, from a portion above the one peripheral P type gate region 17a above the semiconductor chip 11 to the other peripheral P type gate region 17a.
On the silicon oxide film 14 formed over the type gate region 17b except the upper portion of each N ⁺ type source region 16, a source electrode 19 is also formed by using, for example, aluminum by a method such as vacuum deposition. .. Therefore,
The peripheral P-type gate region 17b and the source electrode 19 are insulated.

In order to stabilize the characteristics of the device, the gate bonding pad region 18a and the source bonding pad region 19a are left on the upper part of the semiconductor chip 11 on which both electrodes are provided, and a part of both electrodes is left. The silicon oxide film 14 and the passivation film 20 are evenly provided. With the passivation film 20,
The gate electrode 18 and the source electrode 19 are also insulated.

Further, the N ⁺ type semiconductor substrate 12 is an N ⁺ type drain region, and the drain electrode 21 is provided in contact with the entire surface of the N ⁺ type drain region by using an appropriate electrode material.

The SIT having the above structure is a normally-off type SIT.
When IT, and when a forward bias voltage of a predetermined voltage value or more is not applied between the gate electrode 18 and the source electrode 19, the P ⁻ type channel region 15 is completely depleted, and the P ⁻ type channel region 15 is between the source and the drain. Does not flow current.

[0011]

Generally, in the SIT having the above structure, the N ⁺ type source region 16 of the semiconductor region has a finer structure than the other semiconductor regions, and the gate- The input capacitance in the reverse direction between the sources is small, the junction between the gate and the source is weak against the reverse surge voltage due to static electricity, and the reverse breakdown voltage between the drain and the source is low because the P-type impurity concentration in the channel region is low. It was For this reason, it is often necessary to add a reverse diode when the device is actually used.

The present invention has been made in view of the above circumstances, and an object of the present invention is to enable manufacture without increasing or complicating a manufacturing process which has been conventionally used,
An object of the present invention is to provide a static induction semiconductor device having a structure in which the reverse surge voltage between the gate and the source is strong, the electrostatic withstand capability is increased, and the reverse breakdown withstand capability between the drain and the source is improved.

[0013]

According to the present invention, a plurality of first-conductivity-type source regions are provided near a main surface of a first-conductivity-type semiconductor layer at predetermined intervals, and the first-conductivity-type source regions. And a second conductive type gate region disposed so as to surround each of the first conductive type source regions in the vicinity of one main surface of the semiconductor layer, and adjacent to each other with the first conductive type source region interposed therebetween. In the static induction semiconductor device, in which the second conductive type gate region between the second conductive type gate regions is a second conductive type channel region having an impurity concentration lower than that of the second conductive type gate region, A second-conductivity-type semiconductor region that is electrically connected to the source electrode is provided by separating a part from the second-conductivity-type gate region, and the second-conductivity-type gate region and the second-conductivity-type semiconductor region are separated. A semiconductor layer of the first conductivity type and a second conductive layer The withstand voltage between the gate regions of the first conductivity type and the withstand voltage between the semiconductor layer of the first conductivity type and the semiconductor region of the second conductivity type in the separation portion are the channel region of the second conductivity type and the first conductivity type. It is characterized in that it is set lower than the withstand voltage between the source regions.

[0014]

In the present invention, the second-conductivity-type semiconductor region is formed separately from the second-conductivity-type gate region and electrically connected to the source electrode. It is formed as an anode region of a reverse diode composed of a semiconductor layer of one conductivity type. Therefore, when the potential of the source becomes higher than that of the drain, the current flows through this reverse diode, and the destruction of the element is avoided.

In addition, the breakdown voltage between the first conductivity type semiconductor layer and the second conductivity type gate region in the isolation portion of the second conductivity type gate region and the second conductivity type semiconductor region, and the isolation portion. Since the breakdown voltage between the first conductive type semiconductor layer and the second conductive type semiconductor region is set lower than the breakdown voltage between the second conductive type channel region and the first conductive type source region, a fine structure is achieved. The semiconductor layer of the first conductivity type in the isolation region, which is wider than the source region of the first conductivity type, is punched through, and the reverse surge voltage between the gate and the source is strengthened, and the electrostatic withstand capability is improved, resulting in device breakdown. Escape from.

Further, the second conductivity type semiconductor region is the second region.
Since it has the same impurity concentration and the same depth as those of the conductive type gate region, it does not lead to an increase in the number of manufacturing processes and a complicated process.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a normally-off type S of the present invention.
It is sectional drawing which shows the internal structure of the principal part of the semiconductor chip which comprises IT.

As shown in FIG. 1, the semiconductor chip 31 constituting the SIT of this embodiment has the N ⁺ type silicon substrate 32 and the N ⁺ type silicon substrate 32 as in the conventional SIT shown in FIG. The N ⁻ type epitaxial layer 33 formed by performing epitaxial growth on the upper side is formed as a base material. A semiconductor substrate made of silicon single crystal may be formed as a matrix.

[0019] On the surface region of the semiconductor chip 31, N as the insulating film ^- -type epitaxial layer by oxidizing the surface of the 33 comprising a predetermined film thickness of the silicon oxide film (S _i O ₂₎
34 are selectively formed. The silicon oxide film 3
Various semiconductor regions as shown below are formed in the upper layer of the N ⁻ type epitaxial layer 33 by selectively performing, for example, ion implantation from above while repeatedly forming and removing 4.

That is, in the upper layer of the N ⁻ type epitaxial layer 33, a plurality of P ⁻ type channel regions 35 containing a low concentration of P type impurities are arranged at predetermined intervals, and the plurality of P ⁻ type channel regions 35 are formed. ^- the upper portion of each type channel region 35, a stripe-shaped or block-shaped N ⁺ type source region 36 comprising an N-type impurity in a high concentration is formed.

Also, N⁺Each of the mold source regions 36 is formed.
Each P^-P-type so as to surround the mold channel region 35
The P-type gate region 37 containing an impurity in a medium concentration,
The P ^-Are continuously arranged so as to surround the mold channel region 35.
P-type gate region 3 which is provided and is continuously arranged
P-type semiconductor region 47 (hereinafter, peripheral isolation P
Type semiconductor region) is the same impurity as the P type gate region 37.
They are arranged at the same concentration and the same depth. This is above
Of the P-type gate regions 37 continuously arranged as
A region closest to the peripheral isolation P-type semiconductor region 47 (hereinafter, referred to as a near region).
A predetermined distance L from the side P-type gate region 37c)
Are installed. Where each N⁺The mold source region 36
Each P between the P-type gate regions 37 that are adjacent to each other with a pin between them^-Type
A main current path is formed in the channel region 35.

Then, with respect to the neighboring P type gate region 37c at a position surrounding each P ⁻ type channel region 35 and each N ⁺ type source region 36, the other peripheral P type gate region 37 is provided.
Part of the silicon oxide film 34 on a (hereinafter referred to as the peripheral P-type gate region) is removed by etching or the like, and the exposed surface of the peripheral P-type gate region 37a and the silicon oxide film 34 on the periphery thereof are The gate electrode 38 is provided using, for example, aluminum by a technique such as vacuum deposition, and the peripheral P-type gate region 37a and the gate electrode 38 are electrically connected.

Further, silicon is formed over a part of the peripheral P-type gate region 37a above the semiconductor chip 31 to a part of the peripheral isolation P-type semiconductor region 47 except the upper part of each N ⁺ type source region 36. On the oxide film 34, the source electrode 39 is similarly installed by using a method such as vacuum vapor deposition using aluminum. Perimeter separation P
The silicon oxide film 34 on the type semiconductor region 47 is removed by etching or the like, leaving a part thereof, and the peripheral isolation P-type semiconductor region 47 and the source electrode 39 are electrically connected.

In order to stabilize the characteristics of the device, the gate bonding pad region 38a and the source bonding pad region 39a are left above the semiconductor chip 31 on which the above-mentioned electrodes are provided, and one electrode of both electrodes is left. Portion and the silicon oxide film 34 to cover the passivation film 40.
Are installed uniformly. The passivation film 40
Therefore, the gate electrode 38 and the source electrode 39 are also insulated.

The N ⁺ type semiconductor substrate 32 is an N ⁺ type drain region, and the drain electrode 41 is provided in contact with the entire surface of the N ⁺ type drain region using an appropriate electrode material. As a result, the semiconductor chip 31 having the function of SIT is obtained.

In the above, the peripheral isolation P-type semiconductor region 4
The distance L between the P-type gate region 37c and the neighboring P-type gate region 37c depends on the concentration of N-type impurities in the N ⁻ type epitaxial layer 33, but is, for example, several μm to several tens of μm.
The distance is set so as to punch through at a voltage lower than the PN junction breakdown voltage between the sources.

This embodiment is configured as described above,
P under the source bonding pad 19a in the conventional example
In the present embodiment, the type gate region 17b (see FIG. 3) is similarly formed separately in the neighboring P type gate region 37c below the source bonding pad 39a and the peripheral isolation P type semiconductor region 47. The peripheral isolation P-type semiconductor region 47 is electrically connected to the source electrode 39 and serves as an anode region of a diode formed of a PN (PN ⁻ ) junction formed by the P-type semiconductor region 47 and the N ⁻ type epitaxial layer 33. Formed, as shown in the equivalent circuit of FIG.
This means that the reverse diode 51 is added between the drain and the source.

The PNP (PN ^- P) junction formed by the neighboring P-type gate region 37c, the N ^-- type epitaxial layer 33 and the peripheral isolation P-type semiconductor region 47 has a P ^-- type channel region 35 and an N ⁺ -type channel region. It is formed so as to punch through at a voltage lower than the breakdown voltage of the gate-source PN junction formed with the source region 36, and a punch through diode 52 is added as shown in the equivalent circuit of FIG. ..

Therefore, when the SIT having the above structure is reverse-biased and the potential of the source becomes higher than that of the drain, the current flowing between the drain and the source is the reverse diode 5.
1 and does not flow into the N ⁺ type source region 36 formed in the fine structure. Therefore, the device is not destroyed.

In addition, the isolation region between the P-type gate region 37c in the vicinity of the N ^-- type epitaxial layer 33 and the peripheral isolation P-type semiconductor region 47, which is a component of the punch-through diode 52 formed under the source bonding pad, is formed. In the SIT of this embodiment, the gate-source is punched through in a wide range, the structure is strong against surge voltage, the electrostatic withstand capability is improved, and the device is protected from destruction.

Further, the SIT of the present embodiment can be manufactured by changing only the contact mask and the P-type gate region mask as compared with the conventional SIT, and can be manufactured in the same number of steps as the conventional. It does not lead to increase or complexity of manufacturing process.

The above embodiment is a surface gate type SIT.
However, it is also applicable to an embedded gate type SIT, and further to an SIT whose conductivity type is opposite to those of these two types of SIT.

Further, not only the S _i device but also a compound semiconductor such as G _e or G _a A _s may be used. Further, a bipolar transistor having a structure basically similar to that of the SIT, that is, a structure in which a reverse diode is added between the drain and the source and a punch through diode is added between the gate and the source as in the above embodiment. Can also be applied to.

[0034]

As described above, according to the present invention, since the reverse diode is added between the drain and the source, the breakdown of the element due to the application of the reverse bias voltage is eliminated.
Since a punch-through diode is added between the gate and the source, the reverse surge voltage between the gate and the source is strengthened and the electrostatic withstand capability is improved.

Further, as compared with the conventional method, it can be manufactured only by changing the mask, and can be manufactured in the same number of steps.
It does not lead to increase or complexity of manufacturing process.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an internal structure of a main part of a semiconductor chip that constitutes an SIT according to an embodiment of the present invention.

FIG. 2 is an illustration of a drain-source and gate-source equivalent circuit of the SIT of FIG.

FIG. 3 is a cross-sectional view showing an internal structure of a main part of a semiconductor chip forming a conventional SIT.

[Description of Reference Signs] 31 semiconductor chip 32 N ⁺ type silicon substrate 33 N ⁻ type epitaxial layer 35 P ⁻ type channel region 36 N ⁺ type source region 37 P type gate region 38 gate electrode 38a gate bonding pad region 39 source electrode 39a source Bonding pad area 41 Drain electrode 47 Peripheral isolation P-type semiconductor area

Claims (1)

[Claims] 1. A plurality of first-conductivity-type source regions arranged at a predetermined interval in the vicinity of one main surface of a first-conductivity-type semiconductor layer, and in the vicinity of one main surface of the first-conductivity-type semiconductor layer. And a second conductive type gate region surrounding the first conductive type source region, the second conductive type gate region being adjacent to each other with the first conductive type source region interposed therebetween. In a static induction type semiconductor device in which a second conductive type channel region having an impurity concentration lower than that of the second conductive type gate region is formed between the second conductive type gate region and the second conductive type gate region below the bonding pad region of the source electrode. A second conductive type semiconductor region that is electrically connected to the source electrode is provided by separating the portion, and the first conductive type semiconductor region is provided in a separated portion of the second conductive type gate region and the second conductive type semiconductor region. Between the semiconductor layer and the gate region of the second conductivity type , And the breakdown voltage between the semiconductor layer of the first conductivity type and the semiconductor region of the second conductivity type in the isolation portion is calculated from the breakdown voltage between the channel region of the second conductivity type and the source region of the first conductivity type. An electrostatic induction type semiconductor device characterized by being set low.