JPH0324784B2 - - Google Patents
Info
- Publication number
- JPH0324784B2 JPH0324784B2 JP58112027A JP11202783A JPH0324784B2 JP H0324784 B2 JPH0324784 B2 JP H0324784B2 JP 58112027 A JP58112027 A JP 58112027A JP 11202783 A JP11202783 A JP 11202783A JP H0324784 B2 JPH0324784 B2 JP H0324784B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- nitride film
- wiring
- silicon nitride
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 25
- 150000004767 nitrides Chemical class 0.000 description 13
- 239000011229 interlayer Substances 0.000 description 9
- 239000012535 impurity Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 230000008020 evaporation Effects 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000001017 electron-beam sputter deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に関し、特に多層配線構造
を有する半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device having a multilayer wiring structure.
半導体装置の高集積化、高速化、あるいは設計
工数の短縮化のためには、半導体装置の多層配線
化は必要不可欠である。今日まで多種多様な多層
配線構造が提案されているが、その１つに配線金
属としてアルミニウムあるいはアルミニウム合金
を、層間絶縁膜としてプラズマCVD窒化膜を、
表面を平担化するために所謂SOG（Spin On
Glass）膜をそれぞれ用いる多層配線構造があ
る。この構造は、製造方法が比較的簡単であるた
めに広く用いられている。 2. Description of the Related Art In order to increase the integration and speed of semiconductor devices, or to shorten the number of design steps, multilayer wiring of semiconductor devices is essential. To date, a wide variety of multilayer wiring structures have been proposed, one of which uses aluminum or aluminum alloy as the wiring metal and a plasma CVD nitride film as the interlayer insulating film.
So-called SOG (Spin On) is used to flatten the surface.
There is a multilayer wiring structure that uses a glass film. This structure is widely used because the manufacturing method is relatively simple.
ところで、この構造は配線の材質に関わる重要
な問題を含んでいた。これを、第１図と第２図を
用いて説明する。第１図において、１はシリコン
基板、２はその表面を熱酸化して得たシリコン酸
化膜、３はシリコン基板表面の拡散領域を結ぶ厚
さ1.0μmの第１層目のAl配線、４はこの第１の層
目Al配線３と後で形成する第２層目Al配線６と
を絶縁するためにプラズマCVD法によつて形成
した厚さ1.0μmの窒化シリコン膜、そして、５は
第１層目Al配線３の段部で第２層目Al配線６が
段切れしないように段部の傾斜をなめらかにする
ために回転塗布法によつて形成されたSOG（Spin
On Glass）膜である。このような構造にするこ
とで第１層目と第２層目とのAl配線３，６がシ
ヨートせず、しかも第２層Al配線６が段切れし
ない多層配線が得られる。 However, this structure involved an important problem related to the material of the wiring. This will be explained using FIGS. 1 and 2. In FIG. 1, 1 is a silicon substrate, 2 is a silicon oxide film obtained by thermally oxidizing its surface, 3 is a first layer of Al wiring with a thickness of 1.0 μm that connects the diffusion region on the silicon substrate surface, and 4 is a silicon oxide film obtained by thermally oxidizing the surface of the silicon substrate. 5 is a silicon nitride film with a thickness of 1.0 μm formed by plasma CVD to insulate the first layer Al wiring 3 from the second layer Al wiring 6 to be formed later; SOG (Spin) is formed by a spin coating method to smooth the slope of the step so that the second layer Al wiring 6 does not break at the step of the layer Al wiring 3.
On glass) film. By adopting such a structure, a multilayer wiring can be obtained in which the first and second layer Al wirings 3 and 6 are not shot, and the second layer Al wiring 6 is not cut off.
ところで、SOG膜５はケイ素化合物〔RnSi
（OH）4-oを有機溶剤に溶解したものを焼きしめす
ることで得られる酸化ケイ素（SiO2）の被膜で
ある。したがつて、塗布した後に溶剤を除去する
ため、なるべく高温で焼きしめを行なう必要があ
るが、第１層Al配線３とシリコン基板１との反
応温度を考慮して、SOG膜形成の可能な熱処理
温度は450℃位である。この温度で、完全ではな
いが、素子の特性と信頼性に対して十分なSOG
膜５の焼きしめを行なうことができる。 By the way, the SOG film 5 is made of silicon compound [RnSi
(OH) A film of silicon oxide (SiO 2 ) obtained by dissolving 4-o in an organic solvent and baking it. Therefore, in order to remove the solvent after coating, it is necessary to perform baking at as high a temperature as possible, but considering the reaction temperature between the first layer Al wiring 3 and the silicon substrate 1, it is necessary to The heat treatment temperature is about 450℃. At this temperature, SOG is sufficient, but not perfect, for device characteristics and reliability.
The membrane 5 can be hardened.
しかしながら、かかる温度で焼きしめを行なう
と、第２図に示すように層間絶縁膜であるプラズ
マCVD窒化膜４がもり上がつたり、割れたりす
る現象７がしばしば発生した。当然のことなが
ら、この上に第１図で示した第２層目のAl配線
６を形成すると、第１層目のAl配線３と接触し
てこの素子はシヨート不良となる。 However, when baking is performed at such a temperature, a phenomenon 7 in which the plasma CVD nitride film 4, which is an interlayer insulating film, bulges or cracks often occurs, as shown in FIG. Naturally, if the second layer Al wiring 6 shown in FIG. 1 is formed on top of this, it will come into contact with the first layer Al wiring 3, resulting in a short defect in this element.
この現象を注意深く調べたところ、原因は第１
層目のAl配線３に含まれる不純物（特に水分）
であることがわかつた。 After carefully investigating this phenomenon, we found that the cause was
Impurities (especially water) contained in layer Al wiring 3
It turns out that it is.
シリコン基板の表面に電子ビーム蒸着法や、ス
パツタリング蒸着法によつてAlを蒸着した後、
フオトリゾグラフイ技術を用いてパターンを形成
することによつてAl配線は形成されるが、蒸着
装置内に非常にわずかではあるが水分等の残留ガ
スが存在していて、この結果、Al蒸着中にこれ
らの不純物が入り込む。このように不純物が混入
したAl配線が層間絶縁膜である厚さ1.0μmのプラ
ズマCVD窒化膜４で完全に被われた状態で、
SOG膜５の焼き締めのために450℃の熱処理が行
なわれると、Al配線中に含まれる水分等の不純
物が膨張したり、あるいはAlと反応してその生
成物が膨張したりする。特にプラズマCVD窒化
膜はピンホール等の欠陥も少なく、また多くの物
質の透過性に対して阻止能力が高いため、これら
のガスは逃げ場所がなく、結局プラズマCVD窒
化膜を押し上げたり割つたりするのである。 After depositing Al on the surface of the silicon substrate by electron beam evaporation or sputtering evaporation,
Al wiring is formed by forming a pattern using photolithography technology, but a very small amount of residual gas such as moisture is present in the evaporation equipment, and as a result, Al evaporation These impurities get inside. With the Al wiring mixed with impurities completely covered with the plasma CVD nitride film 4 with a thickness of 1.0 μm, which is an interlayer insulating film,
When heat treatment at 450° C. is performed to bake and tighten the SOG film 5, impurities such as moisture contained in the Al wiring expand, or react with Al and its products expand. In particular, the plasma CVD nitride film has few defects such as pinholes, and has a high blocking ability against the permeability of many substances, so these gases have no place to escape and end up pushing up or breaking the plasma CVD nitride film. That's what I do.
このような問題を根本的に解決するには、不純
物を含まないAl配線を形成すれば良いが、現在
広く用いられているAlの蒸着機ではこのような
Alを形成することができない。 In order to fundamentally solve these problems, it would be possible to form Al wiring that does not contain impurities, but the currently widely used Al evaporation machines cannot do this.
Unable to form Al.
本発明は上記問題点に鑑み、層間絶縁膜の割れ
による第1Al配線と第2Al配線のシヨート不良が
全くない多層配線の構造を提供するものである。 In view of the above-mentioned problems, the present invention provides a multilayer wiring structure in which there is no shorting failure of the first Al wiring and the second Al wiring due to cracks in the interlayer insulating film.
すなわち、本発明は下層の配線層上に該配線層
内に含まれた不純物が透過するような膜厚の窒化
シリコン膜が形成され、この上に酸化シリコン膜
が形成され、これらを層間絶縁膜の少なくとも１
部として上層の配線層が形成されていることを特
徴とする。 That is, in the present invention, a silicon nitride film is formed on a lower wiring layer to a thickness that allows impurities contained in the wiring layer to pass through, a silicon oxide film is formed on this film, and these are formed into an interlayer insulating film. at least one of
It is characterized in that an upper wiring layer is formed as a portion.
また、本発明は、多層配線構造における層間絶
縁膜が、厚さ300Åから2000Åの第１プラズマ
CVD窒化シリコン膜、SOG（Spin On Glass）膜
および厚さ3000Å以上の第２プラズマCVD窒化
シリコン膜の３層構造を有することを特徴とす
る。 Further, the present invention provides that the interlayer insulating film in the multilayer wiring structure is formed by the first plasma with a thickness of 300 Å to 2000 Å.
It is characterized by having a three-layer structure of a CVD silicon nitride film, an SOG (Spin On Glass) film, and a second plasma CVD silicon nitride film with a thickness of 3000 Å or more.
以下に本発明の実施例を第３図を用いて説明す
る。第１層Al配線３を形成した後、1000Åの第
１プラズマCVD窒化シリコン膜４−１を成長す
る。次に回転塗布法によつてSOG膜５を形成し、
SOG膜５中に存在する溶剤を除去するために450
℃の熱処理を行なう。このとき、第１プラズマ
CVD窒化シリコン膜４−１は1000Åと薄いため、
第１層Al配線３中に含まれる不純物はこれを透
過し外部に出ることができる。従つて、従来のよ
うにプラズマCVD窒化膜に割れを発生させるこ
とはない。 An embodiment of the present invention will be described below with reference to FIG. After forming the first layer Al wiring 3, a first plasma CVD silicon nitride film 4-1 with a thickness of 1000 Å is grown. Next, a SOG film 5 is formed by a spin coating method,
450 to remove the solvent present in the SOG film 5
Perform heat treatment at ℃. At this time, the first plasma
Since the CVD silicon nitride film 4-1 is as thin as 1000 Å,
Impurities contained in the first layer Al wiring 3 can pass through this and exit to the outside. Therefore, cracks do not occur in the plasma CVD nitride film as in the conventional method.
この後、第1Al配線と第2Al配線を完全に絶縁
するために9000Åの第２プラズマCVD窒化シリ
コン膜４−２を成長する。このように従来1.0μm
のプラズマCVD窒化膜とSOG膜で層間絶縁膜を
形成していたのを1000Åの第１プラズマCVD窒
化膜と、SOG膜と、9000Åの第２プラズマCVD
窒化膜との３層で層間絶縁膜を形成することで従
来多発していた第１層Al配線と第２層Al配線の
シヨート不良はなくなつた。 Thereafter, a second plasma CVD silicon nitride film 4-2 with a thickness of 9000 Å is grown to completely insulate the first Al wiring and the second Al wiring. In this way, conventional 1.0μm
The interlayer insulating film was formed using a plasma CVD nitride film and an SOG film, but now the interlayer insulating film is formed using a 1000 Å first plasma CVD nitride film, an SOG film, and a 9000 Å second plasma CVD film.
By forming an interlayer insulating film with three layers including the nitride film, short defects between the first layer Al wiring and the second layer Al wiring, which had occurred frequently in the past, were eliminated.
以上説明したように本発明の多層配線構造を用
いると半導体素子の製造歩留りは大幅に向上す
る。 As explained above, when the multilayer wiring structure of the present invention is used, the manufacturing yield of semiconductor devices is greatly improved.
なお、本発明においてはAl合金の配線を使う
ことも可能で、また乙層配線のみならず、３層、
４層のいわゆる多層に拡張できることは言うまで
もない。第１の窒化シリコン膜の厚さを300Å乃
至2000Åにすることが、配線内の不純物透過から
好ましい。 In addition, in the present invention, it is also possible to use Al alloy wiring, and not only layer B wiring but also three-layer wiring,
Needless to say, it can be expanded to four layers, so-called multilayers. It is preferable that the thickness of the first silicon nitride film is 300 Å to 2000 Å from the viewpoint of impurity penetration into the wiring.
第１図は従来の構造を示す断面図、第２図は従
来の構造に見られる欠陥を示す断面図、第３図は
本発明の一実施例を示す断面図である。
１……シリコン基板、２……シリコン熱酸化
膜、３……第１層Al配線、４……プラズマCVD
窒化膜、４−１……第１プラズマCVD窒化膜、
４−２……第２プラズマCVD窒化膜、５……
SOG膜、６……第２層Al配線、７……プラズマ
CVD窒化膜の割れ。
FIG. 1 is a sectional view showing a conventional structure, FIG. 2 is a sectional view showing defects found in the conventional structure, and FIG. 3 is a sectional view showing an embodiment of the present invention. 1... Silicon substrate, 2... Silicon thermal oxide film, 3... First layer Al wiring, 4... Plasma CVD
Nitride film, 4-1...first plasma CVD nitride film,
4-2... Second plasma CVD nitride film, 5...
SOG film, 6... Second layer Al wiring, 7... Plasma
Cracks in CVD nitride film.
Claims (1)
ルミニウム配線層と、該第１のアルミニウム配線
層を覆つて設けられ、膜厚が300〜2000Åのプラ
ズマCVD法による第１の窒化シリコン膜と、該
第１の窒化シリコン膜上に設けられたSOG膜と、
該SOG膜上に設けられた第２の窒化シリコン膜
と、該第２の窒化シリコン膜上に設けられた第２
のアルミニウム配線層とを有することを特徴とす
る半導体装置。 ２ 半導体基板の一主面上に第１のアルミニウム
配線層を設ける工程と、膜厚が300〜2000Åの第
１の窒化シリコン膜を、該第１のアルミニウム配
線層を覆つてプラズマCVD法により設ける工程
と、該第１の窒化シリコン膜上にSOG膜を形成
する工程と、該SOG膜を焼き締めるための熱処
理を行なう行程と、該SOG膜上に第２の窒化シ
リコン膜を設ける工程と、該第２の窒化シリコン
膜上に第２のアルミニウム配線層を設ける工程と
を有することを特徴とする半導体装置の製造方
法。[Claims] 1. A first aluminum wiring layer provided on one main surface of a semiconductor substrate, and a plasma CVD method provided covering the first aluminum wiring layer with a film thickness of 300 to 2000 Å. a first silicon nitride film; an SOG film provided on the first silicon nitride film;
a second silicon nitride film provided on the SOG film; and a second silicon nitride film provided on the second silicon nitride film.
1. A semiconductor device comprising: an aluminum wiring layer; 2. Providing a first aluminum wiring layer on one main surface of the semiconductor substrate, and providing a first silicon nitride film with a thickness of 300 to 2000 Å by plasma CVD to cover the first aluminum wiring layer. a step of forming an SOG film on the first silicon nitride film, a step of performing heat treatment to bake and tighten the SOG film, and a step of providing a second silicon nitride film on the SOG film; A method of manufacturing a semiconductor device, comprising the step of providing a second aluminum wiring layer on the second silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11202783A JPS604239A (en) | 1983-06-22 | 1983-06-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11202783A JPS604239A (en) | 1983-06-22 | 1983-06-22 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS604239A JPS604239A (en) | 1985-01-10 |
| JPH0324784B2 true JPH0324784B2 (en) | 1991-04-04 |
Family
ID=14576160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11202783A Granted JPS604239A (en) | 1983-06-22 | 1983-06-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS604239A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63258043A (en) * | 1987-04-15 | 1988-10-25 | Nec Corp | Manufacture of semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5633899A (en) * | 1979-08-29 | 1981-04-04 | Cho Lsi Gijutsu Kenkyu Kumiai | Method of forming multilayer wire |
| JPS5886746A (en) * | 1981-11-19 | 1983-05-24 | Nec Corp | Semiconductor device |
-
1983
- 1983-06-22 JP JP11202783A patent/JPS604239A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5633899A (en) * | 1979-08-29 | 1981-04-04 | Cho Lsi Gijutsu Kenkyu Kumiai | Method of forming multilayer wire |
| JPS5886746A (en) * | 1981-11-19 | 1983-05-24 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS604239A (en) | 1985-01-10 |
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