JPS5633899A - Method of forming multilayer wire - Google Patents

Method of forming multilayer wire

Info

Publication number
JPS5633899A
JPS5633899A JP10912379A JP10912379A JPS5633899A JP S5633899 A JPS5633899 A JP S5633899A JP 10912379 A JP10912379 A JP 10912379A JP 10912379 A JP10912379 A JP 10912379A JP S5633899 A JPS5633899 A JP S5633899A
Authority
JP
Japan
Prior art keywords
forming multilayer
multilayer wire
wire
forming
multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10912379A
Other languages
Japanese (ja)
Other versions
JPS6337517B2 (en
Inventor
Takahiko Takahashi
Akio Anzai
Kensuke Nakada
Chiyoshi Kamata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHO LSI GIJUTSU KENKYU KUMIAI
Priority to JP10912379A priority Critical patent/JPS5633899A/en
Publication of JPS5633899A publication Critical patent/JPS5633899A/en
Publication of JPS6337517B2 publication Critical patent/JPS6337517B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP10912379A 1979-08-29 1979-08-29 Method of forming multilayer wire Granted JPS5633899A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10912379A JPS5633899A (en) 1979-08-29 1979-08-29 Method of forming multilayer wire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10912379A JPS5633899A (en) 1979-08-29 1979-08-29 Method of forming multilayer wire

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP31198087A Division JPS63158853A (en) 1987-12-11 1987-12-11 Method of forming multilayer interconnection

Publications (2)

Publication Number Publication Date
JPS5633899A true JPS5633899A (en) 1981-04-04
JPS6337517B2 JPS6337517B2 (en) 1988-07-26

Family

ID=14502135

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10912379A Granted JPS5633899A (en) 1979-08-29 1979-08-29 Method of forming multilayer wire

Country Status (1)

Country Link
JP (1) JPS5633899A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58176997A (en) * 1982-04-12 1983-10-17 株式会社日立製作所 Plural layer wiring structure and thermal head
JPS604239A (en) * 1983-06-22 1985-01-10 Nec Corp Semiconductor device
JPS60501931A (en) * 1983-08-01 1985-11-07 アメリカン テレフオン アンド テレグラフ カムパニ− Chip group synchronizer
JPS61292323A (en) * 1985-04-02 1986-12-23 ソーン、イーエムアイ、ノース、アメリカ、インコーポレーテッド Formation of contact window in semiconductor structure
JPS6297421A (en) * 1986-08-12 1987-05-06 Nippon Gakki Seizo Kk Pulse fm detection circuit
JPS62154643A (en) * 1985-12-26 1987-07-09 Matsushita Electronics Corp Manufacture of semiconductor device
JPS6418756U (en) * 1987-07-25 1989-01-30
JPS6418761U (en) * 1987-07-25 1989-01-30
JPH07277U (en) * 1993-06-07 1995-01-06 株式会社勝見商会 Vertical full rotary hook of sewing machine
US5702981A (en) * 1995-09-29 1997-12-30 Maniar; Papu D. Method for forming a via in a semiconductor device
US5719517A (en) * 1993-06-29 1998-02-17 Mitsubishi Denki Kabushiki Kaisha Clock generating circuit for digital circuit operating in synchronism with clock, semiconductor integrated circuit including them, and logical gate used for them

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5323584A (en) * 1976-08-17 1978-03-04 Nec Corp Production of semiconductor device
JPS5365088A (en) * 1976-11-22 1978-06-10 Nec Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5323584A (en) * 1976-08-17 1978-03-04 Nec Corp Production of semiconductor device
JPS5365088A (en) * 1976-11-22 1978-06-10 Nec Corp Semiconductor device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58176997A (en) * 1982-04-12 1983-10-17 株式会社日立製作所 Plural layer wiring structure and thermal head
JPH0324784B2 (en) * 1983-06-22 1991-04-04 Nippon Electric Co
JPS604239A (en) * 1983-06-22 1985-01-10 Nec Corp Semiconductor device
JPS60501931A (en) * 1983-08-01 1985-11-07 アメリカン テレフオン アンド テレグラフ カムパニ− Chip group synchronizer
JPS61292323A (en) * 1985-04-02 1986-12-23 ソーン、イーエムアイ、ノース、アメリカ、インコーポレーテッド Formation of contact window in semiconductor structure
JPS62154643A (en) * 1985-12-26 1987-07-09 Matsushita Electronics Corp Manufacture of semiconductor device
JPH0261169B2 (en) * 1986-08-12 1990-12-19 Yamaha Corp
JPS6297421A (en) * 1986-08-12 1987-05-06 Nippon Gakki Seizo Kk Pulse fm detection circuit
JPS6418756U (en) * 1987-07-25 1989-01-30
JPS6418761U (en) * 1987-07-25 1989-01-30
JPH07277U (en) * 1993-06-07 1995-01-06 株式会社勝見商会 Vertical full rotary hook of sewing machine
US5719517A (en) * 1993-06-29 1998-02-17 Mitsubishi Denki Kabushiki Kaisha Clock generating circuit for digital circuit operating in synchronism with clock, semiconductor integrated circuit including them, and logical gate used for them
US5702981A (en) * 1995-09-29 1997-12-30 Maniar; Papu D. Method for forming a via in a semiconductor device

Also Published As

Publication number Publication date
JPS6337517B2 (en) 1988-07-26

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