JPH03228295A - Shift register circuit - Google Patents

Abstract

PURPOSE:To reduce the power consumption by adding a synchronization control part which controls the synchronization control signal after deciding the states of the input and output signals of a synchronizing shift register part. CONSTITUTION:A synchronization control part 9 includes an exclusive OR circuit 5 which inputs the input signal S1 and the output signal S0 of a synchronizing shift register 4 and outputs an exclusive OR signal SEX and an AND circuit 6 which inputs the signal SEX and an external synchronizing signal SC and outputs a synchronization control signal SA. In such a constitution, the register 4 works only when the signals S1 and S0 of an input terminal 1 and an output terminal 2 have different states from each other. Thus the register 4 does not work when both signals S1 and S0 have the same state and keeps a constant state. Then the power consumption of the register 4 is reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a shift register circuit.

[Conventional technology]

FIG. 3 is a block diagram of an example of a conventional shift register circuit.

This shift register circuit includes a synchronous shift register section 4 having an input terminal 1, an output terminal 2, and a synchronous control signal input terminal 3.

Synchronization signal S is input from the outside to synchronization signal input terminal 3. When input, regardless of the state of input signal Sl of input terminal 1,
The shift register operates as a circuit.

[Problem to be solved by the invention]

The conventional shift register circuit described above has the disadvantage that when a synchronization control signal is input, the shift register operates regardless of the input signal, so connecting a large number of shift registers in series increases power consumption. .

An object of the present invention is to provide a shift register circuit with low power consumption.

[Means to solve the problem]

The shift register of the present invention is a shift register circuit having a synchronous shift register section that shifts an input signal in accordance with a synchronous control signal and outputs an output signal, and inputs an input signal and an output signal of the shift register, an exclusive OR circuit that outputs an altruistic OR signal;
It is constructed by adding a synchronization control section having a NAND circuit or an AND circuit that inputs the logical sum signal and an external synchronization signal and outputs the synchronization control signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

The shift register circuit connects the input terminal 1 and the output terminal 2 of the synchronous shift register section 4 to the respective input terminals of the EX-OR gate 5, and connects the output terminal of the EX-OR gate 5 and the synchronous signal input terminal 7 by AND. a synchronization control section 9 connected to each input terminal of the gate 6 and connecting the output terminal of the AND gate 6 to the synchronization control signal input terminal 3 of the shift register 4;
is added to the conventional block shown in FIG.

In this circuit, when the states of input terminal 1 and output terminal 2 are the same ("H" or "L'"), the output signal SEX of EX-OR gate 5 becomes "L", and the output of EX-OR gate 5 becomes "L". Output signal S of AND gate 6 with signal SEX as input
A is a synchronization signal SC input from the synchronization signal input terminal 7
Regardless, "L" is always input to the synchronous control signal input terminal 3 of the shift register section 4.

Therefore, the shift register section 4 maintains a constant state.

Furthermore, when the states of the signals at input terminal 1 and output terminal 2 are different, the output signal SEX of EX-OR gate 5 is +H1
1, and the output signal SA of the AND gate 6 inputting the output signal SEX of the EX-OR gate 5 is a signal in phase with the synchronization signal Sc input from the synchronization signal input terminal 7. 3 is input.

Therefore, the shift register section 4 operates.

As explained above, the shift register section 4 operates only when the signal states of the input terminal 1 and the output terminal 2 are different; when the signal states are the same, the shift register section 4 does not operate and maintains a constant state. Therefore, the power consumption of the synchronous shift register section 4 is reduced compared to the conventional example.

FIG. 2 is a circuit diagram of a second embodiment of the invention.

The shift register circuit of this embodiment differs from the shift register of the first embodiment in that it includes a synchronous control section 91 using a NAND gate 8 instead of the AND gate 6 of the synchronous control section 9 in FIG. .

With this configuration, when the signals at input terminal 1 and output terminal 2 are in the same state, the output signal SEX of EX-OR gate 5 is “
L becomes 11, EX-OR, output signal SE of gate 5
The output signal SN of the NAND gate 18 which receives X as an input is always "HI+" input to the synchronous control signal input terminal 3 of the shift register section 4, regardless of the synchronous signal input from the synchronous signal input terminal 7.

Therefore, the shift register section 4 maintains a constant state.

Also, when the states of input terminal 1 and output terminal 2 are different, E
The output signal Sε× of the X-OR gate 5 becomes “H”, and E
NAN whose input is the output signal SEX of the X-OR gate 5
The output signal SN of the D gate 8 is the synchronization signal S input from the synchronization signal input terminal 7. A signal having the opposite phase is input to the synchronous control signal input terminal 3 of the shift register section 4.

Therefore, the shift radiator section 4 operates.

As a result of the above, power consumption is reduced similarly to the first embodiment.

This embodiment has the effect of reducing the number of elements compared to the first embodiment by using a NAND gate 8 instead of the AND gate 6.

〔Effect of the invention〕

As described above, the present invention has the effect of reducing power consumption by adding a synchronous control section that determines the states of the input signal and output signal of the synchronous shift register section and controls the synchronous control signal.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the invention, FIG. 2 is a circuit diagram of a second embodiment of the invention, and FIG. 3 is a block diagram of an example of a conventional shift register. DESCRIPTION OF SYMBOLS 1... Input terminal, 2... Output terminal, 3... Synchronous control signal input terminal, 4... Synchronous shift register, 5...
...EX-OR gate, 6...AND gate, 7...
・Synchronization signal input terminal, 8...NAND gate, 9, 9
1...Synchronization control section, S! ...input signal, so...
Output signal, Sc...synchronization signal, SN...NAND signal, SEX...EX-OR output signal.

Claims (1)

[Claims] In a shift register circuit having a synchronous shift register section that shifts an input signal in accordance with a synchronous control signal and outputs an output signal, the input signal and the output signal of the shift register are input, and a neutral OR signal is generated. 1. A shift register circuit comprising: an exclusive OR circuit for output; and a synchronization control section having a NAND circuit or an AND circuit for inputting the OR signal and an external synchronization signal and outputting the synchronization control signal.