JPH01190128A - Decoding circuit - Google Patents

Abstract

PURPOSE:To obtain a decode signal without hazard with simple circuit constitution by forming a ring counter by plural FFs whose trigger terminal receives a clock, applying logic operation to each FF output, and forming the decode signal. CONSTITUTION:A F1 output Q1 of plural FFs F1, F2 whose trigger terminal T receives a clock CLK is fed to a data terminal D of the F2. Then the inverted output Q2 of the final stage F2 is supplied to the data terminal D of the F1 to form a ring counter 1 of shift register constitution. In the logic arithmetic circuit 2, outputs Q1, inverse of Q1, Q2 and inverse of Q2 of the outputs of the F1, F2 are calculated to output decode signals ST0-ST3. Thus, the frequency- division output of the F1, F2 is synchronized and the phase is not deviated, then no hazard takes place in the signals ST0-ST3. It is not required to add a delay element. Thus, the circuit constitution is made simple and the cost is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a decoding circuit used in a signal output section of a fully custom microcomputer.

[Prior Art] Conventionally, as shown in FIG. 3, as a decoding circuit of this type used in the signal output section of a fully custom type microphone, a ripple counter 1' is formed with flip-flops F, F2, and a ripple counter 1' is formed with flip-flops F, F2. The divided outputs Q, , Q, , Q2 . NOR circuit NO1~ which takes the NOR of Q2 and forms the decoded signal ST,~ST)
There was one that was caused by the logical operation circuit 2 consisting of NO1. In addition, as a solution to one of the problems of the conventional example, as shown in FIG.
．． No, is there a buffer as a delay element on one input? B
There was one with + * B 2 added.

[Problem to be Solved by the Invention 1] In the conventional example shown in FIG. ．． Since there is a slight delay in Q, as shown in Figure 14, the NOR circuits No.
There is a problem in that a hazard (whisker-like noise) H occurs in the decoded signals ST, -ST3 that have been logically operated by the logical operation circuit 2 consisting of the following. Therefore, in order to solve this problem, as shown in Fig. 5, a NOR circuit No.
2. It is conceivable to suppress the occurrence of hazard H by inserting buffers Bl and B2 into one input of NO, and adjusting the phase, but this poses a problem of complicating the configuration and increasing cost.

The present invention has been made in view of the above points, and its purpose is to provide a decoding circuit that can obtain a decoded signal without hazards, has a simple circuit configuration, and is inexpensive. It is in.

[Means for Solving the Problems] In order to achieve the above object, the present invention uses an a-default flip-flop to which a clock is input to the trigger terminal, and inputs the output of the previous stage flip-flop to the data terminal of the subsequent stage flip-flop. A ring counter is formed by connecting a shift register so that the inverted output of the final stage flip-flop is input to the data terminal of the first stage flip-flop.
A logic operation circuit is provided that performs logic operations on the outputs of each flip-flop and outputs a decoded signal.

[Function] According to the present invention, a ring counter having a shift register configuration is formed by a plurality of flip-flops to which a clock is input to the transistor 707, and a decode signal is generated by a logical operation circuit that performs a logical operation on the output of each 7-rip 707 flip-flop. The divided outputs from each flip-flop are synchronized and there is no phase shift, so even when logical operations are performed, /% Zard does not occur and there is no hazard. Since a decode signal can be obtained and there is no need to add a delay element for phase adjustment, it is possible to provide a decode circuit with a simple circuit configuration and low cost.

[Embodiment] FIG. 1 shows an embodiment of the present invention, in which a plurality of flip-flops F to which a clock CLK is input to the trigger terminal T are shown.
,, F2 is inputted from the 7-rib 70-tube F1 output Q1 in the previous stage to the data terminal 〇 of the flip-flop F2 in the latter stage,
A ring counter 1 is formed by connecting a shift register so that the inverted output Q2 of the final stage flip-flop F2 is inputted to the data terminal of the first stage flip-flop F1.
A logical operation is performed on each flip-flop F + -F 2 output Q l 1 tatami - 2, Q is arrangement, and a decode signal ST, ~
A logic operation circuit 2 that outputs ST is provided.

In addition, in the embodiment, a 2-bit ring counter 1
However, by adding flip-flops, a multi-bit ring counter 1 can be formed.

In this case, it goes without saying that the logical operation circuit 2 is appropriately designed depending on the required decoded signal.

The operation of the embodiment will be explained below. Now, FIG. 2 shows the clock CLK, each flip-flop F3. Frequency division output Q of F2, , Q, Q2. Q2 and decode signal ST
, ~ST, and the inversion of the divided outputs Q,,Q,,Q,,Q, of each flip-flop F-2F2 constituting the ring counter 1 is the clock CLK.
Since the decoded signals ST, ~ST are supplied in synchronization with the decoded signals ST and ST, there is no phase shift.

Since the hazard H does not occur in the conventional example shown in FIG. The configuration is simpler than the example, and costs can be reduced.

[Effects of the Invention] The present invention is configured as described above, and a ring counter having a shift register configuration is formed by a plurality of flip-flops to which a clock is applied to the trigger terminal, and each flip-flop output is subjected to a logical operation. The decoded signal is formed by a logical operation circuit, and the divided outputs from each flip-flop are synchronized and there is no phase shift, so even if logical operations are performed, a hazard will occur. It is possible to obtain a decoded signal without any hazards, and there is no need to add a delay element for adjusting the phase, so it is possible to provide a decoding circuit with a simple circuit configuration and low cost. effective.

[Brief explanation of the drawing]

@ Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2 is an explanatory diagram of the same operation as above, Figure 3 is a circuit diagram of a conventional example, Figure 4 is an explanatory diagram of the same operation as above, and Figure 5 is another conventional example. FIG. 2 is a circuit diagram of an example main part. 1 is the ring counter, 2 is the Mi embedded circuit, FI t
F2 is a flip-flop, and No. -No.4 are NOR circuits. Agent Patent Attorney Ishi 1) Ai Shichi

Claims (1)

[Claims] (1) For multiple flip-flops with a clock input to the trigger terminal, input the output of the previous stage flip-flop to the data terminal of the latter stage flip-flop, and send the inverted output of the last stage flip-flop to the data terminal of the first stage flip-flop. What is claimed is: 1. A decoding circuit characterized in that a ring counter is formed by connecting a shift register so as to be input to the input signal, and a logical operation circuit is provided for logically calculating the output of each flip-flop and outputting a decoded signal.