JPH0149238B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technical field to which the invention pertains The present invention relates to a predictive encoding circuit, and particularly to a predictive encoding circuit used for digital signal processing of color television signals.

(2) Description of the Prior Art Conventionally, this type of predictive coding circuit has been required to perform two operations, quantization and addition, during one time slot, as shown in FIG. Therefore, this circuit configuration has the disadvantage that it is difficult to perform these arithmetic operations without using fast-speed elements.

(3) Description of the purpose of the invention The present invention provides a margin for the delay time of the critical path by delaying the clock input of the register at the final stage of the critical path and changing the order of operations of the limiter and register that follow this. This is what we are trying to do.

(4) Structure of the invention In FIG. 1 showing a conventional predictive encoding circuit, a delay circuit is inserted between the clock of register 9 and the clock of register 11 at the final stage of the critical path, and The order of operations is changed so that the signal path is in the order of register 9 -> register 11 -> limiter 10 -> register 12.

(5) Description of Embodiments Next, embodiments of the present invention will be described with reference to the drawings. Referring to FIG. 1, a differential circuit B including registers 4, 7, a subtracter 3, and an adder 6 inside
and registers 2, 9, 11, 12, 13, on the outside
14, a limiter 10, a subtracter 1, an adder 8, and a quantizer 5, forming a double difference circuit configuration. Here, the critical path 22 of this predictive encoding circuit starts from register 4, passes through quantizer 5, adders 6 and 8, and ends at register 9. The clock input of register 9 is in phase with the clock input of register 4.

Referring to FIG. 2, the configuration is the same as FIG. 1 except that a delay circuit is inserted between the clock of register 9 and the clock of register 11. Here, the critical path 22 is exactly the same as in FIG. 1, but the clock input to register 9 is delayed from the clock input to register 4.

In FIG. 1, the clock input of register 9 at the final stage of the critical path is in phase with the clock input of register 4, so the delay time of the critical path is from the rising edge of the clock to the rising edge of the next clock, that is, one time slot. must be within the range. In contrast, in FIG. 2, the clock input of register 9 at the final stage of the critical path is higher than the clock input of register 4.
It is delayed by 1. That is, the relationship between the clock and the delayed clock is as shown in FIG. Therefore, the delay time of the critical path only needs to be within the time from the rise of the original clock to the rise of the next clock plus the delay time ΔT of the delay element 21, so there is a margin for the delay time of the delay element 21. can be increased.

However, in FIG. 2, the signal path following the critical path is from register 9 to register 11 via limiter 10. Therefore, the limiter operation by limiter 10 must be performed within the time _T1 from the rising edge of the original clock to the rising edge of the delayed clock.
In other words, the delay time of this path is the time T ₁ obtained by subtracting the delay time ΔT of the delay element 21 from the time from the rise of the original clock to the rise of the next clock.
(Fig. 4), which is disadvantageous in terms of speed. Note that the limiter 10 is necessary to limit the number of digits because the number of digits may increase when the adders 6 and 8 perform addition, and as the number of digits increases, the number of elements to be operated on increases. There is.

In order to solve this problem, in the configuration according to an embodiment of the present invention shown in FIG. 3, the order of operation of the limiter 10 and the register 11 is exchanged. According to this configuration, the limiter 10 operates on the output from the register 11, and the register 11 operates with the original clock. Therefore, limiter 10 only needs to perform its limiting operation within one time slot of the original clock, time T ₄ (FIG. 4), and speed is also improved. In this way, the signal path following the critical path is a path from register 9 to register 11, and the delay time of this path is determined by the register setup time and hold time, so it is usually sufficiently smaller than the critical path. Therefore, by adjusting the delay time of the delay element 21 as in the present invention, the critical path can be made longer than the clock period (the reciprocal of the clock frequency), and as a result, the maximum operable clock frequency can be made longer than the conventional clock frequency. It is possible to make it higher than the circuit. Also, a special example of FIG. 3 is a 0.5 time slot delay, ie, a 180° phase reversal. In this case, an inverter can be used as the delay circuit, which is very easy to implement, and the critical path can be increased by about 1.5 times compared to the conventional circuit.

(6) Description of effects of the invention As explained above, the present invention delays the clock input of the register at the final stage of the critical path, and also changes the order of operations of the limiter and register that follow, thereby reducing the delay time of the critical path. This has the effect of giving a margin to

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional predictive encoding circuit, Fig. 2 is a block diagram showing a delay circuit inserted between the clock of register 9 and register 11 in Fig. 1, and Fig. 3 is a block diagram showing a conventional predictive coding circuit. FIG. 4 is a block diagram in which the order of operation of limiter 10 and register 11 is reversed and the signal path is in the order of register 9→register 11→limiter 10→register 12. FIG. 4 is a signal waveform diagram of the original clock and the delayed clock. In the drawings, 1, 3...subtractor, 5...
...Quantizer, 6, 8... Adder, 10... Limiter, 2, 4, 7, 9, 11, 12, 13, 14...
...Register, 21...Delay element or inverter, 22...Critical path, A...Differential circuit, B...Differential circuit.

Claims (1)

[Claims] 1. A first subtracter that receives input data at one input, a first register that receives the output of this first subtracter, a first adder, a second register that receives the output of this first adder, and a first register that receives the output of this first subtracter. a third register that receives the output; a limiter that receives the output of this third register; a fourth register that receives the output of this limiter and whose output is supplied to the other input of the first subtracter; and receives the output of this fourth register. a fifth register; and a sixth register receiving the output of the fifth register, the output of which is supplied to one input of the first adder, and a first clock is connected to the first and third to sixth registers. a first difference circuit which is supplied to the second register and a second clock delayed from the first clock is supplied to the second register; a second subtracter which receives the output of the first register at one input; a seventh register receiving the output of the subtracter, a second adder whose output is supplied to the other input of the first adder and the first subtracter, respectively;
a second difference circuit having an eighth register receiving the output of the adder and having an output supplied to one input of the second adder; and a second difference circuit having the first clock supplied to the seventh and eighth registers; , and a quantizer whose output is supplied to the other input of the second adder.