JPH10293147A - Clock duty detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock duty detecting circuit having a small circuit scale for detecting the duty of a clock. SOLUTION: A first delay holding means fetches and holds an input clock into and in a first holding section by using a first delayed clock generated by delaying the input clock by a preset period of time t1 . A second delay holding means fetches and holds the input clock into and in a second holding section by using a second delayed clock generated by delaying the input clock by a preset period of time t2 . The decrease/increase of the pulse width of the input clock is detected from the outputting states of the first and second delay holding means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock duty detection circuit for detecting a clock duty.

[0002]

2. Description of the Related Art Conventionally, in a transmission apparatus such as an SDH,
Although the detection of the clock disconnection and the detection of the surplus and missing teeth of the clock are performed, the detection of the duty (pulse width) of the clock is not performed.

However, the duty (pulse width) of the clock is a problem directly related to the quality of the device, and may cause erroneous data detection depending on the amount of change in the pulse width.

[0004]

Therefore, there is a problem of how to realize the detection of the duty of the clock with a small circuit scale and a circuit configuration which does not cause much problem in performance.

An object of the present invention is to provide a duty detection circuit having a small circuit scale.

[0006]

FIG. 1 is a diagram (1) for explaining the principle of the present invention, (a) is a diagram for explaining the principle of the first present invention,
(B) is a diagram for explaining the principle of the second invention, FIG. 2 is a diagram (2) for explaining the principle of the invention, (a) is a diagram for explaining the principle of the third invention, and (b) is a diagram for explaining the fourth invention. FIG. 3 is a diagram for explaining the principle of the present invention, FIG. 3 is a diagram for explaining the principle of the present invention (part 3), (a) is a diagram for explaining the principle of the fifth present invention, (b) is a diagram for explaining the principle of the sixth present invention, FIG.
FIG. 17 is an explanatory view of the principle of the seventh invention.

According to a first aspect of the present invention, an input clock is taken into a first holding portion by using a change point of a first delay clock generated by delaying the input clock by a preset time t _1. A first delay / hold means for holding is provided.

Then, a decrease in the pulse width of the input clock is detected from the output state of the first delay / hold means. In other words, the first delay / hold means delays the input clock by the time t ₁ to generate the first delay clock, and outputs the first delay clock output from the first delay portion. And a first holding portion that takes in and holds an input clock using a transition point (rising edge).

With such a configuration, when the pulse width of the input clock decreases, it is possible to detect the decrease in the pulse width in the first holding portion using the rising edge of the delay clock.

According to a second aspect of the present invention, a first delay clock generated by delaying an input clock by a preset time t ₁ is used to capture and hold the input clock in a first holding portion. And a second delay clock that captures and holds the input clock in a second holding portion using a second delay clock generated by delaying the input clock by a preset time t _2. A holding means is provided.

Then, a configuration is employed in which a decrease / increase in the pulse width of the input clock is detected from the output states of the first and second delay / hold means. In other words, the first delay / holding means is composed of a first delay part and a first holding means for taking in and holding an input clock using the first delay clock output from the first delay part. , The second delay / hold means uses a second delay portion for delaying the input clock by the time t ₂ to generate a second clock, and a second delay clock output from the second delay portion. , And a second holding portion that takes in and holds an input clock.

With such a configuration, when the pulse width of the input clock decreases / increases, the decrease or increase of the pulse width is detected in the first and second holding portions using the first and second delay clocks. be able to.

According to a third aspect of the present invention, the second delayed clock is:
The first delay clock is configured to be further delayed by a time (t ₂ −t ₁ ). In other words, a first delay part for delaying the input clock by the time t _{1 and} a third delay part for delaying the input clock by the time (t ₂ −t ₁ ) are connected in series, and the input clock is delayed by the time t ₂ obtained by the configuration in which the delay can be reduced circuit scale of the delay portions for generating a delay time of the time t _2.

According to a fourth aspect of the present invention, there is provided a coincidence detecting means for performing coincidence detection between the first divided delay clock and the divided input clock which is generated by dividing the first delayed clock and the input clock by n. Provide.

The input clock is fetched and held in the first and second holding parts by using the output of the coincidence detecting means and the delay output obtained by delaying the output of the coincidence detecting means by the time t _2. did.

That is, the coincidence detecting means includes a first delay portion for generating a first delay clock, a frequency-divided output of the input clock (for example, n = 2), and a frequency-divided output of the first delay clock. (E.g., n = 2) is provided with an exclusive NOR part for detecting the coincidence part, and the output of the coincidence detection means and the time t ₂
The input clock is fetched and held in the first holding portion and the second holding portion by using the output of the coincidence detecting means delayed by only a predetermined time.

With such a configuration, when the pulse width of the input clock decreases / increases, the delay time of t ₁ and t ₂ causes
The decrease / increase of the pulse width can be detected in the first and second holding portions.

Further, similarly to the third aspect of the present invention, the first and the second
Are connected in series, the delay time of the second delay part can be reduced. Further, by applying a high-speed device (FF or the like) to the frequency-divided portion in the coincidence detecting means, malfunctions in the first and second holding portions can be prevented even when the input clock pulse width is reduced. it can.

According to a fifth aspect of the present invention, an inverting means for inverting an input clock is provided. Then, a first delay-holding means, the inverting input clock inversion means has transmitted is generated by delaying by a time t _1, as to capture, hold input clock using a change point of the first inversion delay clock Is configured.

With such a configuration, when the pulse width of the input clock increases, the increase in the pulse width can be detected in the first holding portion. According to a sixth aspect of the present invention, the output of the first delay / hold means and the second delay /
The inverted output of the holding means is applied to the NAND means. And
The configuration is such that the decrease / increase of the pulse width of the input clock is detected from the output state of the NAND means.

With such a configuration, "H" is output when the clock pulse decreases / increases to indicate an abnormality, and "L" can be output when the clock pulse is normal. According to a seventh aspect of the present invention, the clock duty detecting circuit according to the sixth aspect outputs a logical sum means for calculating a logical sum of the first delayed input clock and the input clock, and outputs a mismatch between the first delayed clock and the input clock. A pulse width having exclusive OR means and selecting / dividing means for selecting one of the outputs of the OR means and the exclusive OR means and dividing the frequency by n to correct the pulse width It is configured to add a correction means.

With such a configuration, when the clock duty detecting circuit determines that the pulse width of the input clock is abnormal, the pulse width is changed from the selecting / dividing means to the output state of the first delay / hold means. A corrected clock can be transmitted.

[0023]

FIG. 5 is a block diagram of a main part of a first embodiment of the present invention. FIGS. 6A and 6B are explanatory diagrams of the operation of FIG. 5. FIG. 5A shows a normal state, and FIG. FIG. 7 is a diagram showing the main part of the second embodiment of the present invention, FIG. 8 is an explanatory diagram (part 1) of the operation of FIG. 7, and FIG. 9 is an explanatory diagram (part 2) of the operation of FIG.
(a) is when the pulse width is reduced, and (b) is when the pulse width is increased.

FIG. 10 is a diagram showing a main part of a third embodiment of the present invention, FIG. 11 is an explanatory diagram (part 1) of the operation of FIG. 10, and FIG. 12 is an explanatory diagram (part 2) of the operation of FIG. a) when the pulse width decreases, and (b) when the pulse width increases.

FIG. 13 is a block diagram of the main part of the fourth embodiment of the present invention, FIG. 14 is an explanatory diagram (part 1) of FIG. 13, and FIG. 15 is an explanatory diagram (part 2) of FIG. a) when the pulse width decreases, and (b) when the pulse width increases.

FIG. 16 is a diagram showing the construction of the main part of a fifth embodiment of the present invention, and FIG. 17 is a diagram for explaining the operation of FIG.
FIG. 18B is a diagram showing a main part of the sixth embodiment of the present invention, FIG. 19 is an operation explanatory diagram of FIG. 18 (part 1), and FIG. 20 is an operation explanatory diagram of FIG. (Part 2)
(A) shows a case where the pulse width is reduced, and (b) shows a case where the pulse width is increased.

FIG. 21 is a diagram showing the main parts of a seventh embodiment of the present invention, FIG. 22 is an explanatory diagram (part 1) of the operation shown in FIG. 21, FIG. 23 is an explanatory diagram (part 2) of the operation shown in FIG. FIG. 22 is a diagram (part 3) illustrating the operation of FIG. 21.

Here, the same reference numerals indicate the same objects throughout the drawings. Note that the circled numbers in the main part configuration diagram indicate the waveforms of the same circled numbers in the operation explanatory diagram. Hereinafter, FIG.
24 to FIG. 24, in the following description, the input clock (hereinafter abbreviated as CLK) is delayed by t ₁
The rising point of LK (hereinafter referred to as delay input CLK)
Captures the level of "H" substantially central portion of the level of the input CLK of normal, rising point of the delay clock obtained by delaying the input CLK by a time t _2, the input CLK of the normal "L" of the substantially central portion of the level Assume that the level is taken in.

The operation of FIG. 5 will be described with reference to FIG. When the pulse width of the input CLK is in a normal state, the delay CLK delayed by the time t _{1 in the} delay line 111 is FF
211 is applied to a second input terminal.

On the other hand, the input CLK is applied to the first input terminal of the FF 211, but is punched out at the rising point of the delay clock. Therefore, the Q output transmitted from the first output terminal of the FF 211 becomes “H” (FIG. 6A).
reference).

However, when the pulse falling side is decreasing (as indicated by the left arrow in the dotted line in FIG. 6B),
It is assumed that it has decreased to the solid line),
Cannot be punched out, the Q output of the FF 211 becomes “L”, and a decrease in pulse width is detected (FIG. 6B).
−−).

The operation of FIG. 7 will be described with reference to FIGS. 8 and 9. In FIG. 7, reference numeral 111 denotes a delay line delayed by a time t ₁ , 112 denotes a delay line delayed by a time t ₂ ,
211 and 212 are flip-flops (hereinafter referred to as F
F).

Now, as shown in FIG. 8-, when CLK having a normal pulse width is input to the delay line 111 in the clock duty detection circuit, C which is delayed by time t ₁ is output.
LK (hereinafter abbreviated as first delay CLK) is FF21
1 to the second input terminal.

The above-mentioned CLK is applied to the delay line 11.
2, CLK delayed by time t ₂ (hereinafter referred to as CLK)
A second delay CLK is applied to a second input terminal of the FF 212 (refer to the left side of FIG. 8).

On the other hand, since the input CLK is applied to the first input terminals of the FF 211 and the FF 212, the input CLK is punched by the first delay CLK or the second delay CLK.

As a result, the input CLK is delayed by the first delay CLK.
Is punched out, the output of the first output terminal of the FF 211 (hereinafter abbreviated as Q output) becomes “H”, and when punched out with the second delay CLK, the Q output of the FF 212 is “L”.
(See FIG. 8-).

Further, the pulse width is reduced, for example, as shown in FIG.
(A) -CLK shown in-is FF 211, FF 212
When applied to the first input terminal, the first delay CLK and the second delay CLK cannot each punch out the input CLK (see FIG. 9A-).

As a result, the Q outputs of the FFs 211 and 212 each become "L" (see FIG. 9A). Conversely, the pulse width increases, for example, as shown in FIG.
-Is the first of FF211 and FF212.
, The first delay CLK and the second delay CLK can both punch out the input CLK (see FIG. 9B-).

Therefore, the Q outputs of the FFs 211 and 212 both become "H" (see FIG. 5B-). The operation of FIG. 10 will be described with reference to FIGS.

As shown in FIG. 10, the delay clock applied to the second input terminal of the FF 213 is the delay line 11
Although the signal passes through two delay lines 1 and 1, the delay time of the delay line 113 is (t ₂ −t ₁ ) so that the entire delay time is t ₂ .

As a result, the delay time of the delay line 113 is reduced, and the configuration of the delay line 113 is reduced. That is, when the pulse width is normal, the output of the delay line 111 takes time t with respect to the input CLK.
Only ₁ delayed addition, the output of the delay line 111 and delay line 113 is output with a delay by a time t ₂ to the input CLK.

On the other hand, FF 211 and FF 213 are input CLs.
K is punched out by CLK delayed by time t ₁ and time t ₂ , respectively. Therefore, in the CLK having the normal pulse width, the Q output of the FF 211 becomes “H” and the FF 211
The Q output of 213 becomes “L” (see FIG. 11-).

When the pulse width is reduced, the FF 211, F
Since input CLK cannot be punched out in F213,
The Q outputs of the F211 and the FF213 both become “L” (see FIG. 12A).

Conversely, when the pulse width increases, the FF 211, F
Since the input CLK can be punched out in F213,
Both the Q output of the FF 211 and the FF 213 become “H” (FIG. 1)
2 (b) -〜).

The operation of FIG. 13 will be described with reference to FIGS. 14 and 15. In FIG. 13, reference numeral 411 denotes an exclusive NOR circuit.
2 is a delay line, and 213 and 212 are FFs. As shown in FIG. 14 pulse width is normal CLK is, if you type in the delay line 111 is delayed by a time t _1, the second input terminal of the FF311 as the first delay CLK (not shown) I do.

Here, since the FF 311 is connected to a divide-by-two frequency divider, the input CLK delayed by the time t ₁ is divided by two and applied to the second input terminal of the exclusive NOR circuit 411 (FIG. 14). −, See).

Also, the FF 310 is 2 in the same manner as the FF 311.
Since it is a frequency divider, the input CLK is directly frequency-divided by two and applied to the first input terminal of the exclusive NOR circuit 411 (see FIG. 14-).

As a result, an output as shown in FIG. 14- is taken out from the exclusive NOR circuit 411, a part of the output is directly applied to the second input terminal of the FF 213, and the remaining output is the delay time t ₂ Through delay line 112 of F
It is applied to the second input terminal of F212.

Since the input CLK is applied to the first input terminals of the FFs 213 and 212, the rising of the output of the exclusive NOR circuit applied to the second input terminal and the exclusion through the delay line 112 are performed. The output is taken into the FFs 213 and 212 using the rising edge of the output of the logical NOR circuit, and as the Q output, “H” as shown in FIG.
An "L" output is obtained.

On the other hand, when the pulse width is reduced, for example, as shown in FIG.
When a CLK as shown in FIG. 15A is input to the FF 310, an output as shown in FIG. 15A is applied from the FF 310 to the first input terminal of the exclusive NOR circuit 411.

Similarly, the delay line 111 and the FF 31
The output shown in (a)-of FIG. 15 through 1 is applied to the second input terminal of the exclusive NOR circuit 411. Therefore, an output shown in FIG. 15A is obtained from the exclusive NOR circuit 411, and a part of this output is the second output of the FF 213.
Of applying a CLK input terminal, the remainder is applied as CLK to the second input terminal of the FF212 through the delay line 112 of the time t ₂ (FIG. 15 (a) - see).

On the other hand, since the input CLK as shown in FIG. 15A is applied to the first input terminals of the FFs 212 and 213, the output of the FF 213 is "L" and the output of the FF 212 is "L".
Also becomes "L" (see FIG. 15 (a)-).

Conversely, when the pulse width increases, FF213, FF
At 212, the input CLK can be punched out (FIG. 15).
(B)-see). Therefore, FF213, FF21
The Q output of each of these becomes "H" (FIG. 11-,
reference).

The operation of FIG. 16 will be described with reference to FIG.
When the pulse width is normal, the input CLK is applied to the first input terminal of the FF 211, the input CLK is inverted to the second input terminal by the inverting circuit 412, and the inverted delay is delayed by the time t _{1 in the} delay line 111. CLK is applied.

Then, the input CLK is punched out at the rising edge of the inverted delay CLK, and the Q output of the FF 211 becomes "H" (see FIG. 17 (a)-). At the time of the pulse rising side decrease, since the input CLK cannot be punched out by the output of the delay line 111 in the FF 211, the Q output of the FF 211 becomes “L” (FIG. 17).
(B)-see).

The operation of FIG. 18 will be described with reference to FIGS. 19 and 20. It is assumed that the holding circuits 211 and 212 are configured by FFs. Now, the pulse width is normal CLK is applied to a second input terminal of the FF211 as the first delay CLK delayed by the entering time t ₁ to the delay line 111, only t ₂ by entering the delay line 112 delays Then, it is applied to the second input terminal of the FF 212 as a second delay CLK (see FIG. 19-).

Therefore, the FF 211 punches out the input CLK with the first delay CLK, and the FF 212 punches out the input CLK with the second delay CLK. As a result, FF21 in normal operation
1 is "H", the inverted Q (XQ) output of the FF 212 is "H", and the output of the NAND circuit 413 is "L" (see FIG. 19-).

On the other hand, when the pulse width is reduced, the FF 211, 2
12, the input CLK cannot be punched out.
11 is "L", and the XQ output of FF212 is "H".
The output of the NAND circuit 413 becomes “H”, and it is detected that the pulse width of the input CLK is abnormal (FIG. 2).
0 (a) -〜).

When the pulse width is increased, the FF 211
Since the input CLK can be punched out at 212, FF2
11 is "H", and the XQ output of FF212 is "L".
20 and the output of the NAND gate circuit 413 becomes "H" to detect that the pulse width is abnormal (FIG. 20).
(B)-see).

The operation of FIG. 21 will be described with reference to FIGS. Note that the parts of the delay circuits 111 and 112, the holding circuits 211 and 212, and the NAND circuit 413 in FIG.
The configuration is the same as that of FIG.
The R circuit 415, the selector 416, and the holding circuit 312 are a pulse width correction part.

The same parts as those shown in FIG. 18 will be described briefly. The delay line 111 receives the input CLK
Is delayed by the time t ₁ , and the delay line 112 delays the input CLK by the time t ₂ , and the first delay C
LK, and outputs it as a second delay CLK.

The FFs 211 and 212 have a first delay C
The input CLK is punched out using the LK and the second delay CLK. Now, the input CLK whose pulse width is normal
, The Q output of the FF 211 is “H”,
The output "H", the output of the NAND circuit 413 to become the "L", the selector circuit 417 selects and outputs the input CLK (see FIG. _22-1-3).

On the other hand, when the pulse width decreases, the FF 211,
Since it is not possible to punch out the input CLK at 212, FF
The Q output of 211 is “L”, the XQ output of FF 212 is “H”, the output of NAND circuit 413 is “H”, and it is detected that the pulse width of input CLK is abnormal (see FIG. 23-). .

At this time, the input CLK is output from the OR circuit 414.
And the OR output of the first delay CLK is applied to the selector 416 (see FIG. 23-). Also, exclusive O
From the R circuit 415, the input CLK and the second delay CLK
Is also applied to the selector 416 (FIG. 2).
3-,).

When the output state of the FF 211 is “L” (when the pulse width is reduced, the selector 416 becomes “L”).
And select the output of the R circuit 414 and sends it to the Ff312 (see Figure 23- _1).

[0066] FF312 Since constitute a 1/2 frequency divider, expanding the pulse width by 2 divides the output of the OR circuit input is sent to the selector 417 (see FIG. _23-2).
Therefore, the selector 417 selects the output of the FF 312 because the detection result of the NAND circuit 413 indicates “H” indicating an abnormality, and outputs the CLK having the increased pulse width (FIG. 2).
See _3-3).

Conversely, when the pulse width increases, the FF 211
Since the input CLK can be punched out at 212, FF2
11 is "H", and the XQ output of FF211 is "L".
, And the output of the NAND circuit 413 becomes “H”, thereby detecting that it is abnormal.

Therefore, the operations of the OR circuit 414 and the exclusive OR circuit 415 operate in the same manner as when the pulse width is reduced. In the selector 416, the output of the FF 211 becomes "H", and the output of the exclusive OR circuit 415 is selected. Is output.

The FF 312 divides the frequency of the input clock ₁ by 2 to reduce the pulse width, and sends the clock ₁ to the selector 417. Since the detection result of the NAND circuit 413 is “H”, the output of the FF 312 is selected, and the selector 417 outputs CLK with a reduced pulse width (see FIGS. 24 to ₃ ).

[0070]

As described above, according to the present invention, there is an effect that a duty detection circuit having a small circuit scale can be provided.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams illustrating the principle of the present invention (part 1), wherein FIG. 1A is a diagram illustrating the first principle of the present invention, and FIG.

FIGS. 2A and 2B are diagrams illustrating the principle of the present invention (part 2), wherein FIG. 2A is a diagram illustrating the third principle of the present invention and FIG.

FIGS. 3A and 3B are diagrams illustrating the principle of the present invention (part 3), wherein FIG. 3A is a diagram illustrating the principle of the fifth embodiment of the present invention, and FIG.

FIG. 4 is a diagram illustrating the principle of the seventh invention.

FIG. 5 is a configuration diagram of a main part of the first embodiment of the present invention.

6A and 6B are explanatory diagrams of the operation of FIG. 5, in which FIG.
Is when the pulse falling side is decreasing.

FIG. 7 is a configuration diagram of a main part of a second embodiment of the present invention.

FIG. 8 is a diagram (part 1) illustrating the operation of FIG. 7;

9A and 9B are diagrams illustrating the operation of FIG. 7 (part 2), in which (a) shows a case where the pulse width is reduced and (b) shows a case where the pulse width is increased.

FIG. 10 is a configuration diagram of a main part of a third embodiment of the present invention.

11 is a diagram (part 1) illustrating the operation of FIG.

FIGS. 12A and 12B are explanatory diagrams (part 2) of the operation of FIG. 10, in which FIG. 12A shows a case where the pulse width is reduced and FIG. 12B shows a case where the pulse width is increased.

FIG. 13 is a configuration diagram of a main part of a fourth embodiment of the present invention.

FIG. 14 is an operation explanatory view (part 1) of FIG. 13;

FIGS. 15A and 15B are explanatory diagrams (part 2) of the operation in FIG. 13, in which (a) shows a case where the pulse width is reduced and (b) shows a case where the pulse width is increased.

FIG. 16 is a configuration diagram of a main part of a fifth embodiment of the present invention.

FIG. 17 is an operation explanatory diagram of FIG. 16, where (a) is normal and (b)
Is when the pulse rising side is decreasing.

FIG. 18 is a configuration diagram of a main part of a sixth embodiment of the present invention.

FIG. 19 is a diagram (part 1) illustrating the operation of FIG. 18;

20 is a diagram (part 2) of the operation of FIG. 18, in which (a) shows a case where the pulse width is reduced, and (b) shows a case where the pulse width is increased.

FIG. 21 is a configuration diagram of a main part of a seventh embodiment of the present invention.

FIG. 22 is an operation explanatory diagram (part 1) of FIG. 21;

FIG. 23 is a diagram (part 2) for explaining the operation in FIG. 21;

FIG. 24 is an operation explanatory view (3) of FIG. 21;

[Explanation of symbols]

 111, 112, 113 Delay lines 211, 212, 213 Flip-flops 310, 311 Divider 411 EX-NOR 412 Inverting circuit 413 NAND circuit 414 OR circuit 415 EX-OR circuit 416, 417 Selector

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Nobuyuki Kobayashi 2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture Fujitsu Digital Technology Co., Ltd. In-house (72) Inventor Hiroyuki Ogaki 4 Kamikadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Chome 1-1 Fujitsu Limited

Claims (7)

[Claims] An input clock is set to a predetermined time t _1.
First delay / hold means for taking in and holding the input clock in a first holding part by using a change point of the first delay clock generated by delaying the first delay clock; A clock duty detecting circuit configured to detect a decrease in the pulse width of the input clock from the output state of the clock. 2. Using the first delay clock generated with a delay time t ₁ set in advance the input clock, first to capture, hold input clock to the first holding portion
Delay and holding means, and a predetermined time t ₂ (t ₂ > t ₁ ) for the input clock.
Second delay / hold means for taking in and holding the input clock in a second holding portion by using a second delay clock generated by delaying only the first and second delay / hold means A clock duty detection circuit configured to detect a decrease / increase of the pulse width of the input clock from the output state of the clock duty detection circuit. 3. The apparatus according to claim 2, wherein the second delay clock is configured to generate the first delay clock by further delaying the first delay clock by a time (t ₂ −t ₁ ). Clock duty detection circuit. 4. A first delay clock and an input clock generated by dividing the first delay clock and the input clock by n (n is a positive integer).
Dividing provided coincidence detection means detects a coincidence of the delayed clock and the divided input clock, using an output of the coincidence detection means, it outputs a delayed output obtained by delaying the time t ₂ of the coincidence detection means, 3. The clock duty detection circuit according to claim 2, wherein said input clock is fetched and held in said first and second holding portions. 5. providing inverting means for inverting the input clock, in the first delay-holding means, and the inverted input clock said inverting means is sent generated with a delay time t _1, the first
Wherein the input clock is fetched and held by using the change point of the inverted delay clock of the above (1), and an increase in the pulse width of the input clock is detected from the output state of the first delay / hold means. Item 2. The clock duty detection circuit according to Item 1. 6. An output of said first delay / hold means and an inverted output of said second delay / hold means are applied to a NAND means, and a pulse width of an input clock is reduced / increased from an output state of said NAND means. 3. The clock duty detecting circuit according to claim 2, wherein the clock duty detecting circuit detects the clock duty. 7. The clock duty detection circuit according to claim 6, wherein: a logical sum means for calculating a logical sum of the first delay clock and the input clock; and an exclusive unit for outputting a mismatch between the first delay clock and the input clock. OR means, and one of the outputs of the OR means and the exclusive OR means is selected,
a pulse width correcting means having a selecting / dividing means for correcting the pulse width by dividing by n; and selecting and dividing means when the clock duty detecting circuit determines that the pulse width of the input clock is abnormal. From the first
A clock having a pulse width corrected in accordance with the output state of the delay / hold means.