JP3770378B2 - Phase comparison circuit - Google Patents

Description

で示すことができる。ここで、ｔＤ１はフリップフロップ回路ＦＦ３に供給するクロック信号を遅延する遅延回路Ｄ１の遅延時間である。さらに、ｔ２はフリップフロップ回路ＦＦ１においてクロック信号ＣＩが立ち上がってから反転データ出力信号ＱＮが出力するまでの遅延である。（４）式のΔｔｄｏｗｎを０にする遅延ｔＤ３を発生することにより、ＤＯＷＮ信号が正確にクロック周期Ｔの１／２の幅を示すように設計可能となる。また、遅延回路Ｄ１はフリップフロップ回路ＦＦ１とＦＦ３の間のデータ転送を誤りなく行うに必要な次の条件である、
（ｔ１＋ｔｓｅｔ）＜（ｔＤ１＋Ｔ/２）＜（Ｔ＋ｔ１−ｔｈｏ１ｄ）（５）
を満たすように設定する。ここで、ｔｓｅｔはフリップフロップ回路ＦＦ３のデータセットアップ時間、ｔｈｏ１ｄはフリップフロップ回路ＦＦ３のデータホールド時間である。
【００２６】
加えて、ＵＰ信号の降下時点とＤＯＷＮ信号の立ち上がり時点は、遅延回路Ｄ４により等しくすることが可能になる。遅延回路Ｄ４を排他的論理和回路ＥＸＯＲ１の出力ラインに挿入することにより、ＵＰ信号に遅延回路Ｄ４の発生する遅延時間ｔＤ４を付加する。この遅延時間ｔＤ４を次式
ｔ２＋ｔＤ３＋tdE23LH＝ｔ１＋tdE12LL＋ｔＤ４ （６）
を満足する値に設計することにより、ＵＰ信号の降下時点とＤＯＷＮ信号の立ち上がり時点が等しくなる。
【００２７】
したがって、本実施形態によると、フリップフロップ回路ＦＦ１とＦＦ３の回路遅延ｔ１，ｔ２，ｔ３および排他的論理和回路ＥＸＯＲ１とＥＸＯＲ２の回路遅延tdE12LL，tdE11LH，tdE24LL，tdE23LHにより生じる位相出力誤差を、遅延回路Ｄ２，Ｄ３の遅延により０に近づけることが可能となる。また、遅延回路Ｄ１により、フリップフロップ回路ＦＦ１とＦＦ３間のデータ転送のタイミング余裕が確保されるとともに、遅延回路Ｄ１の遅延による位相出力誤差も位相回路Ｄ２，Ｄ３により０に近づけることができる。そして、ＵＰ信号とＤＯＷＮ信号の立ち上がり時点と降下時点を遅延回路Ｄ４により一致させることが可能となる。
【００２８】
本実施形態においては、位相信号Ｅ３をフリップフロップ回路ＦＦ３の反転データ出力端子ＱＮから出力している点が、従来の実施例と異なる。フリップフロップ回路ＦＦ１のデータ出力端子Ｑから、位相信号Ｅ２、Ｅ３をとり（但し、位相信号Ｅ３については反転遅延回路Ｄ３と同様な遅延をもつ遅延回路（第３の遅延回路）を介在させてから取り出す。）、さらにフリップフロップ回路ＦＦ３の入力をとることも可能であり、同様に動作するが、このようにすると、そのデータ出力端子Ｑの出力負荷が大きくなり高速な信号転送が困難になる問題がある。よって、本実施形態では、フリップフロップ回路ＦＦ１の出力信号を、データ出力端子Ｑと反転データ出力端子ＱＮの双方からとることにより、出力負荷を分散した。このことにより、本実施形態の位相比較回路は、従来の位相比較回路に比べ、より高速な動作が可能となる。
【００２９】
［第２の実施形態］
本発明の第２の実施形態を図３を用いて説明する。本実施形態の位相比較回路は、位相検出部３と位相差出力部４からなる。位相差出力部４が第１の実施形態の位相差出力部２と異なる点は、排他的論理和回路ＥＸＯＲ１をＮＡＮＤ回路Ｎ１，Ｎ２，Ｎ３で構成した排他的論理和回路（第３の排他的論理和回路）に置換し、排他的論理和回路ＥＸＯＲ２をＮＡＮＤ回路Ｎ４，Ｎ５，Ｎ６で構成した排他的論理和回路（第４の排他的論理和回路）に置換し、位相信号Ｅ１，Ｅ２，Ｅ３，Ｅ４に加えて、それらの反転信号である反転位相信号Ｅ１Ｎ，Ｅ２Ｎ，Ｅ３Ｎ，Ｅ４Ｎを用いることである。
【００３０】
また、位相検出部３が第１の実施形態の位相検出部１と異なる点は、上記の反転位相信号Ｅ１Ｎ，Ｅ２Ｎ，Ｅ３Ｎ，Ｅ４Ｎを発生するため、データ入力信号ＤＩに加えて反転データ入力信号ＤＩＮを入力し、フリップフロップ回路ＦＦ２（第３のフリップフロップ回路）とフリップフロップ回路ＦＦ４（第４のフリップフロップ回路）を加え、さらに、反転位相信号Ｅ１ＮとＥ３Ｎの遅延時間を位相信号Ｅ１とＥ３に対する遅延時間とは別に設定するために遅延回路Ｄ２’（第４の遅延回路）と反転遅延回路Ｄ３’（第２の反転遅延回路）を加えた点である。
【００３１】
本実施形態の接続を説明する。位相比較回路の入力であるデータ入力信号ＤＩは、フリップフロップ回路ＦＦ１のデータ入力端子Ｄと遅延回路Ｄ２の入力端子に接続する。位相比較回路の入力である反転データ入力信号ＤＩＮは、フリップフロップ回路ＦＦ２のデータ入力端子Ｄと遅延回路Ｄ２’の入力端子に接続する。位相比較回路の入力であるクロック入力信号ＣＩは、フリップフロップ回路ＦＦ１，ＦＦ２の各クロック入力端子ＣＫとインバータ回路Ｉ１の入力端子に接続する。インバータ回路Ｉ１の出力端子は遅延回路Ｄ１の入力端子に接続し、遅延回路Ｄ１の出力端子はフリップフロップ回路ＦＦ３，ＦＦ４の各クロック入力端子ＣＫに接続する。
【００３２】
フリップフロップ回路ＦＦ１のデータ出力端子Ｑは、フリップフロップ回路ＦＦ３のデータ入力端子Ｄに接続するとともに、その信号を位相信号Ｅ２として、ＮＡＮＤ回路Ｎ２の第１の入力端子に接続する。フリップフロップ回路ＦＦ１の反転データ出力端子ＱＮは、遅延回路Ｄ３の入力端子に接続する。フリップフロップ回路ＦＦ２のデータ出力端子Ｑは、フリップフロップ回路ＦＦ４のデータ入力端子Ｄに接続するとともに、その信号を位相信号Ｅ２Ｎとして、ＮＡＮＤ回路Ｎ１の第１の入力端子に接続する。フリップフロップ回路ＦＦ２の反転データ出力端子ＱＮは、遅延回路Ｄ３’の入力端子に接続する。フリップフロップ回路ＦＦ３のデータ出力端子Ｑは、その信号を位相信号Ｅ４として、ＮＡＮＤ回路Ｎ４の第１の入力端子に接続する。フリップフロップ回路ＦＦ４のデータ出力端子Ｑは、その信号を位相信号Ｅ４Ｎとして、ＮＡＮＤ回路Ｎ５の第１の入力端子に接続する。
【００３３】
遅延回路Ｄ２の出力端子は、その信号を位相信号Ｅ１として、ＮＡＮＤ回路Ｎ１の第２の入力端子に接続する。遅延回路Ｄ２’の出力端子は、その信号を位相信号Ｅ１Ｎとして、ＮＡＮＤ回路Ｎ２の第２の入力端子に接続する。反転遅延回路Ｄ３の出力端子は、その信号を位相信号Ｅ３として、ＮＡＮＤ回路Ｎ５の第２の入力端子に接続する。反転遅延回路Ｄ３’の出力端子は、その信号を位相信号Ｅ３Ｎとして、ＮＡＮＤ回路Ｎ４の第２の入力端子に接続する。
【００３４】
位相差出力部４の接続を説明する。位相差出力部４では、ＮＡＮＤ回路Ｎ１の出力端子をＮＡＮＤ回路Ｎ３の第２の入力端子に接続し、ＮＡＮＤ回路Ｎ２の出力端子をＮＡＮＤ回路Ｎ３の第１の入力端子に接続する。また、ＮＡＮＤ回路Ｎ４の出力端子をＮＡＮＤ回路Ｎ６の第２の入力端子に接続し、ＮＡＮＤ回路Ｎ５出力端子をＮＡＮＤ回路Ｎ６の第１の入力端子に接続する。さらに、ＮＡＮＤ回路Ｎ３の出力端子は、遅延回路Ｄ４の入力端子に接続し、遅延回路Ｄ４の出力端子の信号は、本位相比較回路のＵＰ信号として出力する。ＮＡＮＤ回路Ｎ６の出力端子の信号は、本位相比較回路のＤＯＷＮ信号として出力する。
【００３５】
本実施形態では、回路数が増加するが、第１の実施形態の位相差出力の精度をさらに向上させることができる。まず図４を用いて、第１の実施形態での位相差出力精度の向上の限界を説明する。図４は、図２のＵＰ信号とＤＯＷＮ信号のそれぞれの連続する２パルスに注目して、パルス幅を示した図である。図２と同様に回路遅延を０とした信号波形を基準にして、各回路遅延を付加してＵＰ信号とＤＯＷＮ信号幅を示した。
【００３６】
図４によると、ＵＰ信号の連続するパルスの幅の位相差からのずれΔｔｕｐ１とΔｔｕｐ２、Δｔｄｏｗｎ１とΔｔｄｏｗｎ２は、以下の式

で示すことができる。
【００３７】
上記（７）式と（８）式を比較すると前記第１の実施形態の位相差精度が理解できる。すなわち、Δｔｕｐ１を０にするために、遅延回路Ｄ２の遅延量ｔＤ２を「ｔ１＋tdE12LL−tdE11LH」なる値に設定しても、Δｔｕｐ２は「tdE12HL−tdE12LL＋tdE11LH−tdE11HH」となり、０にはならない。排他的論理和回路ＥＸＯＲ１回路は、第２の入力信号（Ｅ２）がＬからＨに遷移して出力端子がＬに遷移する際の遅延tdE12HLと、第２の入力信号（Ｅ２）がＨからＬに遷移して出力端子がＬに遷移する際の遅延tdE12LLが一般に異なるためである。そして、排他的論理和回路ＥＸＯＲ１の第１の入力信号（Ｅ１）がＨからＬに遷移して出力端子がＨに遷移する際の遅延tdE11LHと、第１の入力信号（Ｅ１）がＬからＨに遷移して出力端子がＨに遷移する際の遅延tdE11HHも一般に異なる。
【００３８】
したがって、前記した第１の実施形態では、排他的論理和回路ＥＸＯＲ１の遅延を入力条件に対して全て等しくしない限り、２回に１回の割合でＵＰ信号のパルス幅と表示すべき位相差の間に誤差が生ずる。ＤＯＷＮ信号も同様に、（９）式により、Δｔｄｏｗｎ１を０にするように遅延時間ｔＤ３を設定しても、（１０）式のΔｔｄｏｗｎ２が０にならない問題がある。
【００３９】
そこで、第２の実施形態では、ＵＰ信号とＤＯＷＮ信号の連続する２つパルス幅を等しくすることができるようにした。図５を用いて説明する。図４の場合と同様に、回路遅延を０とした信号波形を基準にして、各回路遅延を付加してＵＰ信号とＤＯＷＮ信号幅を示した。図５によるとＵＰ信号の連続するパルスの幅の位相差からのずれΔｔｕｐ１とΔｔｕｐ２およびΔｔｄｏｗｎ１とΔｔｄｏｗｎ２は、以下の式

で示すことができる。
【００４０】
ここで、ｔＤ２は遅延回路Ｄ２の遅延時間、ｔＤ２’は遅延回路Ｄ２’の遅延時間、ｔＤ３は遅延回路Ｄ３の遅延時間、ｔＤ３’は遅延回路Ｄ３’の遅延時間である。また、tdN*#LHは、ＮＡＮＤ回路Ｎ＊（＊は１，２，３，４，５，６のいずれか）の遅延時間であり、特に、入力信号Ｅ＃（＃は１，２，３，４のいずれか）あるいは、ＮＡＮＤ回路Ｎ３，Ｎ６の入力信号となるＮＡＮＤ＃（＃は１，２，４，５のいずれか）の出力信号がＬに遷移してから、ＮＡＮＤ回路＊（＊は１，２，３，４，５，６のいずれか）の出力信号がＨに遷移するまでの遅延時間である。また、tdN*#HLは、ＮＡＮＤ回路Ｎ＊（＊は１，２，３，４，５，６のいずれか）の遅延時間であり、特に、入力信号Ｅ＃（＃は１，２，３，４のいずれか）あるいは、ＮＡＮＤ回路Ｎ３，Ｎ６の入力信号であるＮＡＮＤ＃（＃は１，２，４，５のいずれか）の出力信号がＨに遷移してから、ＮＡＮＤ回路Ｎ＊（＊は１，２，３，４，５，６のいずれか）の出力信号がＬに遷移するまでの遅延時間である。
【００４１】
（１１），（１２），（１３），（１４）式において、ｔＤ２，ｔＤ２’，ｔＤ３，ｔＤ３’以外の変数は、回路によりただ一つの値を持つ（ｔＤ１は設計者が設定）。したがって、遅延時間ｔＤ２，ｔＤ２’，ｔＤ３，ｔＤ３’は、Δｔｕｐ１，Δｔｕｐ２，Δｔｄｏｗｎ１，Δｔｄｏｗｎ２を全て０にするように設定することが可能となる。よって、本実施形態によると、位相比較回路の出力信号であるＵＰ信号とＤＯＷＮ信号の連続する２パルスのパルス幅に付加される誤差Δｔｕｐ１，Δｔｕｐ２，Δｔｄｏｗｎ１，Δｔｄｏｗｎ２をすべて補償することができる。
【００４２】
なお、本実施形態においても、反転遅延回路Ｄ３を通常の遅延回路（第３の遅延回路）に置換してその入力端子をフリップフロップ回路ＦＦ１のデータ出力端子Ｑに接続し、また反転遅延回路Ｄ３’を通常の遅延回路（第５の遅延回路）に置換してその入力端子をフリップフロップ回路ＦＦ２のデータ出力端子Ｑに接続しても上記と同様な動作を行わせることができるが、それらデータ出力端子Ｑの出力負荷が大きくなり、高速化にはそぐわない嫌いがある。
【００４３】
本発明の第２の実施形態によると、本発明の第１の実施形態の効果に加えて、排他的論理和回路における入力端子、入力遷移方向、出力遷移方向の別により生じる、ＵＰ信号とＤＯＷＮ信号の連続する２パルスの位相出力誤差を、０に近づけることが可能となる。
【００４４】
【発明の効果】
以上のように本発明によれば、２つの入力信号の位相差を、ＵＰ信号とＤＯＷＮ信号のパルス幅の差として、高い精度で出力できるようになるという利点がある。
【図面の簡単な説明】
【図１】 本発明の第１の実施形態の位相比較回路の回路図である。
【図２】 図１の位相比較回路において回路遅延による位相出力信号誤差を補正することを示すタイミング図である。
【図３】 本発明の第２の実施形態の位相比較回路の回路図である。
【図４】 図１の位相比較回路において連続する２パルスの位相誤差の補正が困難であることを示すタイミング図である。
【図５】 図３の位相比較回路において連続する２パルスの位相誤差を補正可能であることを示すタイミング図である。
【図６】 従来の位相比較回路の回路図である。
【図７】 図６の位相比較回路のデータ入力信号とクロック入力信号の位相が一致している場合の動作を示す図であり、回路遅延を考慮しないタイミング図である。
【図８】 図７の位相比較回路のクロック入力信号の位相がデータ入力信号の位相よりＴ／４進んでいる場合の動作を示す図であり、回路遅延を考慮しないタイミング図である。
【図９】 図６の位相比較回路のデータ入力信号とクロック入力信号の位相が一致している場合の動作を示す図であり、回路遅延を考慮した場合、出力位相誤差を生じることを示すタイミング図である。
【符号の説明】
１，３，５：位相検出部、２，４，６：位相差出力部
ＦＦ１〜ＦＦ４：フリップフロップ回路
ＥＸＯＲ１，ＥＸＯＲ２：排他的論理和回路
Ｄ１，Ｄ２，Ｄ２’，Ｄ４：遅延回路
Ｄ３，Ｄ３’：反転遅延回路
Ｉ１：インバータ回路
Ｎ１〜Ｎ６：ＮＡＮＤ回路[0001]
BACKGROUND OF THE INVENTION
The present invention is used in a clock recovery circuit, a phase lock loop (PLL) circuit, and the like, and particularly in a linear phase comparison circuit that outputs a pulse having a width proportional to a phase difference between two input signals. It is related with the phase comparison circuit which can convert the phase difference between them into an output pulse width with high precision.
[0002]
[Prior art]
A conventional phase comparison circuit will be described with reference to FIG. 6 (reference: A Self Correcting Clock Recovery Circuit, CRHogge, Jr., IEEE Journal of Lightwave Technology, vol.LT-3, pp.1312-1314, December) 1985). The conventional phase comparison circuit includes a phase detection unit 5 and a phase difference output unit 6. The phase detection unit 5 includes two flip-flop circuits FF1 and FF3 and an inverter circuit I1, and the phase difference output unit 6 includes two exclusive OR circuits EXOR1 and EXOR2.
[0003]
The connection of the conventional phase comparison circuit will be described. The phase detector 5 has a data input terminal DI, a clock input terminal CI, and four phase signal output terminals E1, E2, E3, E4. The data input terminal DI is a data input terminal D and a phase signal output terminal of the flip-flop circuit FF1. The clock input terminal CI is connected to E1, and is connected to the clock input terminal CK of the flip-flop circuit FF1 and the input terminal of the inverter circuit I1.
[0004]
The data output terminal Q of the flip-flop circuit FF1 is connected to the data input terminal D and the phase signal output terminals E2 and E3 of the flip-flop circuit FF3. The output terminal of the inverter circuit I1 is connected to the clock input terminal CK of the flip-flop circuit FF3, and the data output terminal Q of the flip-flop circuit FF3 is connected to the phase signal output terminal signal E4.
[0005]
The phase difference output unit 6 has phase signal input terminals E1, E2, E3, E4, an UP signal output terminal UP, and a DOWN signal output terminal DOWN. The phase signal output terminals E1, E2, E3, and E4 of the phase detection unit 5 are connected to the phase signal input terminals E1, E2, E3, and E4 of the phase difference output unit 6, respectively, and the phase signal input terminals E1 and E2 are exclusive logic. The phase signal input terminals E3 and E4 are respectively connected to two inputs of the exclusive OR circuit EXOR2 and connected to two inputs of the sum circuit EXOR1. The output terminal of the exclusive OR circuit EXOR1 is connected to the output terminal UP of the phase difference output unit 6, and the output terminal of the exclusive OR circuit EXOR2 is connected to the output terminal DOWN of the phase difference output unit 6. The output terminals UP and DOWN are also output terminals of the phase detection circuit.
[0006]
The operation of the conventional phase comparison circuit will be described with reference to FIGS. The phase comparison circuit is a circuit that outputs the phase difference between the data input signal DI and the clock input signal CI as the difference between the pulse time width of the output signal UP and the pulse time width of the output signal DOWN. The pulse width of the output signal DOWN is kept constant at one half of the clock period. When the phase of the clock input signal CI advances with respect to the data input signal DI, the phase relationship is displayed by making the pulse width of the signal UP narrower than the pulse width of the signal DOWN by the advanced time difference. Further, when the phase of the clock input signal CI is delayed with respect to the data input signal DI, the phase relationship is displayed by making the pulse width of the signal UP larger than the pulse width of the signal DOWN by the delayed time difference.
[0007]
FIG. 7 shows the timing when the data input signal DI and the clock input signal CI are in a desired phase relationship. The phase signal E1 uses the data input signal DI to transmit the transition point (phase) of the data input signal DI to the phase difference output unit 6. The phase signal E2 informs the phase difference output unit 6 of the time point (phase) when the clock input signal CI transits to a high level. This is because the data output signal Q changes to the value of the data input signal DI (phase signal E1) when the clock input signal CI changes to high level by the flip-flop circuit FF1. The phase difference output unit 6 inputs the phase signals E1 and E2 to the exclusive OR circuit EXOR1. The exclusive OR circuit EXOR1 outputs a high-level pulse as an UP signal only during the time when the values of the phase signals E1 and E2 are different. The pulse width tup of the UP signal corresponds from the transition point of the data input signal DI to the rising point of the clock input signal CI, and represents the phase difference between the data input signal DI and the clock input signal CI.
[0008]
On the other hand, the phase signal E3 is the data output signal Q of the flip-flop circuit FF1, and has information on the time point (phase) when the clock input signal CI transits to a high level. The phase signal E4 is the data output signal Q of the flip-flop circuit FF3, and has information on the time point (phase) when the clock input signal CI transits to a low level. In general, since the time ratio between the high level and the low level of the clock input signal CI is 1: 1, the phase signal E4 is a signal obtained by delaying the phase signal E3 by one half of the clock period. Therefore, when the exclusive OR of the phase signals E3 and E4 is obtained by using the exclusive OR circuit EXOR2 in the phase difference output unit 6, the time width (tdown) is ½ of the clock period. A high level pulse is output as a DOWN signal.
[0009]
In FIG. 7 described above, the rising edge of the clock input signal CI is located at the exact center of the data input signal DI, and there is no phase difference between the two. It can be seen that the pulse width tup of the UP signal is ½ of the clock period and is equal to the pulse width of the DOWN signal.
[0010]
On the other hand, in FIG. 8, the rising position of the clock input signal CI is located at a position advanced by T / 4 (T is one cycle of the clock) from the center of the data input. In this state, the pulse width tup of the UP signal is T / 4. Compared with a DOWN signal having a pulse width of T / 2 at all times, a difference in pulse width of T / 4 is output, indicating that the clock input signal is advanced by T / 4 with respect to the data input signal DI.
[0011]
[Problems to be solved by the invention]
However, the conventional phase comparison circuit has a problem that the phase difference between the data input signal DI and the clock input signal CI cannot be accurately output as the difference between the pulse widths of the UP signal and the DOWN signal. This is because the pulse widths of the UP signal and the DOWN signal increase or decrease depending on the delay time of the flip-flop circuits FF1 and FF3 and the exclusive OR circuits EXOR1 and EXOR2. 7 and 8 used in explaining the operation of the conventional phase comparison circuit are ideal timing diagrams when the delay time of the circuit is not taken into consideration.
[0012]
FIG. 9 shows a timing chart when the delay time of the circuit is taken into consideration. Compared to FIG. 7, the phase signal E2 is delayed from the ideal case by a time t1 from when the clock input signal CI rises to when the data output signal Q is output in the flip-flop circuit FF1. In the UP signal, the delay times tdE11LH and tdE12LL of the exclusive OR circuit EXOR1 appear at the rise and fall, respectively. Here, tdE * # LH is obtained from the time when the input signal E # (where # is one of 1, 2, 3, and 4) of the exclusive OR circuit EXOR * (* is 1 or 2) transits to L. The delay until the output signal transitions to H is shown. The last two characters indicate the transition direction of the input signal and the transition direction of the output signal, such as a delay from the transition of the input signal to L in the case of LL until the transition of the output signal to L. These are distinguished from each other because the exclusive OR circuit generally has a different delay time depending on each input terminal, input signal transition direction, and output signal transition direction. Due to these circuit delays, the pulse width of the UP signal is
Δtup = t1 + tdE12LL−tdE11LH (1)
Is increased by Δtup shown in FIG.
[0013]
On the other hand, a delay t1 similar to that of the phase signal E2 is added to the phase signal E3, and an output delay t3 of the flip-flop circuit FF3 is added to the phase signal E4. The delay times t1 and t3 are both output circuit delay times of the flip-flop circuit, but do not necessarily match because they depend on the circuit configuration, the number of output fanouts, and the like. Further, in the DOWN signal, the delay times tdE23LH and tdE24LL of the exclusive OR circuit EXOR2 appear at the rise time and fall time, respectively. Due to these two circuit delays, the pulse width of the DOWN signal is given by
Δtdown = t3 + tdE24LL− (t1 + tdE23LH) (2)
Is increased by Δtdown shown in FIG. Therefore, there is a difference between Δtup and Δtdown in the pulse width of the UP signal and the DOWN signal, and there is a problem that the phase difference between the data input signal DI and the clock input signal CI cannot be output with high accuracy.
[0014]
Further, when these circuit delays occur, there arises a problem that the time point at which the UP signal falls is delayed from the rising point of the DOWN signal, or the time point at which the DOWN signal falls is delayed from the rising point of the UP signal. Here, a charge pump circuit generally used in the subsequent stage of the phase difference output unit 6 is not shown, but when the UP signal and the DOWN signal pulses overlap, not only the output voltage stability of the charge pump circuit is impaired, but also the power consumption increases. There is a problem that brings about.
[0015]
The present invention has been made in view of the above points, and an object of the present invention is to provide a phase comparison circuit capable of outputting a phase difference between two input signals as a difference in pulse width between an UP signal and a DOWN signal with high accuracy. Is to provide.
[0016]
[Means for Solving the Problems]
  In order to solve the above problems, the invention of claim 1 provides a first input signal.And detecting a phase difference between the data signal (DI), which is the second input signal, and the clock signal (CI), which is the second input signal, and a pulse between the UP signal, which is the first output signal, and the DOWN signal, which is the second output signal. In the phase comparison circuit that outputs the difference in width, the first input signal (DI) is input to the data input terminal (D), and the second input signal (CI) is input to the clock input terminal (CK). Flip-flop circuit (FF1) and the data output terminal (Q) of the first flip-flop circuit (FF1) are connected to the data input terminal (D), and the inverted signal (CIN ′) of the second input signal is The second flip-flop circuit (FF3) input to the clock input terminal (CK) and the inverted signal (DIN) of the first input signal are input to the data input terminal (D) and the second input signal ( CI) is black The third flip-flop circuit (FF2) connected to the clock input terminal (CK) and the data output terminal (Q) of the third flip-flop circuit (FF2) are connected to the data input terminal (D) and A fourth flip-flop circuit (FF4) in which an inverted signal (CIN ′) of the second input signal is input to a clock input terminal (CK), and a data input terminal (D) of the first flip-flop circuit (FF1) ) Connected to the inverted data output terminal (QN) of the first flip-flop circuit (FF1), the first delay circuit (D3) connected to the inverted data output terminal (QN) of the first flip-flop circuit (FF1), A third delay circuit (D2 ′) connected to the data input terminal (D) of the third flip-flop circuit (FF2), and an inverted data output terminal (QN) of the third flip-flop circuit (FF2). The second inverting delay circuit (D3 ′), the output signal (E1) of the first delay circuit (D2), the output signal (E1N) of the fourth delay circuit (D2 ′), and the first The signal (E2) of the data output terminal (Q) of the flip-flop circuit (FF1) and the output signal (E2N) of the data output terminal (Q) of the third flip-flop circuit (FF2) are input and the exclusive OR A third exclusive OR circuit that performs processing, an output signal (E3) of the first inverting delay circuit (D3), an output signal (E3N) of the second inverting delay circuit (D3 ′), and the second The signal (E4) of the data output terminal (Q) of the second flip-flop circuit (FF3) and the output signal (E4N) of the data output terminal (Q) of the fourth flip-flop circuit (FF4) are input and the exclusive logic Fourth exclusive OR to perform sum processing And having a circuitThe phase comparison circuit is characterized by this.
According to a second aspect of the present invention, in the phase comparator according to the first aspect, a pulse width deviation from the phase difference that appears in two consecutive pulses of the UP signal is further different from the first delay circuit (D2). The first inversion delay circuit (D3) is set independently by the delay value with respect to the fourth delay circuit (D2 ′), and the deviation of the pulse width from the phase difference that appears in two consecutive pulses of the DOWN signal. And a phase comparator that is independently set by the delay value of the second inversion delay circuit (D3 ′).
The invention of claim 3 is the phase comparator according to claim 2,SaidThe third exclusive OR circuit inputs the output signal (E1) of the first delay circuit (D2) and the signal (E2N) of the output terminal (Q) of the third flip-flop circuit (FF2). The first NAND circuit (N1), the output signal (E1N) of the fourth delay circuit (D2 ′), and the signal (E2) of the output terminal (Q) of the first flip-flop circuit (FF1) Are input to the second NAND circuit (N2), and the third NAND circuit (N3) is input to the output of the first NAND circuit (N1) and the output of the second NAND circuit (N2). ), And the fourth exclusive OR circuit outputs the output signal (E3N) of the second inverting delay circuit (D3 ′) and the output terminal (Q3) of the second flip-flop circuit (FF3). ) Signal (E4) as an input, a fourth NAND circuit (N ) And the output signal (E3) of the first inverting delay circuit (D3) and the signal (E4N) of the output terminal (Q) of the fourth flip-flop circuit (FF4). A circuit (N5), and a sixth NAND circuit (N6) that receives the output of the fourth NAND circuit (N4) and the output of the fifth NAND circuit (N5) as inputs. A phase comparator characterized by
The invention of claim 4 is a data signal (DI) as a first input signal and a second input signal. In a phase comparison circuit that detects a phase difference from a clock signal (CI) and outputs the difference as a pulse width between an UP signal that is a first output signal and a DOWN signal that is a second output signal. A first flip-flop circuit (FF1) in which a signal (DI) is input to a data input terminal (D) and a second input signal (CI) is input to a clock input terminal (CK); and the first flip-flop A second flip-flop in which the data output terminal (Q) of the circuit (FF1) is connected to the data input terminal (D) and the inverted signal (CIN ′) of the second input signal is input to the clock input terminal (CK). A circuit (FF3) and an inverted signal (DIN) of the first input signal are input to the data input terminal (D), and the second input signal (CI) is connected to the clock input terminal (CK). Flip The flop circuit (FF2) and the data output terminal (Q) of the third flip-flop circuit (FF2) are connected to the data input terminal (D), and the inverted signal (CIN ′) of the second input signal is input to the clock. A fourth flip-flop circuit (FF4) input to the terminal (CK), a first delay circuit (D2) connected to the data input terminal (D) of the first flip-flop circuit (FF1), A third delay circuit (not shown) connected to the data output terminal (Q) of the first flip-flop circuit (FF1) and a data input terminal (D) of the third flip-flop circuit (FF2) A fourth delay circuit (D2 ′), a fifth delay circuit (not shown) connected to the data output terminal (Q) of the third flip-flop circuit (FF2), and the first delay circuit (D2 Output signal (E1), the output signal (E1N) of the fourth delay circuit (D2 ′), the signal (E2) of the data output terminal (Q) of the first flip-flop circuit (FF1), and the third A fifth exclusive OR circuit that receives the output signal (E2N) of the data output terminal (Q) of the flip-flop circuit (FF2) of the flip-flop circuit (FF2) and performs an exclusive OR process, and the third delay circuit (not shown). An output signal (not shown), an output signal (not shown) of the five delay circuits (not shown), a signal (E4) of the data output terminal (Q) of the second flip-flop circuit (FF3), and a fourth flip-flop A sixth exclusive OR circuit that receives the force signal (E4N) of the data output terminal (Q) of the logic circuit (FF4) and performs exclusive OR processing.Thus, a phase comparison circuit is provided.
According to a fifth aspect of the present invention, in the phase comparator according to the fourth aspect of the present invention, a pulse width deviation from the phase difference that appears in two consecutive pulses of the UP signal is further different from the first delay circuit (D2). The third delay circuit (not shown) is set independently by the delay value with respect to the fourth delay circuit (D2 '), and the deviation of the pulse width from the phase difference that appears in two consecutive pulses of the DOWN signal. And a phase comparator that is independently set by delay values of the fifth delay circuit (not shown).
According to a sixth aspect of the present invention, in the phase comparator according to the fourth aspect, the fifth exclusive OR circuit includes an output signal (E1) of the first delay circuit (D2) and the third flip-flop. A seventh NAND circuit (N1) that receives the signal (E2N) of the output terminal (Q) of the output circuit (FF2), the output signal (E1N) of the fourth delay circuit (D2 ′), and the An eighth NAND circuit (N2) that receives the signal (E2) of the output terminal (Q) of one flip-flop circuit (FF1), the output of the seventh NAND circuit (N1), and the eighth NAND circuit (N1). A ninth NAND circuit (N3) that receives the output of the NAND circuit (N2), and the sixth exclusive OR circuit outputs an output signal (not shown) of the fifth delay circuit (not shown). (Not shown) and the output terminal of the second flip-flop circuit (FF3) A tenth NAND circuit (N4) that receives the signal (E4) of the child (Q), an output signal (not shown) of the third delay circuit (not shown), and the fourth flip-flop circuit (not shown) The eleventh NAND circuit (N5) that receives the signal (E4N) of the output terminal (Q) of the FF4), the output of the tenth NAND circuit (N4), and the eleventh NAND circuit (N5) And a twelfth NAND circuit (N6) that receives the output of the phase comparator.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
  [First Embodiment(Principle of the present invention)]
  Of the present inventionAs a principleA first embodiment will be described with reference to FIG. The phase comparison circuit of this embodiment includes a phase detection unit 1 and a phase difference output unit 2. The phase detector 1 includes a flip-flop circuit FF1 (first flip-flop circuit), a flip-flop circuit FF3 (second flip-flop circuit), an inverter circuit I1, a delay circuit D1, a delay circuit D2 (first delay circuit), An inversion delay circuit D3 (first inversion delay circuit) is used. The phase difference output unit 2 includes an exclusive OR circuit EXOR1 (first exclusive OR circuit), EXOR2 (second exclusive OR circuit), and a delay circuit D4 (second delay circuit).
[0021]
The connection of this embodiment will be described with reference to FIG. In the phase detector 1, the data input signal DI that is the input of the phase comparison circuit is connected to the data input terminal D of the flip-flop FF1 and the input terminal of the delay circuit D2, and the signal at the output terminal of the delay circuit D2 is connected to the phase signal E1. Output as. The clock input signal CI, which is the input of this phase comparison circuit, is connected to the clock input terminal CK of the flip-flop circuit FF1 and the input terminal of the inverter circuit I1, and the output terminal of the inverter circuit I1 is connected to the input terminal of the delay circuit D1, The output terminal of the delay circuit D1 is connected to the clock input terminal CK of the flip-flop circuit FF3. The data output terminal Q of the flip-flop circuit FF1 is connected to the data input terminal D of the flip-flop circuit FF3 and outputs the signal as a phase signal E2. The inverted data output terminal QN of the flip-flop circuit FF1 is connected to the input terminal of the inverting delay circuit D3, and the signal at the output terminal of the inverting delay circuit D3 is output as the phase signal E3. The signal at the data output terminal Q of the flip-flop circuit FF3 is output as the phase signal E4.
[0022]
  Phase differenceoutputIn the section 2, the phase signals E1 and E2 are connected to two inputs of the exclusive OR circuit EXOR1, the output terminal of the exclusive OR circuit EXOR1 is connected to the input terminal of the delay circuit D4, and the delay circuit D4 The output signal is output as the UP signal of this phase comparison circuit. The phase signals E3 and E4 are respectively connected to two inputs of the exclusive OR circuit EXOR2, and the output signal of the exclusive OR circuit EXOR2 is output as the DOWN signal of this phase comparison circuit.
[0023]
The operation of this embodiment will be described with reference to FIG. The basic operation as the phase comparison circuit is the same as that of the conventional phase comparison circuit shown in FIG. This phase comparison circuit outputs the phase difference between the data input signal DI and the clock input signal CI as the difference between the pulse time width of the UP signal and the pulse time width of the DOWN signal. The DOWN signal is output with a constant pulse width with a width of 1/2 of the clock period T. When the phase of the clock input signal CI advances with respect to the data input signal DI, the UP signal has a pulse width narrower than the pulse width of the DOWN signal by the advanced time difference, and conversely, the clock input to the data input signal DI. When the phase of the signal CI is delayed, the pulse width of the DOWN signal becomes thicker by the delayed time difference.
[0024]
The principle that the phase comparison circuit improves the phase comparison accuracy will be described with reference to FIG. In FIG. 2, UP 'is an output signal of the exclusive OR circuit EXOR1, and CIN' is an output signal of the delay circuit D1. In the present embodiment, in addition to the basic phase comparison operation of the circuit of FIG. 6, the phase signal E1 is delayed by the time tD2 by the delay circuit D2. By adding this delay tD2, the amount by which the UP signal pulse width increases from the phase difference between the data input signal DI and the clock input signal CI is compared with the following equation (1) in the conventional phase comparison circuit. formula
Δtup = t1 + tdE1211− (tD2 + tdE11LH) (3)
It can be expressed as That is, by inserting a delay circuit D2 that generates a delay tD2 that sets Δtup in equation (3) to 0, the UP signal accurately indicates the phase difference between the data input terminal DI and the clock input terminal CI. Design becomes possible.
[0025]
The pulse width of the DOWN signal is also kept at a half of the clock period T. The inversion delay circuit D3 connected to the inversion data output terminal QN of the flip-flop circuit FF1 outputs a phase signal E3 obtained by delaying the phase signal E2 by a time tD3. By adding this delay tD3, the amount by which the DOWN signal pulse width increases from half the width of the clock period T is as follows in comparison with the expression (2) in the conventional phase comparison circuit.

Can be shown. Here, tD1 is the delay time of the delay circuit D1 that delays the clock signal supplied to the flip-flop circuit FF3. Further, t2 is a delay from when the clock signal CI rises in the flip-flop circuit FF1 until the inverted data output signal QN is output. By generating the delay tD3 that sets Δtdown of the equation (4) to 0, it becomes possible to design the DOWN signal so as to accurately indicate a width of ½ of the clock period T. The delay circuit D1 is the following condition necessary for performing data transfer between the flip-flop circuits FF1 and FF3 without error.
(T1 + tset) <(tD1 + T / 2) <(T + t1-tho1d) (5)
Set to satisfy. Here, tset is the data setup time of the flip-flop circuit FF3, and to1d is the data hold time of the flip-flop circuit FF3.
[0026]
In addition, the delay time of the UP signal and the rising time of the DOWN signal can be made equal by the delay circuit D4. By inserting the delay circuit D4 into the output line of the exclusive OR circuit EXOR1, the delay time tD4 generated by the delay circuit D4 is added to the UP signal. This delay time tD4 is expressed by the following equation.
t2 + tD3 + tdE23LH = t1 + tdE12LL + tD4 (6)
By design to a value that satisfies the above, the falling time of the UP signal is equal to the rising time of the DOWN signal.
[0027]
Therefore, according to this embodiment, the phase output errors caused by the circuit delays t1, t2, and t3 of the flip-flop circuits FF1 and FF3 and the circuit delays tdE12LL, tdE11LH, tdE24LL, and tdE23LH of the exclusive OR circuits EXOR1 and EXOR2 It becomes possible to approach 0 by the delay of D2 and D3. Further, the delay circuit D1 ensures a timing margin for data transfer between the flip-flop circuits FF1 and FF3, and the phase output error due to the delay of the delay circuit D1 can be made closer to 0 by the phase circuits D2 and D3. The rise time and the fall time of the UP signal and the DOWN signal can be matched by the delay circuit D4.
[0028]
This embodiment is different from the conventional example in that the phase signal E3 is output from the inverted data output terminal QN of the flip-flop circuit FF3. The phase signals E2 and E3 are taken from the data output terminal Q of the flip-flop circuit FF1 (however, the delay signal (third delay circuit) having the same delay as that of the inverting delay circuit D3 is interposed for the phase signal E3). Further, it is possible to take the input of the flip-flop circuit FF3 and operate in the same manner. However, if this is done, the output load of the data output terminal Q becomes large and high-speed signal transfer becomes difficult. There is. Therefore, in this embodiment, the output load is distributed by taking the output signal of the flip-flop circuit FF1 from both the data output terminal Q and the inverted data output terminal QN. As a result, the phase comparison circuit of this embodiment can operate at a higher speed than the conventional phase comparison circuit.
[0029]
[Second Embodiment]
A second embodiment of the present invention will be described with reference to FIG. The phase comparison circuit of this embodiment includes a phase detection unit 3 and a phase difference output unit 4. The phase difference output unit 4 is different from the phase difference output unit 2 of the first embodiment in that an exclusive OR circuit (third exclusive OR circuit) in which the exclusive OR circuit EXOR1 is configured by NAND circuits N1, N2, and N3. OR circuit), the exclusive OR circuit EXOR2 is replaced with an exclusive OR circuit (fourth exclusive OR circuit) composed of NAND circuits N4, N5, and N6, and the phase signals E1, E2, In addition to E3 and E4, inverted phase signals E1N, E2N, E3N, and E4N that are inverted signals thereof are used.
[0030]
The phase detector 3 differs from the phase detector 1 of the first embodiment in that the inverted phase signals E1N, E2N, E3N, and E4N are generated, so that the inverted data input signal is added to the data input signal DI. DIN is input, a flip-flop circuit FF2 (third flip-flop circuit) and a flip-flop circuit FF4 (fourth flip-flop circuit) are added, and the delay times of the inverted phase signals E1N and E3N are added to the phase signals E1 and E3. This is because a delay circuit D2 ′ (fourth delay circuit) and an inversion delay circuit D3 ′ (second inversion delay circuit) are added in order to set them separately from the delay time.
[0031]
The connection of this embodiment will be described. A data input signal DI which is an input of the phase comparison circuit is connected to the data input terminal D of the flip-flop circuit FF1 and the input terminal of the delay circuit D2. An inverted data input signal DIN that is an input of the phase comparison circuit is connected to the data input terminal D of the flip-flop circuit FF2 and the input terminal of the delay circuit D2 '. A clock input signal CI, which is an input of the phase comparison circuit, is connected to each clock input terminal CK of the flip-flop circuits FF1 and FF2 and an input terminal of the inverter circuit I1. The output terminal of the inverter circuit I1 is connected to the input terminal of the delay circuit D1, and the output terminal of the delay circuit D1 is connected to the clock input terminals CK of the flip-flop circuits FF3 and FF4.
[0032]
The data output terminal Q of the flip-flop circuit FF1 is connected to the data input terminal D of the flip-flop circuit FF3, and the signal is connected as a phase signal E2 to the first input terminal of the NAND circuit N2. The inverted data output terminal QN of the flip-flop circuit FF1 is connected to the input terminal of the delay circuit D3. The data output terminal Q of the flip-flop circuit FF2 is connected to the data input terminal D of the flip-flop circuit FF4, and the signal is connected to the first input terminal of the NAND circuit N1 as the phase signal E2N. The inverted data output terminal QN of the flip-flop circuit FF2 is connected to the input terminal of the delay circuit D3 '. The data output terminal Q of the flip-flop circuit FF3 is connected to the first input terminal of the NAND circuit N4 using the signal as the phase signal E4. The data output terminal Q of the flip-flop circuit FF4 is connected to the first input terminal of the NAND circuit N5 as its phase signal E4N.
[0033]
The output terminal of the delay circuit D2 is connected to the second input terminal of the NAND circuit N1 using the signal as the phase signal E1. The output terminal of the delay circuit D2 'is connected to the second input terminal of the NAND circuit N2 using the signal as the phase signal E1N. The output terminal of the inverting delay circuit D3 is connected to the second input terminal of the NAND circuit N5 as the phase signal E3. The output terminal of the inverting delay circuit D3 'is connected to the second input terminal of the NAND circuit N4 using the signal as the phase signal E3N.
[0034]
Connection of the phase difference output unit 4 will be described. In the phase difference output unit 4, the output terminal of the NAND circuit N1 is connected to the second input terminal of the NAND circuit N3, and the output terminal of the NAND circuit N2 is connected to the first input terminal of the NAND circuit N3. The output terminal of the NAND circuit N4 is connected to the second input terminal of the NAND circuit N6, and the output terminal of the NAND circuit N5 is connected to the first input terminal of the NAND circuit N6. Further, the output terminal of the NAND circuit N3 is connected to the input terminal of the delay circuit D4, and the signal at the output terminal of the delay circuit D4 is output as the UP signal of the phase comparison circuit. The signal at the output terminal of the NAND circuit N6 is output as the DOWN signal of this phase comparison circuit.
[0035]
In the present embodiment, the number of circuits increases, but the accuracy of the phase difference output of the first embodiment can be further improved. First, with reference to FIG. 4, the limit of improvement in phase difference output accuracy in the first embodiment will be described. FIG. 4 is a diagram showing a pulse width by paying attention to two consecutive pulses of the UP signal and the DOWN signal in FIG. Similarly to FIG. 2, the signal delay with the circuit delay set to 0 is used as a reference, and the circuit delay is added to indicate the UP signal and DOWN signal widths.
[0036]
According to FIG. 4, the deviations Δtup1 and Δtup2 and Δtdown1 and Δtdown2 from the phase difference of the width of the continuous pulse of the UP signal are expressed by the following equations.

Can be shown.
[0037]
Comparing the above equations (7) and (8), the phase difference accuracy of the first embodiment can be understood. That is, even if the delay amount tD2 of the delay circuit D2 is set to a value “t1 + tdE12LL−tdE11LH” in order to set Δtup1 to 0, Δtup2 becomes “tdE12HL−tdE12LL + tdE11LH−tdE11HH” and does not become 0. The exclusive OR circuit EXOR1 circuit has a delay tdE12HL when the second input signal (E2) changes from L to H and the output terminal changes to L, and the second input signal (E2) changes from H to L. This is because the delay tdE12LL when the output terminal changes to L and the output terminal changes to L is generally different. Then, the delay tdE11LH when the first input signal (E1) of the exclusive OR circuit EXOR1 changes from H to L and the output terminal changes to H, and the first input signal (E1) changes from L to H. Generally, the delay tdE11HH when the output terminal changes to H and the output terminal changes to H is also different.
[0038]
Therefore, in the first embodiment described above, the pulse width of the UP signal and the phase difference to be displayed at a rate of once every two times unless the delays of the exclusive OR circuit EXOR1 are all equal to the input conditions. An error occurs between them. Similarly, the DOWN signal has a problem that Δtdown2 in equation (10) does not become zero even if the delay time tD3 is set so that Δtdown1 becomes zero according to equation (9).
[0039]
Therefore, in the second embodiment, two continuous pulse widths of the UP signal and the DOWN signal can be made equal. This will be described with reference to FIG. As in the case of FIG. 4, the UP signal and DOWN signal widths are shown by adding each circuit delay with reference to the signal waveform with the circuit delay set to zero. According to FIG. 5, the deviations Δtup1 and Δtup2 and Δtdown1 and Δtdown2 from the phase difference of the width of the continuous pulse of the UP signal are expressed by the following equations:

Can be shown.
[0040]
Here, tD2 is the delay time of the delay circuit D2, tD2 'is the delay time of the delay circuit D2', tD3 is the delay time of the delay circuit D3, and tD3 'is the delay time of the delay circuit D3'. Further, tdN * # LH is a delay time of the NAND circuit N * (* is any one of 1, 2, 3, 4, 5, and 6). In particular, the input signal E # (# is 1, 2, 3). , 4) or NAND circuit * (* after the output signal of NAND # (# is any of 1, 2, 4 and 5) which becomes the input signal of NAND circuits N3 and N6 transitions to L. Is a delay time until the output signal of any one of 1, 2, 3, 4, 5 and 6) transitions to H. Further, tdN * # HL is a delay time of the NAND circuit N * (* is any one of 1, 2, 3, 4, 5, and 6). In particular, the input signal E # (# is 1, 2, 3). , 4) or the output signal of NAND # (# is any of 1, 2, 4 and 5), which is the input signal of NAND circuits N3 and N6, transitions to H and then NAND circuit N * ( * Is a delay time until the output signal of any one of 1, 2, 3, 4, 5 and 6) transitions to L.
[0041]
In equations (11), (12), (13), and (14), variables other than tD2, tD2 ', tD3, and tD3' have a single value depending on the circuit (tD1 is set by the designer). Accordingly, the delay times tD2, tD2 ', tD3, and tD3' can be set so that Δtup1, Δtup2, Δtdown1, and Δtdown2 are all zero. Therefore, according to the present embodiment, it is possible to compensate for all the errors Δtup1, Δtup2, Δtdown1, and Δtdown2 added to the pulse width of two consecutive pulses of the UP signal and the DOWN signal that are output signals of the phase comparison circuit.
[0042]
Also in this embodiment, the inverting delay circuit D3 is replaced with a normal delay circuit (third delay circuit), and its input terminal is connected to the data output terminal Q of the flip-flop circuit FF1, and the inverting delay circuit D3. Even if 'is replaced with a normal delay circuit (fifth delay circuit) and its input terminal is connected to the data output terminal Q of the flip-flop circuit FF2, the same operation as described above can be performed. The output load of the output terminal Q becomes large, and there is a dislike that is not suitable for high speed.
[0043]
According to the second embodiment of the present invention, in addition to the effect of the first embodiment of the present invention, the UP signal and DOWN generated by the input terminal, the input transition direction, and the output transition direction in the exclusive OR circuit are different. It is possible to make the phase output error of two consecutive pulses of the signal close to zero.
[0044]
【The invention's effect】
As described above, according to the present invention, there is an advantage that the phase difference between two input signals can be output with high accuracy as the difference between the pulse widths of the UP signal and the DOWN signal.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a phase comparison circuit according to a first embodiment of the present invention.
FIG. 2 is a timing diagram illustrating that a phase output signal error due to circuit delay is corrected in the phase comparison circuit of FIG. 1;
FIG. 3 is a circuit diagram of a phase comparison circuit according to a second embodiment of the present invention.
FIG. 4 is a timing chart showing that it is difficult to correct the phase error of two consecutive pulses in the phase comparison circuit of FIG.
5 is a timing chart showing that the phase error of two consecutive pulses can be corrected in the phase comparison circuit of FIG.
FIG. 6 is a circuit diagram of a conventional phase comparison circuit.
7 is a diagram illustrating an operation when the phase of the data input signal and the clock input signal of the phase comparison circuit of FIG.
FIG. 8 is a diagram illustrating an operation when the phase of the clock input signal of the phase comparison circuit of FIG. 7 is advanced by T / 4 from the phase of the data input signal, and is a timing diagram that does not consider circuit delay.
FIG. 9 is a diagram illustrating an operation when the phase of the data input signal and the clock input signal of the phase comparison circuit of FIG. 6 are the same, and a timing indicating that an output phase error occurs when circuit delay is considered. FIG.
[Explanation of symbols]
1, 3, 5: Phase detection unit, 2, 4, 6: Phase difference output unit
FF1 to FF4: flip-flop circuit
EXOR1, EXOR2: exclusive OR circuit
D1, D2, D2 ', D4: delay circuit
D3, D3 ': Inversion delay circuit
I1: Inverter circuit
N1 to N6: NAND circuit

Claims (6)

A phase difference between the data signal (DI) as the first input signal and the clock signal (CI) as the second input signal is detected, and the UP signal as the first output signal and the second output signal are detected. In the phase comparison circuit that outputs the pulse width difference from the DOWN signal,
A first flip-flop circuit (FF1) in which a first input signal (DI) is input to a data input terminal (D) and a second input signal (CI) is input to a clock input terminal (CK);
The data output terminal (Q) of the first flip-flop circuit (FF1) is connected to the data input terminal (D), and the inverted signal (CIN ′) of the second input signal is input to the clock input terminal (CK). A second flip-flop circuit (FF3),
A third flip-flop circuit (FF2) in which an inverted signal (DIN) of the first input signal is input to a data input terminal (D) and the second input signal (CI) is connected to a clock input terminal (CK). )When,
The data output terminal (Q) of the third flip-flop circuit (FF2) is connected to the data input terminal (D), and the inverted signal (CIN ′) of the second input signal is input to the clock input terminal (CK). A fourth flip-flop circuit (FF4),
A first delay circuit (D2) connected to a data input terminal (D) of the first flip-flop circuit (FF1);
A first inversion delay circuit (D3) connected to an inversion data output terminal (QN) of the first flip-flop circuit (FF1);
A fourth delay circuit (D2 ′) connected to the data input terminal (D) of the third flip-flop circuit (FF2);
A second inversion delay circuit (D3 ′) connected to the inversion data output terminal (QN) of the third flip-flop circuit (FF2);
The output signal (E1) of the first delay circuit (D2), the output signal (E1N) of the fourth delay circuit (D2 ′), and the data output terminal (Q) of the first flip-flop circuit (FF1) A third exclusive OR circuit that receives the signal (E2) and the output signal (E2N) of the data output terminal (Q) of the third flip-flop circuit (FF2) and performs an exclusive OR process;
The output signal (E3) of the first inversion delay circuit (D3), the output signal (E3N) of the second inversion delay circuit (D3 ′), and the data output terminal (FF3) of the second flip-flop circuit (FF3) A fourth exclusive OR circuit that receives the signal (E4) of Q) and the output signal (E4N) of the data output terminal (Q) of the fourth flip-flop circuit (FF4) and performs exclusive OR processing; ,
Phase comparison circuit, characterized in that it comprises a. In the phase comparator of claim 1, further
The pulse width deviation from the phase difference that appears in two consecutive pulses of the UP signal is independently set by the delay values of the first delay circuit (D2) and the fourth delay circuit (D2 ′),
The pulse width deviation from the phase difference that appears in two consecutive pulses of the DOWN signal is set independently by the delay values of the first inversion delay circuit (D3) and the second inversion delay circuit (D3 ′). a phase comparator, characterized in that that. The phase comparator according to claim 1 ,
The third exclusive OR circuit comprises:
A first NAND circuit (N1) having the output signal (E1) of the first delay circuit (D2) and the signal (E2N) of the output terminal (Q) of the third flip-flop circuit (FF2) as inputs. When,
A second NAND circuit (N2) having the output signal (E1N) of the fourth delay circuit (D2 ′) and the signal (E2) of the output terminal (Q) of the first flip-flop circuit (FF1) as inputs. )When,
A third NAND circuit (N3) having the output of the first NAND circuit (N1) and the output of the second NAND circuit (N2) as inputs;
The fourth exclusive OR circuit comprises:
A fourth NAND circuit having the output signal (E3N) of the second inverting delay circuit (D3 ′) and the signal (E4) of the output terminal (Q) of the second flip-flop circuit (FF3) as inputs; N4)
A fifth NAND circuit (N5) having the output signal (E3) of the first inverting delay circuit (D3) and the signal (E4N) of the output terminal (Q) of the fourth flip-flop circuit (FF4) as inputs. )When,
A sixth NAND circuit (N6) having as inputs the output of the fourth NAND circuit (N4) and the output of the fifth NAND circuit (N5);
A phase comparator characterized by that. A phase difference between the data signal (DI) as the first input signal and the clock signal (CI) as the second input signal is detected, and the UP signal as the first output signal and the second output signal are detected. In the phase comparison circuit that outputs the pulse width difference from the DOWN signal,
A first flip-flop circuit (FF1) in which a first input signal (DI) is input to a data input terminal (D) and a second input signal (CI) is input to a clock input terminal (CK);
The data output terminal (Q) of the first flip-flop circuit (FF1) is connected to the data input terminal (D), and the inverted signal (CIN ′) of the second input signal is input to the clock input terminal (CK). A second flip-flop circuit (FF3),
A third flip-flop circuit (FF2) in which an inverted signal (DIN) of the first input signal is input to a data input terminal (D) and the second input signal (CI) is connected to a clock input terminal (CK). )When,
The data output terminal (Q) of the third flip-flop circuit (FF2) is connected to the data input terminal (D), and the inverted signal (CIN ′) of the second input signal is input to the clock input terminal (CK). A fourth flip-flop circuit (FF4),
A first delay circuit (D2) connected to a data input terminal (D) of the first flip-flop circuit (FF1);
A third delay circuit (not shown) connected to the data output terminal (Q) of the one flip-flop circuit (FF1);
A fourth delay circuit (D2 ′) connected to the data input terminal (D) of the third flip-flop circuit (FF2);
A fifth delay circuit (not shown) connected to the data output terminal (Q) of the third flip-flop circuit (FF2);
The output signal (E1) of the first delay circuit (D2), the output signal (E1N) of the fourth delay circuit (D2 ′), and the data output terminal (Q) of the first flip-flop circuit (FF1) A fifth exclusive OR circuit that receives the signal (E2) and the output signal (E2N) of the data output terminal (Q) of the third flip-flop circuit (FF2) and performs an exclusive OR process;
Output signal (not shown) of the third delay circuit (not shown), output signal (not shown) of the fifth delay circuit (not shown), data output terminal (Q) of the second flip-flop circuit (FF3) A sixth exclusive OR circuit that receives the signal (E4) and the output signal (E4N) of the data output terminal (Q) of the fourth flip-flop circuit (FF4) and performs exclusive OR processing;
Phase comparison circuit, characterized in that it comprises a. The phase comparator of claim 4, further comprising:
The pulse width deviation from the phase difference that appears in two consecutive pulses of the UP signal is independently set by the delay values of the first delay circuit (D2) and the fourth delay circuit (D2 ′),
It is set independently by the delay value of the DOWN signal shift said third delay circuit of the pulse width from the phase difference which appears in two consecutive pulses of the (not shown) and a fifth delay circuit (not shown) A phase comparator. The phase comparator according to claim 4.
The fifth exclusive OR circuit comprises:
A seventh NAND circuit (N1) having the output signal (E1) of the first delay circuit (D2) and the signal (E2N) of the output terminal (Q) of the third flip-flop circuit (FF2) as inputs. When,
An eighth NAND circuit (N2) having the output signal (E1N) of the fourth delay circuit (D2 ′) and the signal (E2) of the output terminal (Q) of the first flip-flop circuit (FF1) as inputs. )When,
A ninth NAND circuit (N3) having the output of the seventh NAND circuit (N1) and the output of the eighth NAND circuit (N2) as inputs;
The sixth exclusive OR circuit comprises:
A tenth NAND circuit (input) which receives an output signal (not shown) of the fifth delay circuit (not shown) and a signal (E4) of the output terminal (Q) of the second flip-flop circuit (FF3). N4)
An eleventh NAND circuit (with an output signal (not shown) of the third delay circuit (not shown) and a signal (E4N) of the output terminal (Q) of the fourth flip-flop circuit (FF4) as inputs. N5)
A twelfth NAND circuit (N6) having the outputs of the tenth NAND circuit (N4) and the eleventh NAND circuit (N5) as inputs;
A phase comparator characterized by that.

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