WO2017095186A1

WO2017095186A1 - Clock and data recovery apparatus

Info

Publication number: WO2017095186A1
Application number: PCT/KR2016/014117
Authority: WO
Inventors: 변상진
Original assignee: 동국대학교 산학협력단
Priority date: 2015-12-04
Filing date: 2016-12-02
Publication date: 2017-06-08

Abstract

Disclosed is a clock and data recovery apparatus. Specifically, the clock and data recovery apparatus according to an embodiment of the present invention comprises: a linear phase detector for comparing a phase difference and a frequency difference between a received data signal and a recovered clock signal and outputting an up signal and a down signal corresponding to the comparison value; a charge pump for outputting a current corresponding to the up signal and the down signal inputted from the linear phase detector; a loop filter for outputting a VCO adjustment voltage corresponding to the current inputted from the charge pump; a voltage controlled oscillator for recovering a clock signal having a frequency and a phase corresponding to the VCO adjustment voltage outputted from the loop filter, and outputting the recovered clock signal to the linear phase detector; and a reset circuit for initializing the VCO adjustment voltage to a preset reference voltage.

Description

Clock and Data Recovery Unit

Embodiments of the present invention relate to data recovery techniques, and more particularly, to clock and data recovery apparatus.

In general, a clock and data recovery apparatus generates a clock signal synchronized with a data signal from an input data signal, and restores the data signal using the generated clock signal. Clock and data recovery devices are used in a wide range, such as LAN (LAN) for data transmission, wired and wireless communication and optical communication, disk drive.

In the conventional clock and data recovery apparatus, a frequency detector and a phase detector are used to recover a clock signal synchronized with the frequency and phase of a received digital input signal. Conventionally, since both the frequency detector and the phase detector have to be used, there is an inefficient problem in terms of hardware implementation.

[Preceding technical literature]

[Patent Documents]

(Patent Document 01) Korean Registered Patent Publication No. 10-0706605 (2007.04.12)

An embodiment of the present invention is to provide a clock and data recovery apparatus that can easily recover the clock and data through the linear phase detector and the reset circuit.

An embodiment of the present invention is to provide a clock and data recovery apparatus capable of detecting phase and frequency with only a linear phase detector without a separate frequency detector.

Clock and data recovery apparatus according to an embodiment of the present invention, the phase difference and the frequency difference between the received data signal and the recovered clock signal by comparing the phase and the linear phase detector corresponding to the comparison value and outputs; A charge pump outputting a current corresponding to an up signal and a down signal input from the linear phase detector; A loop filter outputting a voltage controlled oscillator (VCO) regulated voltage corresponding to the current input from the charge pump; A voltage controlled oscillator for recovering a clock signal having a frequency and a phase corresponding to a VCO adjustment voltage output from the loop filter and outputting the recovered clock signal to the linear phase detector; And a reset circuit for initializing the VCO adjustment voltage to a preset reference voltage.

The linear phase detector comprises: a full-rate linear phase detector, the inverter for inverting and outputting the recovered clock signal; A first de flip-flop that receives the received data signal and the restored clock signal and outputs a value corresponding to the input; A second di flip-flop that receives an output signal of the first di flip-flop and an output signal of the inverter and outputs a value corresponding to the input; A first XOR circuit configured to receive the received data signal and the output signal of the first flip-flop and output the up signal; And a second XOR circuit configured to receive output signals of the first di flip-flop and the second di flip-flop and output the down signal.

The linear phase detector is a full-rate linear phase detector, when the frequency of the recovered clock signal is less than the bit rate of the received data signal, in addition to the phase difference between the received data signal and the recovered clock signal. The frequency difference between the received data signal and the recovered clock signal may also be provided.

The linear phase detector is a full-rate linear phase detector, and the reset circuit sets the VCO adjustment voltage such that the frequency of the voltage controlled oscillator is smaller than a frequency corresponding to the bit rate of the received data signal. It can be reset to voltage.

The reference voltage may be set to a voltage smaller than a voltage such that the frequency of the voltage controlled oscillator becomes a frequency corresponding to the bit rate of the received data signal.

The linear phase detector may be a half-rate linear phase detector, and an inverter for inverting and outputting the restored clock signal; A first latch receiving the received data signal and the restored clock signal and outputting a value corresponding to the input; A second latch receiving an output signal of the first latch and an output signal of the inverter and outputting a value corresponding to the input; A third latch receiving the received data signal and the output signal of the inverter and outputting a value corresponding to the input; A fourth latch receiving the output signal of the third latch and the restored clock signal and outputting a value corresponding to the input; A first XOR circuit receiving the output signals of the first latch and the third latch and outputting the up signal; And a second XOR circuit receiving the output signals of the second latch and the fourth latch and outputting the down signal.

The linear phase detector is a half-rate linear phase detector and when the frequency of the recovered clock signal is less than half the bit rate of the received data signal, the phase of the received data signal and the recovered clock signal In addition to the difference, the frequency difference between the received data signal and the recovered clock signal may be provided.

The linear phase detector is a half-rate linear phase detector, and the reset circuit adjusts the VCO adjustment voltage such that the frequency of the voltage controlled oscillator is less than a frequency corresponding to half the bit rate of the received data signal. The reference voltage may be initialized.

The reference voltage may be set to a voltage smaller than a voltage such that the frequency of the voltage controlled oscillator becomes a frequency corresponding to half of the bit rate of the received data.

The reset circuit receives a reset signal and initializes the VCO adjustment voltage to the reference voltage. The reset signal is turned on when the bit rate of the received data signal decreases, and the bit rate of the received data signal is maintained or increased. May be turned off.

The reset circuit may include an N-channel MOSFET (NMOS) transistor, the gate configured to receive the reset signal; A drain receiving the reference voltage; And a source connected to the loop filter.

According to an embodiment of the present invention, the clock and data can be easily recovered by detecting both phase and frequency through a linear phase detector, thereby simplifying a conventional complicated hardware configuration. That is, since the frequency can be detected without a separate frequency detector, the configuration of the clock and data recovery apparatus can be simplified.

In addition, by using a reset circuit to satisfy the condition to detect the frequency in the linear phase detector, more accurate clock and data recovery is possible.

1 is a block diagram of a clock and data recovery apparatus according to an embodiment of the present invention;

2 is a block diagram of a linear phase detector according to an embodiment of the present invention.

3 is a block diagram of a linear phase detector according to another embodiment of the present invention.

4 is a graph illustrating a relationship between a phase difference between a received data signal and a restored clock signal and an output current of a charge pump in a linear phase detector according to an embodiment of the present invention.

5 is a graph illustrating a relationship between a frequency of a clock signal restored in a linear phase detector and an average output current of a charge pump according to an exemplary embodiment of the present invention.

6 is a graph showing a simulation signal waveform of the VCO adjustment voltage in the clock and data recovery apparatus according to an embodiment of the present invention;

7 is a graph illustrating a relationship between a frequency of a restored clock signal of a linear phase detector and an average output current of a charge pump according to another exemplary embodiment of the present invention.

8 is a graph illustrating a circuit simulation signal waveform of a VCO regulated voltage in a clock and data recovery apparatus according to another embodiment of the present invention.

9 is a comparison diagram comparing a restored data waveform and received data according to an embodiment of the present invention.

Hereinafter, specific embodiments of the present invention will be described with reference to FIGS. 1 to 9. However, this is only an exemplary embodiment and the present invention is not limited thereto.

In describing the present invention, when it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to the intention or custom of a user or an operator. Therefore, the definition should be made based on the contents throughout the specification.

The technical spirit of the present invention is determined by the claims, and the following embodiments are merely means for efficiently explaining the technical spirit of the present invention to those skilled in the art.

In the following description, the terms "transfer", "communication", "transmit", "receive" and other similar meanings of signals or information are not only meant to directly convey the signal or information from one component to another. It also includes passing through other components. In particular, "transmitting" or "sending" a signal or information to a component indicates the final destination of the signal or information and does not mean a direct destination.

1 is a block diagram of a clock and data recovery apparatus according to an embodiment of the present invention.

Referring to FIG. 1, a clock and data recovery apparatus 100 according to an embodiment may include a linear phase detector 102, a charge pump 104, a loop filter 106, and a voltage. A control oscillator 108 may include a voltage controlled oscillator 108, a reset circuit 110, and a D flip flop 112.

Hereinafter, in one embodiment, the linear phase detector 102 is described as being a full-rate linear phase detector, but is not limited thereto. The linear phase detector 102 may be a linear phase detector having various structures (eg, half-rate). Of course, a linear phase detector, a quarter-rate linear phase detector, etc.) may be used.

The linear phase detector 102 may output an up signal and a down signal in response to the received data signal and the restored clock signal. Here, the received data signal may mean a digital signal that is a target for restoring data. Also, the recovery clock signal may mean a signal used to recover the received data signal.

In detail, the linear phase detector 102 may compare the phase difference and the frequency difference between the received data signal and the restored clock signal to output the up signal and the down signal corresponding to the comparison value to the charge pump 104.

That is, in a general clock and data recovery apparatus, only a phase difference is compared with a linear phase detector, and a frequency difference is compared using a separate frequency detector. However, in the exemplary embodiment of the present invention, one linear phase detector is used to compare the received data signal with the received data signal. The phase and frequency difference of the recovered clock signal is detected. At this time, the linear phase detector 102 detects the frequency difference together only when the frequency of the recovered clock signal is smaller than the bit rate of the received data signal (ie, the frequency of the received data signal).

In an embodiment of the present invention, the voltage controlled oscillator (VCO) adjustment voltage for recovering the clock signal may be initialized to a reference voltage so that the frequency of the recovered clock signal is smaller than the bit rate of the received data signal. have. Here, the reference voltage may be set to a voltage smaller than the voltage that causes the frequency of the voltage controlled oscillator 108 to be a frequency corresponding to the bit rate of the received data signal.

Specifically, the clock and data recovery apparatus 100 initializes the VCO adjustment voltage for restoring the clock signal to the reference voltage using the reset circuit 110, which will be described later, so that the frequency of the recovered clock signal is higher than the bit rate of the received data signal. It can be small.

The clock and data recovery apparatus 100 detects both the phase difference and the frequency difference between the received data signal and the restored clock by using the linear phase detector 102 and the reset circuit 110, thereby simplifying the hardware configuration. Comparing the frequency of the received data signal with the frequency of the recovered clock signal using the linear phase detector 102 will be described later with reference to FIGS. 4 and 5.

The charge pump 104 may receive an up signal and a down signal from the linear phase detector 102 and output a current corresponding thereto. Specifically, the charge pump 104 outputs an up current corresponding to the up signal input from the linear phase detector 102 to the loop filter 106 and down corresponding to the down signal input from the linear phase detector 102. The current can be output to the loop filter 106.

The loop filter 106 may output a VCO regulated voltage corresponding to the up current and the down current input from the charge pump 104. Specifically, the loop filter 106 includes a resistor R connected in series between the output terminal of the charge pump 104 and the ground and a second capacitor connected between the first capacitor C1 and the output terminal of the charge pump 104 and the ground. It may be composed of a capacitor (C2). In this manner, the up current and the down current output from the charge pump 104 are changed to the VCO regulated voltage through the loop filter 106.

The voltage controlled oscillator 108 restores a clock signal having a frequency and a phase changed according to the VCO adjustment voltage output from the loop filter 106, and restores the recovered clock signal to the linear phase detector 102 and the de-flip flop 112. Feedback.

The reset circuit 110 may initialize the VCO adjustment voltage of the loop filter 106 to the reference voltage so that the linear phase detector 102 may compare the frequency difference between the received data signal and the restored clock signal.

In detail, the reset circuit 110 may receive the reset signal and initialize the VCO adjustment voltage of the loop filter 106 to the reference voltage. Here, the reset signal is an output signal when the clock and data recovery apparatus 100 starts to operate or when the bit rate of the received data signal is lower than the bit rate of the previous received data signal. The reset signal is used to initialize the VCO adjustment voltage to the reference voltage. May be a signal. If the bit rate of the received data signal is maintained or increased in comparison with the bit rate of the previous received data signal, the reset signal may be turned off.

The reset circuit 110 may initialize the VCO adjustment voltage to the reference voltage according to the relationship between the frequency of the voltage controlled oscillator 108 and the bit rate of the received data signal. In an exemplary embodiment, when the linear phase detector 102 is a full-rate linear phase detector, the reset circuit 110 performs the VCO adjustment voltage when the frequency of the voltage controlled oscillator 108 is greater than the bit rate of the received data signal. Can be initialized to the reference voltage. Alternatively, when the linear phase detector 102 is a half-rate linear phase detector, the reset circuit 110 references the VCO adjustment voltage when the frequency of the voltage controlled oscillator 108 is greater than half the bit rate of the received data signal. Can be reset to voltage.

That is, the reset circuit 110 may initialize the VCO adjustment voltage to the reference voltage so that the frequency of the voltage control oscillator 108 is smaller than the frequency corresponding to the bit rate of the received data signal. Thus, the reference voltage may be set to a value where the frequency of the voltage controlled oscillator 108 is less than the lowest bit rate of the received data signal. The reset circuit 110 may be implemented as an NMOS transistor. In this case, the reset circuit 110 is connected to the reset signal and the gate (G), the reference voltage and the drain (D :) is connected, the loop filter 106 and the source (S: source) is connected It may be implemented as an N-channel MOSFET (NMOS) transistor.

The de flip-flop 112 may perform a function of restoring data by sampling a received data signal with the restored clock signal.

Referring to FIG. 2, the linear phase detector 102 includes an inverter 128, a first di flip-flop 120, a second di flip-flop 122, a first XOR circuit (XOR: exclusive or 124), 2 XOR circuit 126 may be included.

The linear phase detector 102 of the inverter 128 for inverting and outputting the restored clock signal, the first de flip-flop 120 and the first de flip-flop 120 that receive the received data signal and the restored clock signal. A second de-flip flop 122 receiving the output signal and the output signal of the inverter 128, a first receiving the received data signal and the output signal of the first de-flipped flop 120 and outputting an up signal corresponding thereto. And an XOR circuit 124 and a second XOR circuit 126 that receives the output signals of the first de flip-flop 120 and the second de flip-flop 122 and outputs a down signal corresponding thereto. have.

The linear phase detector 102 can detect the phase and frequency difference between the received data signal and the restored clock signal through the input / output signals between the above components, and output the up and down signals accordingly.

Also, instead of using the de-flip-flop 112 shown in FIG. 1 to sample the received data signal with the restored clock signal, the first de-flip-flop 120 shown in FIG. 2 and At least one of the second de flip-flops 122 may be used to obtain data reconstructed from the received data signal at the A or B point.

Referring to FIG. 3, the linear phase detector 102 includes an inverter 130, a first latch 132, a second latch 134, a third latch 136, a fourth latch 138, and a third latch. It may include a 1 XOR circuit (XOR: exclusive or, 140) and the second XOR circuit 142.

Specifically, the linear phase detector 102 inverts the restored clock signal and outputs the inverter 130, an output of the first latch 132 and the first latch 132 that receive the received data signal and the restored clock signal. A second latch 134 for receiving a signal and an output signal of the inverter 130, an output signal of the third latch 136 and a third latch 136 for receiving a received data signal and an output signal of the inverter 130; A fourth latch 138 that receives the restored clock signal, a first XOR circuit 140 that receives output signals of the first latch 132 and the third latch 136 and outputs an up signal corresponding thereto; And a second XOR circuit 142 that receives the output signals of the second latch 134 and the fourth latch 138 and outputs a down signal corresponding thereto.

4 is a graph illustrating a relationship between a phase difference between a received data signal and a restored clock signal and an output current of a charge pump in a linear phase detector according to an exemplary embodiment of the present invention. Here, a full-rate linear phase detector was used as the linear phase detector.

The graph shown in FIG. 4 shows signals at each point of the linear phase detector shown in FIG. 2 at the frequency of each recovered clock signal (specifically, the received data signal, the recovered clock signal, the point A signal of FIG. 2, By using the timing diagrams of the point B signal, the up signal, and the down signal in FIG. Here, f _DATA denotes a bit rate of the received data signal, f _CLK denotes a frequency of the recovered clock signal, and I _CP denotes an UP path (i.e., up current) and a DOWN path (i.e., the charge pump 104). Down current).

Here, as shown in Figure 2, the phase difference between the center of the received data signal and the rising edge of the recovered clock signal

If defined as f _CLK = 1 / n * f _DATA (where n is a natural number greater than or equal to 1), The output current of the charge pump 104 is

And according to the frequency of the recovered clock signal can be represented by the following equation (1).

[Equation 1]

here,

Denotes a bit transition density.

Referring to FIG. 4, the output current of the charge pump 104 has an average value of 0 when the frequency f _CLK of the restored clock signal is equal to or greater than the bit rate f _DATA of the received data signal, whereas the restored clock signal When the frequency f _CLK is smaller than the bit rate f _DATA of the received data signal, it can be seen that the average value has a positive value.

As such, when the frequency f _CLK of the recovered clock signal is smaller than the bit rate f _DATA of the received data signal, the output current of the charge pump 104 outputs a positive value on average, so that the linear phase detector 102 ), The frequency difference between the received data signal and the recovered clock signal can be detected.

On the other hand, when the frequency f _CLK of the recovered clock signal is equal to or greater than the bit rate f _DATA of the received data signal, the output current of the charge pump 104 outputs a value of 0 on average, so that the linear phase detector ( In 102, the frequency difference between the received data signal and the recovered clock signal cannot be detected. Therefore, in the exemplary embodiment of the present invention, the frequency f _CLK of the clock signal restored by initializing the VCO adjustment voltage of the loop filter 106 to the reference voltage through the reset circuit 110 is the bit rate f _DATA of the received data signal. By making it smaller, the frequency difference between the received data signal and the recovered clock signal can always be detected.

5 is a graph illustrating a relationship between a frequency of a clock signal restored in a linear phase detector and an average output current of a charge pump according to an exemplary embodiment of the present invention. Here, the linear phase detector is assumed to be a full-rate linear phase detector.

The graph shown in FIG. 5 (ie, the graph relating to the average output current of the charge pump) takes the average value of the charge pump output current shown in FIG. 4 at each restored clock frequency with respect to the phase difference as shown in Equation 2 below. It can be obtained by

[Equation 2]

Referring to FIG. 5, the linear phase detector 102 of the charge pump 104 when the frequency f _CLK of the recovered clock signal is smaller than the bit rate f _DATA of the received data signal is determined. the average frequency of the restored clock signal value of the output current (a value of Y axis in Fig. 5) (f _CLK) and having a positive value (+), while inversely, the frequency of the recovered clock signal (f _CLK), the received data signal When the bit rate f _DATA is equal to or greater than, the value of the average output current of the charge pump is zero, regardless of the frequency f _CLK of the recovered clock signal.

That is, the linear phase detector 102 compares the bit rate of the received data signal and the frequency of the recovered clock signal in a range in which the frequency of the recovered clock signal is smaller than the bit rate of the received data signal and detects the difference. The frequency can be detected without using.

If the bit rate of the received data signal is reduced so that the frequency of the recovered clock signal becomes larger than the bit rate of the received data signal, the reset circuit 110 may set the frequency of the recovered clock signal to be lower than the bit rate of the received data signal ( That is, to be initialized). Through this, the linear phase detector 102 can detect not only phase detection but also frequency.

6 is a graph showing a simulation signal waveform of the VCO adjustment voltage in the clock and data recovery apparatus according to an embodiment of the present invention. Here, the linear phase detector is assumed to be a full-rate linear phase detector.

In FIG. 6, the reference voltage is set to 0 V, and it can be seen that the VCO adjustment voltage is properly locked to approximately 500 mV. The clock and data recovery apparatus 100 may acquire a phase after frequency acquisition and recover data using the restored clock signal.

The reference voltage, as already explained, depends on the range of bit rates of the received data signal. For example, if the linear phase detector is a full-rate linear phase detector and the bit rate of the received data signal is a fixed value, such as 1 Gb / s, the reference voltage is such that the frequency of the voltage controlled oscillator 108 is equal to the bit rate of the received data signal. It should be set to a voltage less than the voltage that corresponds to 1 GHz.

Alternatively, when the linear phase detector is a full-rate linear phase detector, and the bit rate of the received data signal is a broadband frequency such as 1 Gb / s at 100 Mb / s, the reference voltage is the frequency of the voltage controlled oscillator 108 It should be set to a voltage less than the voltage to be 100 MHz, the frequency corresponding to the lowest bit rate 100 Mb / s. That is, the reference voltage should be set to a voltage at which the frequency of the voltage controlled oscillator 108 can be set to a value smaller than the lowest bit rate of the received data signal.

7 is a graph illustrating a relationship between a frequency of a restored clock signal of a linear phase detector and an average output current of a charge pump according to another exemplary embodiment of the present invention. The graph can be obtained by showing timing diagrams respectively at various clock frequencies. Here, the linear phase detector was assumed to be a half-rate linear phase detector. In addition, f _in may mean a bit rate of the received data signal, and I _cp may mean a current source value in the UP path (ie, up current) and DOWN path (ie, down current) of the charge pump 104. .

Referring to FIG. 7, the linear phase detector 102 includes the charge pump 104 when the frequency of the recovered clock signal (the value of the X axis of FIG. 7) is less than half (f _in / 2) of the bit rate of the received data signal. When the value of the average output current (the value of the Y-axis in Fig. 7) is inversely proportional to the frequency of the recovered clock signal, and the frequency of the recovered clock signal is equal to or greater than half (f _in / 2) of the bit rate of the received data signal. It can be seen that the value of the average output current of the charge pump is zero regardless of the frequency of the recovered clock signal.

That is, the linear phase detector 102 detects the difference by comparing the bit rate of the received data signal with the frequency of the recovered clock signal in a range where the frequency of the recovered clock signal is less than or equal to half the bit rate of the received data signal, The frequency can be detected without using a frequency detector.

If the bit rate of the signal of the received data is lower than the bit rate of the previous received data signal so that the frequency of the recovered clock signal is greater than half (f _in / 2) of the bit rate of the received data signal, the reset circuit 110 The frequency of the recovered clock signal can be lowered (ie, initialized) to less than half of the bit rate (f _in / 2) of the received data signal. Through this, the linear phase detector 102 can detect not only phase detection but also frequency.

8 is a graph illustrating a circuit simulation signal waveform of a VCO adjustment voltage in a clock and data recovery apparatus according to another embodiment of the present invention. Here, the linear phase detector was assumed to be a half-rate linear phase detector.

In FIG. 8, the reference voltage is set to 100 mV, and it can be seen that the VCO adjustment voltage is properly locked to approximately 600 mV. The reference voltage, as already explained, depends on the range of bit rates of the received data signal. For example, when the bit rate of the received data signal is a fixed value such as 1 Gb / s, the reference voltage is smaller than the voltage such that the frequency of the voltage controlled oscillator 108 becomes 500 MHz corresponding to half of the bit rate of the received data signal. Should be set to voltage. If the bit rate of the received data signal is a wideband frequency such as 1 Gb / s at 100 Mb / s, the reference voltage is a frequency whose frequency of the voltage controlled oscillator 108 corresponds to half of 100 Mb / s, which is the lowest bit rate of the received data signal. Should be set to a voltage less than 50MHz. That is, the reference voltage should be set to a voltage at which the frequency of the voltage controlled oscillator 108 can be set to a value less than half of the lowest bit rate of the received data signal.

9 is a comparison diagram comparing the restored data waveform and the received data according to an embodiment of the present invention.

Referring to FIG. 9, when the data waveform restored using the clock and data recovery apparatus 100 is compared with the received data waveform, it is understood that the clock and data recovery apparatus 100 correctly restores the received data. Can be.

Although the present invention has been described in detail with reference to exemplary embodiments above, those skilled in the art to which the present invention pertains can make various modifications to the above-described embodiments without departing from the scope of the present invention. I will understand. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the claims below and equivalents thereof.

[Description of the code]

100: clock and data recovery unit

102: linear phase detector

104: charge pump

106: loop filter

108: voltage controlled oscillator

110: reset circuit

112: the flip flop

120: first di flip-flop

122: second di flip-flop

124: first XOR circuit

126: second XOR circuit

128: inverter

130: inverter

132: first latch

134: second latch

136: third latch

138: fourth latch

140: first XOR circuit

142: second XOR circuit

Claims

A linear phase detector for comparing a phase difference and a frequency difference between the received data signal and the recovered clock signal to output an up signal and a down signal corresponding to the comparison value;

A charge pump outputting a current corresponding to an up signal and a down signal input from the linear phase detector;

A loop filter outputting a voltage controlled oscillator (VCO) regulated voltage corresponding to the current input from the charge pump;

A voltage controlled oscillator for recovering a clock signal having a frequency and a phase corresponding to a VCO adjustment voltage output from the loop filter and outputting the recovered clock signal to the linear phase detector; And

And a reset circuit for initializing the VCO adjustment voltage to a preset reference voltage.
The method according to claim 1,

The linear phase detector is a full-rate linear phase detector,

An inverter for inverting and outputting the restored clock signal;

A first de flip-flop that receives the received data signal and the restored clock signal and outputs a value corresponding to the input;

A second di flip-flop that receives an output signal of the first di flip-flop and an output signal of the inverter and outputs a value corresponding to the input;

A first XOR circuit configured to receive the received data signal and the output signal of the first flip-flop and output the up signal; And

And a second XOR circuit configured to receive output signals of the first and second flip-flops and output the down signal.
The method according to claim 1,

The linear phase detector is a full-rate linear phase detector,

When the frequency of the recovered clock signal is less than the bit rate of the received data signal, in addition to the phase difference between the received data signal and the restored clock signal, provided to detect a frequency difference between the received data signal and the recovered clock signal, Clock and data recovery device.
The method according to claim 3,

The linear phase detector is a full-rate linear phase detector,

The reset circuit,

And initializing the VCO adjustment voltage to the reference voltage such that a frequency of the voltage controlled oscillator becomes smaller than a frequency corresponding to a bit rate of the received data signal.
The method according to claim 4,

The reference voltage is,

And a voltage lower than a voltage such that the frequency of the voltage controlled oscillator becomes a frequency corresponding to the bit rate of the received data signal.
The method according to claim 1,

The linear phase detector is a half-rate linear phase detector,

An inverter for inverting and outputting the restored clock signal;

A first latch receiving the received data signal and the restored clock signal and outputting a value corresponding to the input;

A second latch receiving an output signal of the first latch and an output signal of the inverter and outputting a value corresponding to the input;

A third latch receiving the received data signal and the output signal of the inverter and outputting a value corresponding to the input;

A fourth latch receiving the output signal of the third latch and the restored clock signal and outputting a value corresponding to the input;

A first XOR circuit receiving the output signals of the first latch and the third latch and outputting the up signal; And

And a second XOR circuit receiving the output signals of the second latch and the fourth latch and outputting the down signal.
The method according to claim 1,

The linear phase detector is a half-rate linear phase detector,

When the frequency of the recovered clock signal is less than half of the bit rate of the received data signal, the frequency difference between the received data signal and the recovered clock signal may be detected in addition to the phase difference between the received data signal and the recovered clock signal. Clock and data recovery device.
The method according to claim 7,

The linear phase detector is a half-rate linear phase detector,

And the reset circuit initializes the VCO adjustment voltage to the reference voltage such that the frequency of the voltage controlled oscillator is less than a frequency corresponding to half the bit rate of the received data signal.
The method according to claim 8,

The reference voltage is,

And a voltage lower than a voltage such that the frequency of the voltage controlled oscillator is a frequency corresponding to half of the bit rate of the received data.
The method according to claim 1,

The reset circuit,

Receiving a reset signal to initialize the VCO adjustment voltage to the reference voltage,

And the reset signal is turned on when the bit rate of the received data signal decreases and turned off when the bit rate of the received data signal is maintained or increased.
The method according to claim 10,

The reset circuit,

N-channel MOSFET (NMOS) transistor,

A gate receiving the reset signal;

A drain receiving the reference voltage; And

And a source coupled to the loop filter.