KR101725335B1 - Clock and data recovery circuit - Google Patents

Clock and data recovery circuit Download PDF

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Publication number
KR101725335B1
KR101725335B1 KR1020150172495A KR20150172495A KR101725335B1 KR 101725335 B1 KR101725335 B1 KR 101725335B1 KR 1020150172495 A KR1020150172495 A KR 1020150172495A KR 20150172495 A KR20150172495 A KR 20150172495A KR 101725335 B1 KR101725335 B1 KR 101725335B1
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KR
South Korea
Prior art keywords
signal
voltage
frequency
outputting
received data
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KR1020150172495A
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Korean (ko)
Inventor
변상진
Original Assignee
동국대학교 산학협력단
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Priority to KR1020150172495A priority Critical patent/KR101725335B1/en
Priority to PCT/KR2016/014117 priority patent/WO2017095186A1/en
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Publication of KR101725335B1 publication Critical patent/KR101725335B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The present invention provides a clock and data restoring circuit. More specifically, according to an embodiment of the present invention, a clock and data restoring circuit comprises a linear phase detector, a charge pump, a loop filter, a voltage control oscillator and a reset circuit. The linear phase detector compares the phase difference with the frequency difference between a received data signal and a restored clock signal to output an up/down signal corresponding to a value obtained by the comparison. The charge pump outputs electric current corresponding to the up/down signal input by the linear phase detector. The loop filter outputs adjustment voltage corresponding to the electric current input to the charge pump. The voltage control oscillator restores a clock signal having a frequency and a phase, which correspond to voltage at open circuit (VOC) adjustment voltage output from the loop filter, and outputs the restored clock signal to the linear phase detector. The reset circuit initializes the VOC adjustment voltage to be a reference voltage to allow the frequency of the voltage control oscillator to be less than a frequency corresponding to half of a bit ratio of the received data.

Description

[CLOCK AND DATA RECOVERY CIRCUIT]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data restoration technique, and more particularly, to a clock and data restoration circuit.

Generally, a clock and data restoration circuit is a circuit that generates a clock signal synchronized with a data signal from an input data signal and restores the data signal using the generated clock signal. Clock and data restoration circuits are widely used for LAN, wired / wireless communication, optical communication, and disk drive for data transmission.

In the conventional clock and data recovery circuit, a frequency detector and a phase detector are used to recover a clock signal synchronized with the frequency and phase of the received digital input signal. Conventionally, since both the frequency detector and the phase detector must be used, there is an inefficient problem in terms of hardware implementation.

Korean Patent Publication No. 10-2010-0005948 (Jan. 18, 2010)

Embodiments of the present invention provide a clock and data recovery circuit that can easily recover clock and data through a linear phase detector and a reset circuit.

The clock and data recovery circuit according to an embodiment of the present invention includes a linear phase detector for comparing phase difference and frequency difference between a received data signal and a recovered clock signal and outputting an up / down signal corresponding to the comparison value; A charge pump for outputting a current corresponding to an up / down signal input from the linear phase detector; A loop filter for outputting a VCO adjustment voltage corresponding to the current input from the charge pump; A voltage control oscillator for restoring a clock signal having a frequency and a phase corresponding to a VCO adjustment voltage output from the loop filter and outputting the recovered clock signal to the linear phase detector; And a reset circuit for initializing the VCO adjustment voltage to a reference voltage such that the frequency of the voltage controlled oscillator is less than a frequency corresponding to half of the received data bit rate.

The reference voltage may be set to a voltage that is less than a voltage such that the frequency of the voltage controlled oscillator is a frequency corresponding to half of the received data bit rate.

The linear phase detector includes: an inverter for inverting and outputting a recovered clock signal;

A first latch for receiving the received data and the recovered clock signal and outputting a value corresponding to the input; A second latch for receiving an output signal of the first latch and an output signal of the inverter and outputting a value corresponding to the input; A third latch for receiving the received data and the output signal of the inverter and outputting a value corresponding to the input; A fourth latch for receiving an output signal of the third latch and the recovered clock signal and outputting a value corresponding to the input; A first XOR circuit receiving an output signal of the first latch and the third latch and outputting an up signal; And a second XOR circuit receiving the output signals of the second latch and the fourth latch and outputting a down signal.

The reset signal may be on when the bit rate of the received data decreases and may be off when the bit rate of the received data is maintained or increased.

The reset circuit includes: an NMOS (N-channel MOSFET) transistor; a gate connected to the reset signal; A drain connected to the reference voltage; And a source coupled to the loop filter.

According to the embodiment of the present invention, the phase and frequency can be detected through the linear phase detector to easily recover the clock and data, thereby simplifying the conventional complicated hardware configuration.

In addition, by satisfying the condition that the frequency can be detected by the linear phase detector using the reset circuit, more accurate clock and data restoration is possible.

1 is a block diagram of a clock and data recovery circuit according to an embodiment of the present invention;
Figure 2 is a block diagram of a linear phase detector according to an embodiment of the present invention;
3 is a graph showing the relationship between the frequency of the recovered clock signal of the linear phase detector and the output current of the charge pump according to an embodiment of the present invention
4 is a graph showing a circuit simulation signal waveform of a VCO adjustment voltage in a clock and data recovery circuit according to an embodiment of the present invention.
5 is a comparative diagram comparing the recovered data waveform and received data according to an embodiment of the present invention.

Hereinafter, specific embodiments of the present invention will be described with reference to FIGS. 1 to 5. FIG. However, this is an exemplary embodiment only and the present invention is not limited thereto.

In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions of the present invention, and may be changed according to the intention or custom of the user, the operator, and the like. Therefore, the definition should be based on the contents throughout this specification.

The technical idea of the present invention is determined by the claims, and the following embodiments are merely a means for effectively explaining the technical idea of the present invention to a person having ordinary skill in the art to which the present invention belongs.

In the following description, terms such as " transmission ","transmission"," transmission ","reception", and the like, of a signal or information refer not only to the direct transmission of signals or information from one component to another But also through other components. In particular, "transmitting" or "transmitting" a signal or information to an element is indicative of the final destination of the signal or information and not a direct destination.

1 is a block diagram of a clock and data recovery circuit according to an embodiment of the present invention.

Referring to FIG. 1, a clock and data recovery circuit 100 according to an embodiment includes a linear phase detector 102, a charge pump 104, a loop filter 106, A voltage controlled oscillator 108, a reset circuit 110, and a D flip flop 112. The D flip-

Hereinafter, in one embodiment, the linear phase detector 102 is a half-rate linear phase detector, but the present invention is not limited thereto. The linear phase detector 102 may be a linear phase detector For example, a full-rate linear phase detector, a quarter-rate linear phase detector, etc. may be used.

The linear phase detector 102 receives the received data signal and the recovered clock signal, and outputs the corresponding up / down signal. Here, the received data signal may mean a digital signal to be restored. In addition, the recovered clock signal may be a signal synchronized with the received data signal and used to recover the received data signal. Specifically, the linear phase detector 102 compares the phase difference and the frequency difference between the received data signal and the restored clock signal, and outputs the up / down signal corresponding to the phase and frequency difference to the charge pump 104 to be described later . In general, it is known that a linear phase detector only compares phase differences and a frequency difference is compared using a separate frequency detector. However, in the embodiment of the present invention, a single linear phase detector is used to calculate a received data signal and a recovered clock signal It is possible to detect the phase difference and the frequency difference. At this time, the linear phase detector 102 detects the frequency difference when the frequency of the recovered clock signal is less than half of the reception data bit rate. To this end, the clock and data recovery circuit uses a voltage control oscillator (VCO) regulated voltage for restoring the clock signal using a reset circuit 110, which will be described later, A voltage smaller than a voltage such that the frequency becomes a frequency corresponding to half of the received data bit rate). The clock and data restoring circuit detects the phase difference and frequency difference between the received data and the restored clock by using the linear phase detector 102 and the reset circuit 110, thereby simplifying the hardware configuration. The contents of the frequency of the received data and the frequency of the recovered clock signal using the linear phase detector 102 will be described later with reference to FIG.

The charge pump 104 may receive an up / down signal input from the linear phase detector 102 and output a corresponding current. Specifically, the charge pump 104 may receive the up / down signal input from the linear phase detector 102 and output the up / down current corresponding to the up / down signal to the loop filter 106.

The loop filter 106 may output a VCO adjustment voltage corresponding to the up / down current input from the charge pump 104. Specifically, the loop filter 106 includes a resistor R and a first capacitor C1 connected in series between the output terminal of the charge pump 104 and the ground, a first capacitor C1 connected between the output terminal of the charge pump 104 and the ground, 2 < / RTI > capacitor C2. As described above, the up / down current output from the charge pump 104 is changed to the VCO adjustment voltage through the loop filter 106.

The voltage-controlled oscillator 108 restores a clock having a frequency and phase changed according to the VCO adjustment voltage output from the loop filter 106, and outputs the restored clock to the linear phase detector 102 and a D flip- Lt; / RTI >

The reset circuit 110 may initialize the VCO adjustment voltage of the loop filter 106 to a reference voltage so that the frequency difference between the received data signal and the recovered clock signal can be compared in the linear phase detector 102. Specifically, the reset circuit 110 receives the reset signal and can initialize the VCO adjustment voltage of the loop filter 106 to the reference voltage. Here, the reset signal is a signal that is output when the clock and data recovery circuit starts to operate or when the bit rate of the received data decreases. When the frequency of the voltage control oscillator 108 is smaller than half of the frequency of the received data bit rate The VCO adjustment voltage may be a signal for initializing the VCO adjustment voltage to the reference voltage. If the bit rate of the received data is maintained or increased, the reset signal can be turned off. That is, the reset circuit 110 may initialize the VCO adjustment voltage to the reference voltage such that the frequency of the voltage controlled oscillator 108 is less than the frequency corresponding to half the value of the received data bit rate. Thus, the reference voltage may be set to a value that is less than half the frequency of the voltage-controlled oscillator 108, the received data minimum bit rate. The reset circuit 110 may be implemented as an NMOS transistor. At this time, the reset circuit 110 is connected to a reset signal and a gate (G), a reference voltage and a drain (D) are connected, and the loop filter 106 is connected to a source Or an NMOS (N-channel MOSFET) transistor.

The D flip-flop 112 performs a function of sampling the received data with the recovered clock and restoring the data.

2 is a block diagram of a linear phase detector in accordance with an embodiment of the present invention.

2, the linear phase detector 102 includes an inverter 120, a first latch 122, a second latch 124, a third latch 126, a fourth latch 128, a first XOR circuit < RTI ID = 0.0 > (XOR: exclusive or, 130) and a second XOR circuit 132.

Specifically, the linear phase detector 102 includes an inverter 120 for inverting and outputting the recovered clock signal, a first latch 122 for receiving the received digital input signal and the recovered clock signal, A second lag (124) receiving an output signal of the inverter and an output signal of the inverter, a third lag (126) receiving a received digital input signal and an output signal of the inverter, A first XOR circuit 130 receiving the output signals of the first and third latches and outputting an up signal and a second XOR circuit 130 receiving the output of the second and fourth latches. And a second XOR circuit 132 for receiving signals and outputting a down signal.

The linear phase detector 102 detects the phase difference by comparing the phases of the data received through the input / output signals between the above structures and the restored clock signal, and outputs the up / down signals corresponding thereto.

3 is a graph illustrating a relationship between the frequency of the recovered clock signal of the linear phase detector and the output current of the charge pump according to an embodiment of the present invention. The graph can be obtained by plotting the timing diagrams at different values of the clock frequency. Here, F in means the bit rate of the received data, and I cp can mean the output current of the charge pump 104.

3, when the frequency of the recovered clock signal (the value of the X-axis in FIG. 3) is smaller than half of the received data bit rate, the linear phase detector 102 detects the output current of the charge pump 104 axis values, inversely proportional to the frequency of the restored clock signal, the value of I cp), and the value of the output current if the frequency of the recovered clock signal is equal to or greater than half the bit rate of the received data, the charge pump is the recovered clock signal, 0 ".< / RTI >

That is, the linear phase detector 102 compares the received data bit rate with the frequency of the recovered clock signal in a range where the frequency of the recovered clock signal is less than or equal to one-half of the received data bit rate and detects the difference, So that it is possible to detect the frequency without using it.

If the bit rate of the received data decreases and the frequency of the recovered clock signal becomes larger than half of the received data bit rate F in , the reset circuit 110 outputs the frequency of the recovered clock signal to the received data (I.e., initialized) to be less than half of the bit rate (F in / 2). This allows the linear phase detector 102 to detect not only the phase but also the frequency.

4 is a graph showing a circuit simulation signal waveform of a VCO adjustment voltage in a clock and data recovery circuit according to an embodiment of the present invention.

In FIG. 4, the reference voltage is set to 100 mV, and it can be confirmed that the VCO adjustment voltage is properly locked to approximately 600 mV. The reference voltage depends on the range of the received data bit rate as already explained. For example, if the bit rate of the received data is a fixed value such as 1 Gb / s, the reference voltage may be a voltage that is less than the voltage that causes the frequency of the voltage controlled oscillator 108 to be 500 MHz, Lt; / RTI > If the received data bit rate is a wide band frequency such as 1 Gb / s at 100 Mb / s, the reference voltage is a frequency at which the frequency of the voltage controlled oscillator 108 is half the frequency of 100 Mb / s, which is the lowest bit rate of the received data Lt; RTI ID = 0.0 > 50MHz. ≪ / RTI > That is, the reference voltage should be set to a voltage at which the frequency of the voltage-controlled oscillator 108 can be set to a value less than half of the received data minimum bit rate.

FIG. 5 is a comparative diagram comparing a restored data waveform and received data according to an embodiment of the present invention.

Referring to FIG. 5, it can be seen that the clock and data restoration circuit accurately restores the received data when the restored data waveform is compared with the received data waveform using the clock and data restoration circuit.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, I will understand. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by equivalents to the appended claims, as well as the appended claims.

100: Clock and data recovery circuit
102: Linear phase detector
104: charge pump
106: Loop filter
108: Voltage Controlled Oscillator
110: reset circuit
112: D flip flop
120: Inverter
122:
124: second extract
126: Third catch
128: fourth pull
130: first XOR circuit
132: second XOR circuit

Claims (5)

A linear phase detector for comparing the phase difference and the frequency difference between the received data signal and the recovered clock signal and outputting an up / down signal corresponding to the comparison value;
A charge pump for outputting a current corresponding to an up / down signal input from the linear phase detector;
A loop filter for outputting a VCO adjustment voltage corresponding to the current input from the charge pump;
A voltage controlled oscillator for recovering a clock signal having a frequency and phase corresponding to a VCO adjustment voltage output from the loop filter and outputting the recovered clock signal to the linear phase detector; And
And a reset circuit for initializing the VCO adjustment voltage to a reference voltage such that a frequency difference is detected in the linear phase detector such that the frequency of the voltage controlled oscillator is less than a frequency corresponding to half of the received data bit rate, Data recovery circuit.
The method according to claim 1,
The reference voltage,
And the voltage of the voltage-controlled oscillator is set to a voltage smaller than a voltage that causes a frequency corresponding to half of the received data bit rate.
The method according to claim 1,
Wherein the linear phase detector comprises:
An inverter for inverting and outputting the restored clock signal;
A first latch for receiving the received data and the recovered clock signal and outputting a value corresponding to the input;
A second latch for receiving an output signal of the first latch and an output signal of the inverter and outputting a value corresponding to the input;
A third latch for receiving the received data and the output signal of the inverter and outputting a value corresponding to the input;
A fourth latch for receiving an output signal of the third latch and the recovered clock signal and outputting a value corresponding to the input;
A first XOR circuit receiving an output signal of the first latch and the third latch and outputting an up signal; And
And a second XOR circuit receiving the output signals of the second latch and the fourth latch and outputting a down signal.
The method according to claim 1,
The reset circuit comprising:
Reset signal to initialize the VCO adjustment voltage to a reference voltage,
Wherein the reset signal is turned on when the bit rate of the received data decreases and is turned off when the received data bit rate is maintained or increased.
The method of claim 4,
The reset circuit comprising:
An NMOS (N-channel MOSFET) transistor,
A gate coupled to the reset signal;
A drain connected to the reference voltage; And
And a source coupled to the loop filter.
KR1020150172495A 2015-12-04 2015-12-04 Clock and data recovery circuit KR101725335B1 (en)

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Application Number Priority Date Filing Date Title
KR1020150172495A KR101725335B1 (en) 2015-12-04 2015-12-04 Clock and data recovery circuit
PCT/KR2016/014117 WO2017095186A1 (en) 2015-12-04 2016-12-02 Clock and data recovery apparatus

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KR1020150172495A KR101725335B1 (en) 2015-12-04 2015-12-04 Clock and data recovery circuit

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112234981A (en) * 2019-07-15 2021-01-15 智原科技股份有限公司 Data and clock recovery circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006518130A (en) * 2003-01-17 2006-08-03 ザイリンクス　インコーポレイテッド Clock and data recovery phase-locked loop and fast phase detector architecture
KR20100005948A (en) 2008-07-08 2010-01-18 포항공과대학교 산학협력단 Single bit blind over sampling data recovery circuit and the recovery method used by the circuit
KR20120133685A (en) * 2011-05-31 2012-12-11 (주)에이디테크놀로지 Clock and Data Recovery Circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006518130A (en) * 2003-01-17 2006-08-03 ザイリンクス　インコーポレイテッド Clock and data recovery phase-locked loop and fast phase detector architecture
KR20100005948A (en) 2008-07-08 2010-01-18 포항공과대학교 산학협력단 Single bit blind over sampling data recovery circuit and the recovery method used by the circuit
KR20120133685A (en) * 2011-05-31 2012-12-11 (주)에이디테크놀로지 Clock and Data Recovery Circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112234981A (en) * 2019-07-15 2021-01-15 智原科技股份有限公司 Data and clock recovery circuit
CN112234981B (en) * 2019-07-15 2024-02-27 智原科技股份有限公司 Data and clock recovery circuit

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