JP2855784B2 - Instantaneous interruption switching control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an instantaneous interruption switching control circuit in a system having a redundant configuration of system 0 and system 1.

[Conventional technology]

Conventionally, this kind of uninterruptible switching control circuit, as shown in an example in FIG. 4, calculates the logical sum of the 0-system clock 41 and the 1-system clock 42 by the arithmetic circuit 13 and obtains the obtained clock A4.
In step 3, the flip-flop 14 is used to retime the selection signal A44 for selecting the 0-system and the 1-system, and the resulting selection signal B45 and the selection signal A44 are selected by the both-system clock disconnection signal 46, The resulting selection signal C47 causes 0
Instantaneous interruption switching of system 1 was performed.

FIGS. 5 and 6 are timing charts in the two cases of the phase relationship between the 0-system clock 41 and the 1-system clock 42 in the conventional example of FIG.

[Problems to be solved by the invention]

The conventional non-interruptible switching control circuit described above uses the logic of the 0-system clock 41 and the 1-system clock 42 if the 0-system clock 41 and the 1-system clock 42 have, for example, a phase relationship as shown in FIG. The clock A43 is obtained, and this clock A
A selection signal B45 is output from the selection signal 43 and the selection signal A44, and the 0-system-1 system can be switched without any instantaneous interruption by the selection signal B45. However, in the case of the 0-system clock 41 and the 1-system clock 42 as shown in FIG. 6, even if the logical product is obtained,
There is a defect that the selection signal B45 does not change even when the selection signal A44 comes, as in the case of the clock B43.

[Means for solving the problem]

The instantaneous uninterruptible switching control circuit according to the present invention comprises a clock A and a clock B, which are supplied with a 0-system clock and a 1-system clock in a redundant configuration and have a pulse width of about a half cycle of the 0-system clock and the 1-system clock. And a mono multi that outputs
An arithmetic circuit that performs a NOR operation on the clock A and the clock B and outputs a clock C; a clock loss detection circuit that outputs a dual-system clock disconnection signal based on the 0-system clock and the 1-system clock; A selection signal A for selecting either the clock or the first system clock
A flip-flop that retimed by the selection signal A and the clock C to output a selection signal B; and selects and selects the selection signal A and the selection signal B by the both-system clock cutoff signal. And a selection circuit for outputting the signal C.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 3 is a timing chart of the embodiment shown in FIG.

The 0-system circuit 2 operates with a clock 21 output from the clock generator 1 and outputs a 0-system signal 22 and a 0-system clock 23. The first system circuit also operates by the clock D21 output from the clock generator 1, and outputs the first system signal 24 and the first system clock 25. Among them, the 0-system signal 22 and the 1-system signal 24 are input to the selection circuit B4 to select the 0-system and 1-system, and the signal A2
6 is output. In addition, 0 system clock 23 and 1 system clock 2
5 is input to the selection circuit C5, and 0 system and 1 system are selected.
Clock E27 is output. The common circuit 6 outputs the signal A26,
It operates according to the clock E27 and outputs a final output signal 28.

Next, when you want to switch between system 0 and system 1,
The control circuit 7 outputs a selection signal A29. Also, the clock A30 and the clock B31 in which the pulse widths of the 0-system clock 23 and the 1-system clock 25 are reduced to about 1/2 cycle by the monomulti 8 are output, and the arithmetic circuit 9 performs a NOR operation on the clocks A30 and B31. Clock C32 is output. Then, the selection signal A29 is retimed by the clock C32 using the flip-flop 10, and the selection signal B33 is output. The selection is made by the system and system 1 clock cutoff signals 34, and the selection signal C35 is output. The selection circuit B4 and the selection circuit C5 are switched by the selection signal C35.

〔The invention's effect〕

As described above, according to the present invention, when it is desired to switch between the 0 system and the 1 system without instantaneous interruption, the selection signal A is output from the control circuit, and the pulse width of the 0 system clock and the 1 system clock is reduced by 1 / mono in mono-multi.
The clock A and the clock B having about two cycles are output. Then, the operation circuit outputs a clock C obtained by performing a NOR operation on the clock A and the clock B, and the selection signal A is output by the flip-flop by using the clock C to output the selection signal B. Then, the selection circuit selects the selection signal A and the selection signal B by using both the 0 system clock and the 1 system clock cutoff signal, outputs the selection signal C, and controls the 0 system by controlling the selection signal C. Even if the clock and the first system clock are illustrated in FIG.
Even in the case illustrated in FIG. 13B, there is an effect that the switching can be performed without an instantaneous interruption.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
The timing chart of the embodiment shown in FIG.
FIG. 4B is a diagram showing two cases of a 0-system clock and a 1-system clock. FIG. 4 is a block diagram showing an example of a conventional hitless switching control circuit, and FIGS. 4
It is a timing chart of the conventional example of the figure. 7: control circuit, 8: mono-multi, 9: arithmetic circuit,
10 ... Flip-flop, 11 ... Clock disconnection detection circuit,
12 ... Selection circuit A.

Claims (1)

(57) [Claims] 1. A mono-multi which inputs a 0-system clock and a 1-system clock having a redundant configuration and outputs a clock A and a clock B whose pulse widths are set to about 1/2 cycle of the 0-system clock and the 1-system clock. An arithmetic circuit that performs a NOR operation on the clock A and the clock B and outputs a clock C; a clock disconnection detection circuit that outputs a dual-system clock disconnection signal based on the 0-system clock and the 1-system clock;
A control circuit that outputs a selection signal A for selecting either the 0-system clock or the 1-system clock, and a flip-flop that re-timing the selection signal A by the clock C and outputs a selection signal B And a selection circuit for selecting the selection signal A and the selection signal B based on the both-system clock disconnection signal and outputting a selection signal C.