JPH03117129A - Bit synchronizing circuit - Google Patents

Abstract

PURPOSE:To realize the bit synchronizing circuit against a data input having many jitters by delaying the data, detecting a logical variation of a near-by phase, and finding a phase shifted by (m)=(n-1)/2 only against only one logical variation. CONSTITUTION:A phase detecting circuit 200 for detecting a phase shifted by a delay element portion of an (m)=(n-1)/2 piece portion and holding it as a new latch phase only in the case a variation of only one logical variation point is detected is constituted. In the case only one logical variation is generated, in an output state of exclusive OR circuits 30-33, it is decided that a phase shift is generated, and a latch phase is changed to data of a point shifted by (m)=2. On the other hand, in the case there is no logical variation or in the case there are plural variation points, it is decided to be entirely normal or generation of intermittent jitters and a selected phase is held.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bit synchronization circuit for resynchronizing data with phase independence or locking.
The above N
This invention relates to a bit synchronization circuit that resynchronizes RZ data with the reference clock.

[Conventional technology]

Conventionally, this type of bit synchronous circuit uses a control method in which a clock or data is delayed by multiple delay elements, each is latched by a D7 lip-flop, and hunting is performed until a phase that satisfies the AND condition is found. ing.

[Problem to be solved by the invention]

The conventional bit synchronization circuit described above secures only a plus α margin for flip-flop set-up time and hold time in circuits with basically little jitter, such as logic circuits, rather than at the center of data change points. Because this control method uses jitter-containing signals that have been waveform-shaped from various transmission devices, logic is not determined based on the center of the signal, or in other words, the center phase of the signal eye pattern. There was a problem that it could not be used for logical judgment of signals from.

[Failure to solve the problem]

The bit synchronization circuit of the present invention has fobp! By inputting the NRZ data of I and the reference clock of f, R2 whose phase is independent from this NRZ data, and delaying the phase of the NRZ data to the optimum position, the NRZ data is resynchronized with the reference clock. In a bit synchronization circuit, for a period of 1/fo, "/fo=T8+TH+(n-1)TD+TJ",
TS: D flip-flop set-up time TJ: D flip-flop hold time n: Odd number of 3 or more TD: Delay amount of delay element TJ: NRZ data jitter amount TS: (n-1) cascaded connections that satisfy TJ=TD a first D flip-flop whose D input is the input of the first delay element of the delay element; and a second D flip-flop whose D input is the output of the first delay element; Tube n-
a data phase delay circuit having n D flip-flops connected as an n-th D flip-flop whose output is the output of one delay element and whose clock input is the reference clock; and this data phase delay circuit. The above 1st~
Among the outputs of the n-th 7 lip-flops, the first D flip-flop, the second D7 lip-flop, and the second D7
1j knob 70 knob, third D flip-flop... n-1st D flip-flop, n-1 combinations of n-th D flip-flop are compared logically, and only one change in logic change point is detected. a phase detection circuit that detects a phase shifted by m=nM1 delay elements and holds it as a new latch phase only when −
It has a selection circuit that selects and outputs the determined optimal output from among the outputs of the n-th D flip-flop.

[Effect]

In the present invention, data is delayed, logic changes in adjacent phases are detected, and a phase shifted by m = (n: number of delay elements) (approximately the center phase) is detected only for -1 to a single logic change. ) find.

〔Example〕

Embodiments of the present invention will be described in detail below based on the drawings.

The figure is a block diagram showing one embodiment of the present invention, and shows an example where the number of D7 lip-flops is n=5.

In the figure, 100 is a data phase delay circuit, and from the NR2 data input, delay elements 1G and 11 having the same amount of delay are connected.
.
has the output of the delay element 10 as its D input, the D7 lip 70 tube 22 has the output of the delay element 11 as its D input, the D flip-flop 23 has the output of the delay element 12 as its D input, and the D flip-flop 24 has the output of the delay element 13 as its D input. A latch circuit for five data phases is configured with the output of the D input as the D input.

These delay elements 10 to 13 have a period of "/f".

For '/fo = TS + TH + (n 1) TD + TJ where 'rs: I) flip-flop set-up time TH
: D flip-flop hold time n: Odd number of 3 or more TD: Delay amount of delay element TJ: NRZ data jitter amount 'rs: (n-1) cascaded delay elements satisfying TH=TD. , the delay elements 10 to 13 and the D flip-flop 20
24 constitute the data phase delay circuit 100.

200 is a phase detection circuit, and this phase detection circuit 200 is
an exclusive OR circuit 30 whose inputs are the Q output of the D flip-flop 20 and the Q output of the D flip-flop 21;
Similarly, an exclusive OR circuit 3 receives the Q output of the D flip-flop 21 and the Q output of the D flip-flop 22.
1, the Q output of the D flip-flop 22, and the Q output of the D flip-flop 23 as inputs.
2, an exclusive OR circuit 3 which receives as inputs the Q output of the D flip-flop 23 and the Q output of the D flip-flop 24.
3, and a decoder which outputs the outputs of these exclusive OR circuits 30 to 33 as A1 to A4, respectively, as the B1 to B4 logics shown in the truth table of the decoder and selection circuit below, which is the truth table of the decoder and selection circuit. 40 and
This decoder "400B1 output and decoder "40B1
A differentiating circuit 60 that takes the logical product of the Q1 output of the D flip-flop 50 whose output is delayed by one clock and inverted, and a differential circuit 60 that takes the logical product of the Q1 output of the D flip-flop 50 whose output is delayed by one clock and inverted, and similarly, the Q2 to Q2 of the D flip-flop 50 for the B2 to B4 outputs of the decoder 40. A differentiation circuit consisting of the Q4 output and corresponding AND circuits 61 to 63, an OR circuit 64 which receives the outputs of the AND circuits 60 to 63, and outputs of B1 to B4 of the decoder 40 to D1 to D1, respectively. D4 is manually operated, the output of the OR circuit 64 is used as an enable input, the reference clock is used as a clock input, and D
1 to D4 It is composed of a D flip-flop 70 that outputs outputs Q1 to Q4 according to human power.

Of the outputs of the D flip-flops 20 to 24 of the data phase delay circuit 100, the D flip-flop 20
．． D flip-flop 21 and D flip-flop 21.
Only when a change in the logic change point of the stutter is detected by comparing the logic of n-1 combinations of the D flip-flop 22 and +1+...the n-1th D flip-flop and the n-th D flip-flop. A phase detection circuit 200 is configured to detect a phase shifted by m=n-1 delay elements and hold it as a new latch phase.

Reference numeral 80 denotes a selection circuit, and this selection circuit 80 uses the Q1 to Q4 outputs of the D flip-flop TO as selection control inputs for B1 to B4, respectively, and uses the Q output of the D flip-flop 24 as Xl.
input, the Q output of the D flip-flop 23 as the input of X2, the Q output of the D flip-flop 21 as the input of X3, the Q output of the D flip-flop 20 as the input of 1 from the inputs X1 to X4 with the selection logic according to the selection circuit truth table of
Select one and send it as NRZ data output.

The selection circuit 80 is configured to input the selection signal from the phase detection circuit 200, select the determined optimal output from among the outputs of the first D flip-flop to the n-th D flip-flop, and output it. ing.

Next, the operation of the embodiment shown in this figure will be explained.

As a phase control method, when only one logic change occurs among the output states of the exclusive OR circuits 30 to 33, it is assumed that a phase shift has occurred, and the latch phase is changed to the data at a point shifted by m = 2. do.

If there is no logic change or if there are multiple change points, the selected phase is held as either completely normal or as intermittent jitter.

Here, the operation of the circuit when the phase changes will be explained.

First, if there was a logic change between the D flip-flop 20 and the D7 lip-flop 21 in the past, only the Q1 output of the D flip-flop 70 would be held at "1".
As a result, the output of the D flip-flop 23 delayed by m=2 from the logic change point is selected by the selection circuit 80 and output.

At this time, at the timing of the next reference clock, D
Assume that the exclusive OR circuit 31 inputting the Q outputs of the flip-flop 21 and the D flip-flop 22 becomes "1". Then, D7 rib 70 rib 50 93
The differential output composed of the output and the AND circuit 62 is “1”.
” is input to the enable input of the D flip-flop 70 through the OR circuit 64. According to this enable input, the D flip-flop 70 uses the exclusive OR circuit 3 at the rising timing of the next reference clock.
Latch output logic from 0 to 33.

At this time, only the exclusive OR circuit 31 is "1", so in the decoder 40, only the B2 output is "1".

Bl, B3. B4 output decodes as “0”, m=
The Q1 to Q4 outputs are sent to the selection circuit 80 to select the Q outputs of the D flip-flops 24 having two different phases.
The selection circuit 80 selects and outputs the Q output of the D flip-flop 24.

If the logic change point is the same at the rising timing of the next reference clock, the output of the AND circuit 62 is "0", and the enable signal is not input, so D
The output of the 7-rib flop 70 remains unchanged.

In addition, there is no logic change in the exclusive OR circuits 30 to 33,
Similarly, when all the outputs are "0", the enable signal is not input, so the output of the D7 lip-flop 70 does not change. Similarly, when "1" occurs in at least two or more of the exclusive OR circuits 30 to 33 (when there are multiple logic change points), the output of the decoder 40 is
Since it is OJ, D flip-flop 70 does not latch the new state, but retains the previous state.

〔Effect of the invention〕

As explained above, the present invention delays data, detects logic changes in adjacent phases, and shifts m = -7-(n: number of delay elements) only for a single -1 logic change. By finding the phase (center phase), it is possible to realize a bit synchronization circuit for data input with a lot of jitter.

[Brief explanation of drawings]

The figure is a block diagram showing one embodiment of the present invention. 10-13...delay element, 20-24...D flip-flop, 30-33...exclusive OR circuit, 40...decoder, 50...D flip-flop, 60-63...AND circuit, 64 fist...OR circuit, 70...D flip-flop, 80...
...Selection circuit, 100...Data phase delay circuit, 2
00...Phase detection circuit.

Claims (1)

[Claims] NRZ data of f_0bps and a reference clock of f_0Hz whose phase is independent from the NRZ data are input, and the phase of the NRZ data is delayed to an optimal position, thereby converting the NRZ data to the reference clock. In a bit synchronization circuit that resynchronizes with
J However, T_S: D flip-flop setup time T_H: D flip-flop hold time n: Odd number of 3 or more T_D: Delay amount of delay element T_J: NRZ data jitter amount T_S: (n-1) pieces that satisfy T_H=T_D cascaded delay elements of;
A first D flip-flop whose D input is the input of the first delay element of this delay element, and a second D flip-flop whose D input is the output of the first delay element, hereinafter the n-th
a data phase delay circuit having n D flip-flops connected as an n-th D flip-flop whose D input is the output of one delay element and whose clock input is the reference clock; Among the outputs of the first to n-th D flip-flops, the first D flip-flop, the second D flip-flop and second D flip-flop, the third D flip-flop, and... m = (n-1/2) delay elements only when a change in only one logic change point is detected by performing logical comparison of n-1 combinations of D flip-flops and n-th D flip-flops. a phase detection circuit that detects the phase shifted by the amount and holds it as a new latched phase; and a selection signal from this phase detection circuit is input to determine the output of the first D flip-flop to the n-th D flip-flop. A bit synchronization circuit comprising a selection circuit that selects and outputs the optimal output.