JPH0918462A - Collision preventing device and method therefor - Google Patents

Abstract

PURPOSE: To provide a collision preventing device which is low in use frequency and can be inexpensively manufactured by a simple constitution and with fewer number of parts. CONSTITUTION: Input data DA 1 is latched to a flip-flop circuit 11 in accordance with a clock signal CK 3 for input, this latched data DA 2 is latched to a flip- flop circuit 12 in accordance with a clock signal CK 6 for data holding and this latched data DA 2 is latched to a flip-flop circuit 13 in accordance with a clock signal CK 4 for output. The data holding phase of the clock signal CK 6 for data holding is controlled so as not to generate the destruction of data in accordance with the phase difference of the clock signal CK 3 for input and the clock signal CK 4 for output by a timing pulse generation circuit 1 4, a collision monitoring pulse preparation circuit 15, a flip-flop circuit 16, a mask pulse preparation circuit 1 7, an OR circuit 18, an AND circuit 19 and an inversion circuit 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention protects data from being destroyed when the phase difference between a data input timing signal and a data output timing signal, which have the same frequency but an indeterminate phase difference, becomes a predetermined value. The present invention relates to a collision prevention device and a collision prevention method.

[0002]

2. Description of the Related Art Generally, in a digital exchange,
The process of giving the data received from one device to another device is performed.

In this case, an input timing signal for receiving data from a certain device and an output timing signal for supplying the received data to another device may have the same frequency and an indefinite phase difference. is there.

In such data supply, when the phase difference between both timing signals reaches a predetermined value (for example, 0), that is, when both timing signals collide with each other, the data may be destroyed.

In order to deal with the data destruction due to the collision of the timing signals, the following two collision prevention methods have been conventionally used.

The first method is to receive the data given from a device by a clock signal having a frequency of ten-odd times (16 times, 32 times, 64 times, etc.) the frequency and change each bit from the change point of the data. Position is determined, and when the 1-bit 2/3 minute data does not change from the beginning of each bit,
This is a method of receiving as 1 bit. In this case, the transmission is performed according to the transmission clock signal.

The second method uses a phase difference absorption circuit composed of a large-scale integrated circuit of a variable period / asynchronous transmission / reception circuit (UART (SIO etc.)) and a memory circuit or a buffer circuit, and their peripheral circuits. Is the way.

[0008]

However, in the above first method, a clock signal having a frequency of ten times more than the data frequency is required, and the change point detection circuit, the data prediction circuit,
Since a data judgment circuit or the like is required, there is a problem that the circuit becomes complicated and the number of parts increases.

Further, in the second method, each component is expensive and large as compared with the general integrated circuit, so that there is a problem in terms of manufacturing cost and component mounting efficiency.

[0010]

In order to solve the above-mentioned problems, the present invention holds the data inputted according to the data input timing signal according to the data holding timing signal and changes the phase of the data holding timing signal. The control is performed based on the phase difference between the data input timing signal and the data output timing signal.

[0011]

In the above structure, the data input according to the data input timing signal is held according to the data holding timing signal before being output according to the data output timing signal.

In this case, the phase of the data holding timing signal is controlled based on the phase difference between the data input timing signal and the data output timing signal so as not to cause data destruction.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

[One Embodiment] [Structure] FIG. 1 is a block diagram showing the structure of one embodiment of the present invention.

In the figure, a flip-flop circuit 11
Has a function of latching the input data DA1 according to the input clock signal CK3.

The flip-flop circuit 12 has a function of latching the latch data DA2 of the flip-flop circuit 11 according to the holding clock signal CK6.

The flip-flop circuit 13 has a function of latching the latch data DA3 of the flip-flop circuit 12 according to the transmission clock signal CK4.

Note that, for the data holding clock signal CK6 and the data output clock signal CK4, for example, the rising timing of one clock signal is used as the data output timing, and the falling timing is used as the data holding timing. It is also used as one clock signal.

The timing pulse generation circuit 14, the collision monitoring pulse generation circuit 15, and the flip-flop circuit 16
The mask pulse generation circuit 17, the OR circuit 18, the AND circuit 19, and the inverter circuit 20 prevent data destruction based on the phase difference between the input clock signal CK3 and the output clock signal CK4. , And has a function of controlling the phase of the holding clock signal CK6.

Here, the timing pulse generation circuit 14
Is the reception clock signal CK3 and the reference clock signal CK
1 has a function of creating various timing pulse signals. The reference clock signal CK1 is synchronized with the input clock signal CK3 and has a frequency four times that of the clock signal CK3.

As the timing pulse, a timing pulse signal TM1 for resetting the flip-flop circuit 16 and a timing pulse signal TM for defining the generation timing of a collision monitoring pulse signal SP1 described later.
2 and a timing pulse signal TM3 that defines the generation timing of the masking pulse signal MS1 described later.

The collision monitoring pulse generating circuit 15 and the flip-flop circuit 16 determine whether or not the phase difference between the input clock signal CK3 and the output clock signal CK4 is within a predetermined range including the data destruction point. Have a function.

Mask pulse generation circuit 17 and OR circuit 1
8, the AND circuit 19, and the inverting circuit 20 set the data holding timing to the first position when the phase difference does not exist within the predetermined range, and when the phase difference exists, the second position is set to the second position. It has the function of setting to the position.

The collision monitoring pulse generating circuit 15 has a function of generating the collision monitoring pulse signal SP1 based on the timing pulse signal TM2. The collision monitoring pulse signal SP1 defines the predetermined range.

The flip-flop circuit 16 receives the collision monitoring pulse signal SP based on the transmission clock signal CK4.
By latching 1, it has a function of determining whether or not the phase difference is within the predetermined range.

The mask pulse creating circuit 17 has a function of creating a masking pulse signal MS1 for masking the falling edge of the transmission clock signal CK4 based on the timing pulse TM3.

The OR circuit 18 and the AND circuit 19 do not mask the falling edge of the output clock signal CK4 when the phase difference does not exist within the predetermined range, and when it does, the falling edge. Is masked with the masking pulse signal MS1 to switch the data holding timing between the first timing and the second timing.

Here, the OR circuit 18 includes the latch output MC1 of the flip-flop circuit 16 and the mask pulse signal M.
It has a function of outputting the gate pulse signal MS2 of the AND circuit 19 by taking the logical sum with S1.

The AND circuit 19 has a gate pulse signal M.
It has a function to gate the output clock signal CK4 based on S2.

The inverting circuit 20 inverts the output of the AND circuit 19 to output the data holding clock signal CK6.
Has the function of outputting.

[Operation] The operation of the above configuration will be described.

First, the outline of the operation will be described.

The input data DA1 is latched by the flip-flop circuit 11 according to the input clock signal CK3. The latch data DA2 is latched in the flip-flop circuit 12 according to the holding clock signal CK6. The latch data DA3 is latched in the flip-flop circuit 13 according to the output clock signal CK4. This latched data becomes the output data DA4.

The phase of the holding clock signal CK6 is controlled according to the phase difference between the input clock signal CK3 and the output clock signal CK4. This prevents the occurrence of data destruction.

The phase of the data holding clock signal CK6 is controlled as follows, for example.

First, the collision monitoring pulse generation circuit 15 and the flip-flop circuit 16 cause the input clock signal CK.
It is determined whether or not the phase difference between 3 and the output clock signal CK4 is within a predetermined range including the data destruction point.

If the phase difference does not exist within the predetermined range, the mask pulse generation circuit 17 or the like sets the phase of the holding clock signal CK6 to the first position, and if there is, the second position. Is set to.

As a result, when data destruction is likely to occur, the phase of the holding clock signal CK6 is changed from the first position to the second position and data destruction is prevented. The above is the outline of the operation.

Next, the details of the operation will be described with reference to the timing charts of FIGS.

2 and 3 are timing charts in the normal case, that is, in the case where data destruction does not occur (when collision does not occur), and FIG. 4 and FIG.
Is when data destruction occurs (when a collision occurs)
6 and 7 show a case where data destruction occurs and a case where data destruction does not occur alternately due to jitter and the like.

In FIGS. 2 to 7, for example, the point where the phase difference between the input timing signal CK3 and the output timing signal is 180 degrees is the data destruction point.

First, the operation when data destruction does not occur will be described with reference to FIGS.

FIG. 2 shows the operation when the phase difference between the input timing signal CK3 and the output timing signal is smaller than 180 degrees and no data destruction occurs.
FIG. 3 shows the operation when the phase difference is smaller than 180 degrees and no data destruction occurs.

In the case of FIG. 2, the input data DA1 (see FIG.
2A is latched by the flip-flop circuit 11 at the rising timing of the input clock signal CK3 (see FIG. 2C), as shown in FIG.

The latch data DA2 (see FIG. 2 (h)) will be described later in detail, but as shown in FIG. 2 (a), at the falling timing of the output clock signal CK4 (see FIG. 2 (i)). , And is latched by the flip-flop circuit 12.

This latch data DA3 (see FIG. 2 (j)) is output clock signal C as shown in FIG.
At the rising timing of K4, the flip-flop circuit 1
Output data DA4 (see FIG. 2 (k))
Becomes

The timing generation circuit 14 includes an input clock signal CK3 and a reference clock signal CK1 (see FIG. 2A).
2) and a clock signal CK2 (see FIG. 2B) having a frequency twice that of the input clock signal CK3 (see FIG. 2B), the timing pulse signal TM1 (FIG. 2, TM2) synchronized with the input clock signal CK3. , TM3 is generated.

The flip-flop circuit 16 is reset at the falling timing of the timing pulse signal TM1. As a result, the latch output MC1 of the flip-flop circuit 16 is set to the high level.

The falling timing of the timing pulse signal TM1 is set at a position delayed by a quarter cycle from the rising timing of the input clock CK3. As a result, the latch output MC of the flip-flop circuit 16
1 is also set to the high level at a position delayed by a quarter cycle from the rising timing of the input clock CK3.

The collision monitoring pulse generation circuit 14 generates a positive collision monitoring pulse signal SP1 (see FIG. 2 (e)) according to the timing pulse signal TM2. The center phase of the pulse of the collision monitoring pulse signal SP1 (see FIG. 2D) is set to the falling timing of the reception clock CK3, and the width thereof is a quarter cycle width of the input clock signal CK3. It is set.

The collision monitoring pulse signal SP1 is supplied to the flip-flop circuit 16 and the output clock signal CK4.
Is latched at the rising timing of. As a result, the latch output MC1 of the flip-flop circuit 16 is switched from the high level to the low level if the rising timing of the output clock signal CK4 is within the pulse of the collision monitoring pulse signal SP1. Hold on to the level.

In the case of FIG. 2, since the data destruction does not occur, the rising timing of the output clock signal CK4 does not exist within the pulse of the collision monitoring pulse signal SP1. As a result, the latch output MC1 of the flip-flop circuit 16 is held at the high level.

The mask pulse creating circuit 17 creates a positive polarity masking pulse signal MS1 (see FIG. 2 (f)) in accordance with the timing pulse signal TM3. The central phase of the pulse of the masking pulse signal MS1 (see FIG. 2E) is set to the falling timing of the input clock signal CK3, and the width is set to the width of a half cycle of the receiving clock signal. ing.

The mask pulse signal MS1 is supplied to the OR circuit 1
8 and is logically ORed with the latch output MC1 of the flip-flop circuit 16. As a result, the latch output M
If C1 is high level, this latch output MC1
It is supplied to the AND circuit 19 as the gate signal MS2, and if it is at the low level, the masking pulse signal MS1 is supplied as the gate signal MS2.

In the case of FIG. 2, since the latch output MC1 is at the high level, this latch output MC1 is the gate signal MS.
2 is supplied to the AND circuit 19. As a result, in this case, the output clock signal CK4 directly passes through the AND circuit 19.

The transmission clock signal CK4 that has passed through the AND circuit 19 is used as the clock signal CK5 and the inverting circuit 2
0 is supplied. The clock signal CK5 supplied to the inverting circuit 20 is inverted, and then the holding clock signal CK6.
Is supplied to the flip-flop circuit 12. As a result, the latch data DA of the flip-flop circuit 11
2 is latched at the falling timing of CK4 of the transmission clock signal.

Although detailed description is omitted, in the case of FIG. 3 as well, the latch output of the flip-flop circuit 16 is held at the high level, and therefore the same operation as in the case of FIG. 2 is performed. The above is the operation when data destruction does not occur.

Next, the operation when data destruction occurs will be described with reference to FIGS. 4 and 5.

In the following description, the operation in this case will be described focusing on the part different from the operation in the case where data destruction does not occur.

FIG. 4 shows an operation when data destruction occurs when the phase difference between the input timing signal CK3 and the output timing signal is slightly smaller than 180 degrees. FIG. 5 shows an operation when data destruction occurs when the phase difference is slightly larger than 180 degrees.

In the case of FIG. 2, the rising timing of the output clock signal CK4 does not exist within the pulse of the collision monitoring pulse signal SP1. Therefore, in this case, the latch output MC1 of the flip-flop circuit 16 becomes high level.

On the other hand, in the case of FIG. 4, the rising timing of the output clock signal CK4 exists within the pulse of the collision monitoring pulse signal SP1. Therefore, in this case, the latch output MC1 (see FIG. 4 (i)) of the flip-flop circuit 16 is switched from the high level to the low level at the rising timing of the output clock signal CK4, as shown in FIG. To be

As a result, in this case, as shown in FIG. 4J, the masking pulse signal MS1 appears as the gate signal MS2. As a result, in this case, the output clock signal CK4 is gated by the masking pulse signal MC1.

As a result, in this case, the falling timing of the output clock signal CK4 is masked by the masking pulse signal MS1. As a result, in this case, the clock signal CK5 (see FIG. 4 (l)) whose fall timing is defined by the fall timing of the masking pulse signal MC1 is obtained as shown in FIG.

As a result, in this case, the latch data DA2 of the flip-flop circuit 11 is latched in the flip-flop circuit 12 at the falling timing of the masking pulse signal MS1. As a result, the holding clock signal C
Since it is possible to obtain the effect of advancing the phase of K6 in a direction in which the rising timing thereof deviates from the change point of the latch data DA2 (the rising timing of the input clock signal CK3), data destruction is prevented.

Although a detailed description is omitted, in the case of FIG. 5 as well, as in the case of FIG.
The rising timing of the latch data DA
Since the effect of advancing in the direction deviating from the change point of 2 (the rising timing of the clock signal CK3) is obtained, data destruction is prevented. The above is the operation when data destruction occurs.

Next, with reference to FIGS. 6 and 7, a case will be described in which the operation when data destruction does not occur and the operation when it occurs due to jitter or the like are alternately repeated.

FIG. 6 shows a case where two operations are alternately repeated when the phase difference between the input timing signal CK3 and the output timing signal is slightly smaller than 180 degrees. FIG. 7 shows a case where two operations are alternately repeated when the phase difference is slightly larger than 180 degrees.

In the case of FIG. 6, the operation described in FIG. 2 and the operation described in FIG. 4 are alternately repeated. As a result, the bit length of the latch data DA3 of the flip-flop circuit 12 extends or contracts by a length of 1/8 of the original bit length as shown in FIG. 6 (m). However, the output data DA4 is output with the original bit length and timing as shown in FIG. 6 (n).

In the case of FIG. 7, the operation of FIG. 3 and the operation of FIG. 5 are alternately repeated. As a result, the bit length of the latch data DA3 of the flip-flop circuit 12 extends or contracts by a length of ⅜ of the original bit length, as shown in FIG. 7 (m). However, the output data DA4 is
As shown in FIG. 7 (n), the original bit length and timing are output.

[Effect] According to this embodiment described in detail above, the following effects can be obtained.

(1) First, according to this embodiment, the data DA2 latched according to the input clock signal CK3 is used.
Is held based on the holding clock signal CK6, and the phase of the holding clock signal CK6 is input clock signal C
Since the data destruction is prevented by controlling based on the phase difference between K3 and the output clock signal CK4, the following four effects can be obtained.

Since the maximum frequency required as the clock frequency may be four times as high as the data frequency, the required maximum frequency can be significantly reduced as compared with the prior art.

Since the change point detecting circuit, the data predicting circuit, the data judging circuit, etc. are not required, the circuit structure can be simplified and the number of parts can be reduced as compared with the prior art. As a result, the component mounting area can be reduced.

Since each component can be realized by a general-purpose integrated circuit, the manufacturing cost can be reduced and the component mounting area can be reduced.

It is possible to realize a device which is less likely to be affected by the jitter of the input clock signal CK3 and the output clock signal CK4.

(2) It is judged whether or not the phase difference between the input clock signal CK3 and the output clock signal CK4 is within a predetermined range. If not, the phase of the data holding clock signal CK4 is determined. It is set to the first position, and if it exists, it is set to the second position that can prevent data corruption. Therefore, not only when data corruption occurs, but also when it is likely to occur. In addition to being able to deal with this, the phase control configuration of the data holding clock signal CK4 can be simplified.

(3) According to this embodiment, the holding clock signal CK6 is also used as the output clock signal CK4. Therefore, the structure for generating the holding clock signal CK6 can be simplified. You can

(4) According to this embodiment, the mask pulse signal M is synchronized with the input clock signal CK3.
Since the phase of the holding clock signal CK6 is changed by generating S1 and masking the output clock signal CK4 with this masking pulse signal MS1, this phase can be changed with a simple configuration. .

(5) According to this embodiment, by changing the frequency of the collision monitoring signal, etc.
It can be applied to various communications and data transmission.

[Other Embodiments] Although one embodiment of the present invention has been described in detail above, the present invention is not limited to the above embodiment.

For example, in the above embodiment, the case where the reference clock signal CK1 having a frequency four times the data frequency is used has been described. However, in the present invention, the flip-flop circuit 11 is changed to a 4-bit serial / parallel conversion circuit, the flip-flop circuit 12 is changed to a 4-bit flip-flop circuit, and the flip-flop circuit 13 is changed to a 4-bit parallel / serial conversion circuit. By converting the circuit into a circuit and replacing the collision monitoring pulse signal SP1 with the clock signal input to the 4-bit flip-flop circuit, data destruction without using the reference clock signal CK1 having a frequency four times the data frequency. Can be prevented.

[0083]

As described in detail above, according to the present invention,
Occurrence of data destruction by holding the data input according to the input timing signal according to the holding timing signal and controlling the phase of this holding timing signal based on the phase difference between the input timing signal and the output timing signal. Since the above is prevented, the following effects can be obtained.

Since the maximum frequency required as the clock frequency may be four times as high as the data frequency, the required maximum frequency can be significantly reduced as compared with the prior art.

Since the change point detecting circuit, the data predicting circuit, the data judging circuit, etc. are not required, the circuit structure can be simplified and the number of parts can be reduced as compared with the prior art. As a result, the component mounting area can be reduced.

Since each component can be realized by a general-purpose integrated circuit, the manufacturing cost can be reduced and the component mounting area can be reduced.

It is possible to realize a device that is not easily affected by the jitter of the input timing signal and the output timing signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation under normal conditions.

FIG. 3 is a timing chart showing a normal operation.

FIG. 4 is a timing chart showing an operation at the time of collision.

FIG. 5 is a timing chart showing an operation at the time of collision.

FIG. 6 is a timing chart showing an operation when a normal time and a collision time are repeated.

FIG. 7 is a timing chart showing an operation when a normal time and a collision time are repeated.

[Explanation of symbols]

 11, 12, 13, 16 ... Flip-flop circuit 14 ... Timing pulse creation circuit 15 ... Collision monitoring pulse creation circuit 17 ... Mask pulse creation circuit 18 ... OR circuit 19 ... AND circuit 20 ... Inversion circuit

Claims (5)

[Claims] 1. A collision prevention device for preventing data destruction caused by a predetermined phase difference between a data input timing signal and a data output timing signal having the same frequency and an uncertain phase difference. Data holding means for holding the data input according to the data input timing signal according to the data holding timing signal, and the data holding based on the phase difference between the data input timing signal and the data output timing signal. A collision prevention device, comprising: destruction prevention means for preventing the occurrence of data destruction by controlling the phase of a use timing signal. 2. The determination means for determining whether or not the phase difference between the data input timing signal and the data output timing signal is within a predetermined range including the predetermined value. If the determination means determines that the phase difference does not exist within the predetermined range, the phase of the data holding timing signal is set to the first position, and if it is determined that the phase difference exists, the data The collision prevention device according to claim 1, further comprising a phase changing unit that sets a second position capable of preventing breakage. 3. The data output timing signal and the data holding timing signal use the timing of one edge of one clock signal as the data output timing and the other edge timing as the data holding timing. The anti-collision device according to claim 1, wherein when used, it is also used as one clock signal. 4. The phase changing means, in synchronization with the data input timing signal, generates a pulse signal for masking a data holding edge of the clock signal, and the judging means, 4. The collision prevention device according to claim 3, further comprising masking means for masking a data holding edge of the clock signal when it is determined that the phase difference is within the predetermined range. 5. A collision prevention method for preventing data destruction caused by a phase difference between a data input timing signal and a data output timing signal having the same frequency and an uncertain phase difference, which is caused by a predetermined value. A data holding process for holding the data input according to the data input timing signal according to the data holding timing signal; and the data holding based on the phase difference between the data input timing signal and the data output timing signal. And a destruction prevention process for preventing the occurrence of data destruction by controlling the phase of the use timing signal.