JPH03126114A - No-hit switching control circuit - Google Patents

Abstract

PURPOSE:To switch systems 1 and 0 without a hit even in the case of the phase deviation between both system clocks by using an AND circuit to use a select signal where the phase deviation between both system clocks is taken into consideration. CONSTITUTION:A second select signal 106 obtained at the retiming of a first select signal 105 for switching between systems 0 and 1 is generated by a control clock 103 resulting from AND or OR between a system 0 clock 101 and a system 1 clock 102. The first or second select signal 105 or 106 is used as a third select signal 107 for switching between both systems in accordance with break information of both system clocks from a clock break detecting circuit 2. That is, when break information of both system clocks is inputted to a selecting circuit 5, the circuit 5 selects the second select signal 106 to output it as the third select signal 107 in the case of the presence of phase deviation between both system clocks 101 and 102 but selects the first select signal 105 to output it as the signal 107 in the case of the absence of the phase deviation. Thus, both systems are switched without a hit through the phase deviation occurs between both system clocks 101 and 102.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is used in a switching circuit for a digital circuit having a redundant configuration of a 0 system and a 1 system, and particularly relates to a non-interruption switching control circuit thereof.

〔overview〕

The present invention provides a switching control circuit for a digital circuit that has a redundant configuration of a 0 system and a 1 system. A second selection signal is generated at the same timing as the first selection signal for switching between the two systems, and the first selection signal or the second selection signal is generated in accordance with the clock interruption information from the clock interruption detection circuit for both systems. By using one of them as the third selection signal for switching between the two systems, a non-interruption switching control circuit is realized.

[Conventional technology]

Conventionally, in digital circuits with this type of redundant configuration, when it is desired to switch between the 0 system and 1 system, a selection signal A (10 in Fig. 1) is used to select either the 0 system clock or the 1 system clock.
5), it was directly switched.

[Problem that the invention seeks to solve]

In the digital circuit with the conventional redundant configuration described above, if you try to switch between the 0 system and 1 system directly using the selection signal A, there will be a slight phase shift between the 0 system clock and the 1 system clock. This has the disadvantage that momentary interruptions may occur depending on the timing of switching.

An object of the present invention is to provide a no-interruption switching control circuit that eliminates instantaneous interruptions during switching by eliminating the above-mentioned drawbacks.

[Failure to solve the problem]

The present invention provides a redundant configuration of the θ thread circuit and the 0 line of the 1 system circuit.
A clock disconnection detection circuit that outputs both system clock disconnection information based on the system clock and the 1 system clock, and a control circuit that outputs a first selection signal that selects the 0 system clock or the 1 system clock. In the switching control circuit, an arithmetic circuit that performs a logical sum or AND of the 0-system clock and the 1-system clock and outputs a control clock; and a second selection circuit that retimes the first selection signal using the control clock. The present invention is characterized by comprising a flip-flop that outputs a signal, and a selection circuit that selects the first selection signal and the second selection signal based on the both-system clock disconnection information and outputs a third selection signal. shall be.

[Effect]

For example, when the circuit is operating with positive logic, the arithmetic circuit uses an AND circuit to AND the O-system clock and the 1-system clock (in the case of negative logic, takes the OR),
When both system clocks are at the "1" level, a control clock that goes to the "1" level is output. In other words, this control clock takes into account the phase shift between the clocks of both systems.

Then, the flip-flop outputs a second selection signal obtained by retiming the first selection signal using this control clock. The selection circuit selects the second selection signal when there is a phase difference between the clocks of both systems and the first selection signal when there is no phase difference between the clocks of both systems. Output as the third selection signal.

Therefore, even if a phase shift occurs between the clocks of both systems, it is possible to switch between both systems without momentary interruption.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.
This figure shows the basic configuration of the present invention.

The second embodiment includes a clock disconnection detection circuit 2 that outputs both system clock disconnection information 104 based on the 0 system clock 101 and 1 system clock 102 of the 0 system circuit and 1 system circuit that have a redundant configuration, and the O system clock and a control circuit 3 that outputs a selection signal AlO3 as a first selection signal for selecting between the 0-system clock 101 and the 1-system clock, which is a feature of the present invention.
A calculation circuit (
In this embodiment, an AND circuit) 1 and a flip-flop 4 outputting a selection signal B106 as a second selection signal obtained by retiming the selection signal A15 using a clock B103.
, the selection signal A is input by inputting the clock disconnection information 104 for both systems.
It includes a selection circuit A5 that selects either lO3 or selection signal B106 and outputs selection signal C107 as a third selection signal.

FIG. 2 is a block diagram showing a second embodiment of the present invention.
1 shows a main part of a non-interruption switching circuit to which the present invention is applied.

In FIG. 2, the portion surrounded by a broken line is the non-interruption switching control circuit of FIG. In addition, the second embodiment includes a clock generation circuit 6.0 system circuit 7.1 system circuit 8, a selection circuit B9, a selection circuit CIO, and a common circuit 11 as both system circuits and their switching selection circuits. I'm here.

Next, the operation of the embodiment of the present invention will be explained using FIG.

The 0-system circuit 7 operates with the clock AlO3 output from the clock generation circuit 6, and outputs a 0-system signal 109 and a 0-system clock 101. Similarly, the 1-system circuit 8 is
It operates with the clock AlO3 output from the clock generation circuit 6, and outputs the 1-system signal 110 and the 1-system clock 102. Then, the selection circuit B9 and the selection circuit C10 select either the 0 system signal 109 or the 1 system signal 110, and the 0 system clock 101 or the 1 system clock 102, respectively, and output the signal 111 and the clock C112. Common circuit 1
1 operates based on this signal 111 and clock C112 to output a final output signal 113.

Here, when it is desired to switch between the 0 system and the 1 system, the control circuit 3 outputs a selection signal AlO3. At this time, the arithmetic circuit 1 outputs a clock B103 obtained by logically multiplying or ORing the 0-system clock 101 and the 1-system clock 102. In this embodiment, the logical product is used. ), the selection signal AlO is output by the clock B103 in the flip-flop 4.
3 and outputs the selection signal B106. Then, the selection circuit A5 selects the selection signal AlO3 and the selection signal B.
106 is selected by inputting the both-system clock disconnection information 104 of the 0-system clock 101 and the 1-system clock 102, and a selection signal C107 is output.This selection signal C107 causes the selection circuit B9 and the selection circuit C
Switch 10.

FIG. 3 is a timing chart showing an example of the operation shown in FIG. 2, and shows a case where the 1-system clock 102 shows a phase lag with respect to the 0-system clock 101.

At this time, the selection signal AlO3 from the control circuit 3 is rising in synchronization with the 0-system clock 101.

On the other hand, the arithmetic circuit (AND circuit in this case) 1 performs the logical product of the 0 system clock 101 and the 1 system clock 102 and outputs a clock B 103 in which the area where both clocks are at the "1" level is set to the "1" level. . As a result, the flip-flop 4 retimes the selection signal AlO3 and clock B.
A selection signal B106 rising in synchronization with signal B103 is output.

The selection circuit A5 selects the selection signal B106 and outputs it as the selection signal C107 when the dual-system clock disconnection information 104 is input. As a result, in this case, the conventional selection signal AlO
3, the instantaneous interruption that occurred due to switching did not occur,
Uninterrupted switching can be achieved.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to switch between the 0 system and the 1 system without momentary interruption even if there is a phase shift between the clocks of both systems, and the effect is great. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 2 is a block diagram showing a second embodiment of the present invention. FIG. 3 is a timing chart showing the operation of the second embodiment of the present invention. 1... Arithmetic circuit, 2... Clock disconnection detection circuit, 3.
... Control circuit, 4... Flip-flop, 5... Selection circuit A, 6... Clock generation circuit, 7... 0 system circuit, 8-1 system circuit, 9... Selection circuit B, 10...Selection circuit C111...Common circuit, 101...0 system clock, 102...1 system clock, 103...Clock B, 104...Both system clock link disconnection information, 105...・
・Selection signal A, 106...Selection signal B1107...
Selection signal C1108...Clock A, 109...0
System signal, 110...1 system signal, 111...signal, 1
12... Clock C1113... Output signal.

Claims (1)

[Scope of Claims] 1. A clock disconnection detection circuit that outputs both system clock disconnection information based on the 0 system clock and 1 system clock of the 0 system circuit and 1 system circuit that have a redundant configuration; A switching control circuit comprising a control circuit that outputs a first selection signal for selecting a system clock, the operation of performing a logical OR or AND of the 0 system clock and the 1 system clock and outputting a control clock. a flip-flop that outputs a second selection signal obtained by retiming the first selection signal using the control clock; and a flip-flop that outputs a second selection signal obtained by retiming the first selection signal using the control clock; and a selection circuit that selects and outputs a third selection signal.