JPH0322445A - 混成集積回路 - Google Patents

混成集積回路

Info

Publication number
JPH0322445A
JPH0322445A JP1157637A JP15763789A JPH0322445A JP H0322445 A JPH0322445 A JP H0322445A JP 1157637 A JP1157637 A JP 1157637A JP 15763789 A JP15763789 A JP 15763789A JP H0322445 A JPH0322445 A JP H0322445A
Authority
JP
Japan
Prior art keywords
pads
semiconductor chip
wiring board
pad
gold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1157637A
Other languages
English (en)
Inventor
Yoshihiko Sato
佐藤　恵彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1157637A priority Critical patent/JPH0322445A/ja
Publication of JPH0322445A publication Critical patent/JPH0322445A/ja
Pending legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路に関する。
〔従来の技術〕
第３図は従来の混或集積回路の一例の断面図である。
プリント板．厚膜印刷基板，薄膜多層基板等の配線板１
上に半導体チップ２を搭載し、金線３により半導体チッ
プ２の電極と配線板１のボンディングパッドとを接続し
、しかる後に半導体チップ搭載部をシリコーン樹脂，エ
ボキシ樹脂，フェノール樹脂等の樹脂４で被覆する。
しかしながら、集積度が大きくなると、ボンディングパ
ッドや電極を一列に配置することが難しくなってくる。
そこで、二列配置が行われるようになった。
第４図（ａ），（ｂ）は従来の混戒集積回路の他の例の
部分平面図及び側面図である。
半導体チップ２のボンディング用パッド２１ａ，２ｌｂ
及び配線板１のホンディング用パッド１１ａ，ｌｌｂを
それぞれ二列に配置し、金線３ａ，３ｂでそれぞれ接続
する。このとき、金線３ａと３ｂとは側面から見たとき
に上下関係にあるようにボンディングするのが普通であ
る。
〔発明が解決しようとする課題〕
上述のように、集積数が大きくなり、配線板１上のパッ
ドｌｌａ，ｌｌｂの配置密度が高くなると、金線３ａと
３ｂとが上下あるいは左右に蛇行して両金線が電気的に
接触するという不良を生じたり、あるいはパッドの微細
配置ができなくなるという欠点が出てくる。
〔課題を解決するための手段〕
本発明は、半導体チップ搭載部と該半導体チップ搭載部
の周囲に該半導体チップ搭載部に近い方のボンディング
用第１パッドと遠い方のボンディング用第２パッドとが
交互に配置され前記パッドの各々に配線が接続している
配線板と、前記半導体チップ搭載部に固着され、前記二
種のパッドに対応してボンディング用パッドが形成され
ている半導体チップとを有する混成集積回路において、
前記第１パッドと第２パッドとの間を通って前記半導体
チップを囲むように絶縁物製の枠を設け、前記枠の表面
でかつ前記第２パッドに対応する位置に金属層を設け、
前記第２パッドと金属層との間及び前記半導体チップの
パッドと金属層との間をそれぞれ金属線で接続したこと
を特徴とする。
〔実施例〕
次に、本発明の実施例について図面を参照して説明する
。
第１図は本発明の一実施例の平面図、第２図（ａ），（
ｂ）は第１図に示す実施例の部分拡大平面図及び側面図
である。
この実施例においては、配線板のパッドｌｌａとｌｌｂ
との間を通るセラミック枠、５を配線７の上から配線板
１に固着する。セラミック枠５は、例えば高さを０．３
ｍｍ、幅１ｍｍの寸法にする。セラミック枠５の表面で
パッドｌｌｂに対応した位置に金属層６を設ける。そし
て、金線３ｂで半導体チップ２のパッド２ｌｂと金属層
６との間を接続し、金線３ｃで配線板１のパッド１１ｂ
と金属層６との間を接続する。これ以外は従来例と同じ
である。
このように、パッド２ｌｂとパッド１ｌｂとの間のよう
に金線が長くなる所では、途中に中継点をおいてやると
、金線３ｂの長さを短くでき、金線の上下または左右蛇
行を少なくでき、電気的に接触するという不良を低減す
ることができる。
上記実施例では、セラミック枠を矩形としたが、矩形に
限定されず、環状としても良い。また、セラミックの代
りにプラスチックあるいはガラス等の絶縁物を用いても
良い。
〔発明の効果〕
以上説明したように、本発明は、半導体チップを囲む形
状に絶縁物の枠を配置し、その枠の内側と外側とに配線
板のボンディング用パッドを配置して半導体チップのパ
ッドと配線板上のパッドとを接続する短かい金線と長い
金線との高度差を十分にとることができ、また長い金線
を二つに分けて各々が短くなるようにしたので、金線の
上下左右に蛇行するのを低減し、両金線が電気的に接触
する確率は小さくし、混戒集積回路の製造歩留りや信頼
度は向上するという効果がある。
【図面の簡単な説明】
第１図は本発明の一実施例の平面図、第２図（ａ）．（
ｂ）は第１図に示す実施例の部分拡大平面図、第３図は
従来の混或集積回路の一例の断面図、第４図（ａ），（
ｂ）は従来の混戒集積回路の他の例の平面図及び側面図
である。 １・・・配線板、２・・・半導体チップ、３．３ａ，３
ｂ，３ｃ・・・金線、４・・・樹脂、５・・・セラミッ
ク枠、６・・・金属層、７・・・配線、ｌｌａ，ｌｌｂ
・・・パッド、２１ａ，２１ｂ・・・パッド。

Claims (1)

    【特許請求の範囲】
  1. 半導体チップ搭載部と該半導体チップ搭載部の周囲に該
    半導体チップ搭載部に近い方のボンディング用第１パッ
    ドと遠い方のボンディング用第２パッドとが交互に配置
    され前記パッドの各々に配線が接続している配線板と、
    前記半導体チップ搭載部に固着され、前記二種のパッド
    に対応してボンディング用パッドが形成されている半導
    体チップとを有する混成集積回路において、前記第１パ
    ッドと第２パッドとの間を通って前記半導体チップを囲
    むように絶縁物製の枠を設け、前記枠の表面でかつ前記
    第２パッドに対応する位置に金属層を設け、前記第２パ
    ッドと金属層との間及び前記半導体チップのパッドと金
    属層との間をそれぞれ金属線で接続したことを特徴とす
    る混成集積回路。
JP1157637A 1989-06-19 1989-06-19 混成集積回路 Pending JPH0322445A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1157637A JPH0322445A (ja) 1989-06-19 1989-06-19 混成集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1157637A JPH0322445A (ja) 1989-06-19 1989-06-19 混成集積回路

Publications (1)

Publication Number Publication Date
JPH0322445A true JPH0322445A (ja) 1991-01-30

Family

ID=15654077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1157637A Pending JPH0322445A (ja) 1989-06-19 1989-06-19 混成集積回路

Country Status (1)

Country Link
JP (1) JPH0322445A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0513591A2 (en) * 1991-05-09 1992-11-19 International Business Machines Corporation Lead Frame-chip package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0513591A2 (en) * 1991-05-09 1992-11-19 International Business Machines Corporation Lead Frame-chip package

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