JPH02281647A - 集積回路 - Google Patents

集積回路

Info

Publication number
JPH02281647A
JPH02281647A JP1102410A JP10241089A JPH02281647A JP H02281647 A JPH02281647 A JP H02281647A JP 1102410 A JP1102410 A JP 1102410A JP 10241089 A JP10241089 A JP 10241089A JP H02281647 A JPH02281647 A JP H02281647A
Authority
JP
Japan
Prior art keywords
semiconductor chip
island
pads
leads
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1102410A
Other languages
English (en)
Inventor
Yoshihiko Sato
佐藤　惠彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1102410A priority Critical patent/JPH02281647A/ja
Publication of JPH02281647A publication Critical patent/JPH02281647A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は集積回路に関する。
〔従来の技術〕
第３図（ａ）、（ｂ）の従来の集積回路の一例の平面図
及びＡ−Ａ’線断面図である。
リードフレームのアイランド３に半導体チップ７を固着
し、リードフレームのり−ド１と半導体チップ７のパッ
ドとを金線９で接続し、樹脂１゜で接続する。
第４図（ａ）、（ｂ）は第３図（ａ）、（ｂ）に示す集
積回路の内部の部分平面図及び側面図である。
リードフレームのり−ド１の先端のパッド２ａ２ｂは１
列に配置され、半導体チップ７のパッド８ａ、８ｂもこ
れに対して１列に配置され、金線９ａ、９ｂでそれぞれ
接続される。
〔発明が解決しようとする課題〕
上述した従来の半導体集積回路は、半導体集積回路が大
規模になって半導体チップ上の電極数が例えば１００〜
２５０本程度に多くなった場合には、その製造の歩留り
や製品の信頼度が低下するという欠点があり、またリー
ドフレームを微細に加工することができなくなるために
、半導体集積回路自体の製造ができなくなるという欠点
がある。即ち、第４図（ａ）、（ｂ）に示したように、
リード１の先端のパッド２の配置密度が高くなると、金
線９ａ、９ｂが上下または左右に蛇行して両者の線が接
触して短絡するという不良を生じる。またリードフレー
ムの製造も難しくなるという欠点がる。
〔課題を解決するための手段〕
本発明の集積回路は、アイランドに半導体チップが固着
され、前記アイランドの周囲に間隔をおいてリードが配
置され、前記リードの先端のボンディング用バッドが一
つおきに前記アイランドに対して遠近となるように配置
され、前記半導体チップのボンディング用パッドと前記
リードのボンディング用パッドとが金属線で接続され、
封止されて成る集積回路において、前記アイランドに近
いボンディング用パッドと遠いボンディングパッドとの
間を通って前記アイランドの周囲を囲む絶縁体の枠を前
記リード上に固着し、前記枠の表面に前記アイランドか
ら遠いボンディング用パッドに対応してボンディング用
金属層を設け、前記アイランドから遠いボンディング用
パッドと前記金属層と前記半導体チップのボンディング
用パッドとを金属線で接続し前記アイランドに近いボン
ディング用パッドと前記半導体チップのボンディングパ
ッドとを直接に接続したことを特徴とする。
〔実施例〕
第１図は本発明の一実施例の部分平面図、第２図（ａ）
、（ｂ）は第１図に示す実施例の部分拡大図及び側面図
である。
半導体チップ７を載置するアイランド３の四辺にリード
１を配置するが、その時リードの先端のパッ、ド２ａ、
２ｂは互いに千鳥足状に配置し、しかもパッド２ａと２
ｂの間隔を少し広くする。そして、パッド２ａと２ｂと
の間の通ってアイランド３を囲むようにセラミック枠５
をリード１の上に固着する。セラミック枠５の表面には
金線９ａ、９ｂ、９ｃがボンディング出来るように金属
層６を形成しておく、金属層６の相貫としては金が適当
である。
アイランド６に半導体チップ７を固着し、半導体チップ
７のパッド８ａとリード１のパッド２ａとの間の距離は
短いので直接に金線９ａで接続する。半導体チップ８ｂ
にボンディングした金線９ｂはセラミック枠５の金属層
６にボンディング接続する。金属層６とリード１のパッ
ド２ｂとは金線９ｃで接続する。
このように、セラミック枠５を設け、高度差を設けるこ
とによって金線９ａと９ｂとの上下方向の間隔を広くす
ることができるので、短絡を防ぐことができる。
上記実施例では、セラミック枠を用いたが、ガラスまた
はプラスチック等の絶縁体で表面にボンディング用の金
属層を形成できるものであれば、どれを用いても良いこ
とは明らかである。
〔発明の効果〕
以上説明したように本発明は、半導体チップを囲む形状
に絶縁物の枠を配置し、その枠の内側と外側とにリード
先端のパッドとをを配置し、半導体チップのパッドとリ
ードとを接続する短かい金線と長い金線との高度差を充
分にとることができるようにしたので、両金線が電気的
に接触する確率が小さくなり、製造される半導体集積回
路の製造歩留や信頼度を向上させることができるという
効果を有する。
【図面の簡単な説明】
第１図は本発明の一実施例の平面図、第２図（ａ）、（
ｂ）は第１図に示す実施例の部分拡大図及び側面図、第
３図（ａ＞、（ｂ）は従来の半導体集積回路の平面図及
びＡ−Ａ’断面図、第４図（ａ）、（ｂ）は第３図（ａ
）に示す半導体集積回路の内部の部分平面図及び側面図
である。 １・・・リード、２ａ、２ｂ・・・パッド、３・・・ア
イランド、４・・・金めつき層、５・・・セラミック枠
、６・・・金属層、７・・・半導体チップ、８ａ、８ｂ
・・・パッド、９ａ、９ｂ、９ｃ・・・金線、１０・・
・樹脂。

Claims (1)

    【特許請求の範囲】
  1. アイランドに半導体チップが固着され、前記アイランド
    の周囲に間隔をおいてリードが配置され、前記リードの
    先端のボンディング用パッドが一つおきに前記アイラン
    ドに対して遠近となるように配置され、前記半導体チッ
    プのボンディング用パッドと前記リードのボンディング
    用パッドとが金属線で接続され、封止されて成る集積回
    路において、前記アイランドに近いボンディング用パッ
    ドと遠いボンディングパッドとの間を通って前記アイラ
    ンドの周囲を囲む絶縁体の枠を前記リード上に固着し、
    前記枠の表面に前記アイランドから遠いボンディング用
    パッドに対応してボンディング用金属層を設け、前記ア
    イランドから遠いボンディング用パッドと前記金属層と
    前記半導体チップのボンディング用パッドとを金属線で
    接続し前記アイランドに近いボンディング用パッドと前
    記半導体チップのボンディングパッドとを直接に接続し
    たことを特徴とする集積回路。
JP1102410A 1989-04-21 1989-04-21 集積回路 Pending JPH02281647A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1102410A JPH02281647A (ja) 1989-04-21 1989-04-21 集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1102410A JPH02281647A (ja) 1989-04-21 1989-04-21 集積回路

Publications (1)

Publication Number Publication Date
JPH02281647A true JPH02281647A (ja) 1990-11-19

Family

ID=14326672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1102410A Pending JPH02281647A (ja) 1989-04-21 1989-04-21 集積回路

Country Status (1)

Country Link
JP (1) JPH02281647A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0513591A2 (en) * 1991-05-09 1992-11-19 International Business Machines Corporation Lead Frame-chip package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0513591A2 (en) * 1991-05-09 1992-11-19 International Business Machines Corporation Lead Frame-chip package

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