JPH03224268A - Formation of schottky electrode - Google Patents
Formation of schottky electrodeInfo
- Publication number
- JPH03224268A JPH03224268A JP1991990A JP1991990A JPH03224268A JP H03224268 A JPH03224268 A JP H03224268A JP 1991990 A JP1991990 A JP 1991990A JP 1991990 A JP1991990 A JP 1991990A JP H03224268 A JPH03224268 A JP H03224268A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wsi
- schottky electrode
- forming
- wsin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 11
- 229910008807 WSiN Inorganic materials 0.000 claims abstract description 10
- 239000013078 crystal Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 abstract description 12
- 238000004544 sputter deposition Methods 0.000 abstract description 7
- 229910045601 alloy Inorganic materials 0.000 abstract description 4
- 239000000956 alloy Substances 0.000 abstract description 4
- 238000010030 laminating Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、ＧａＡｓ半導体結晶（基板、薄膜、厚膜等
を含む。）上に形成されるショットキ電極の形成方法に
関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for forming a Schottky electrode formed on a GaAs semiconductor crystal (including a substrate, a thin film, a thick film, etc.).
ＧａＡｓ半導体結晶上に形成されるＭＥＳＦＥＴ用ゲー
トとして、ＷＳｉを用いるショットキ電極構造の形成方
法が提案されている。ＷＳｉを用いる電極はＴｉＷより
加工性が良く反応性イオンエツチングにより矩形に近い
断面が得られる点でメリットがあるが、シート抵抗が大
きいので抵抗を低減する必要がある。その為、例えばＡ
ｕを上層に形成する方法が提案されている。ところが、
ＷＳｉとＡｕは熱処理の際に相互に拡散し、特性が劣化
することから、ＷＳｉとＡｕとの間に拡散バリアとして
ＴｉＮを介在する技術（特開昭５９−１８１６７６）が
提案されている（第３図）。A method of forming a Schottky electrode structure using WSi has been proposed as a MESFET gate formed on a GaAs semiconductor crystal. Electrodes using WSi have advantages over TiW in that they have better processability and can obtain a nearly rectangular cross section through reactive ion etching, but have a high sheet resistance, so it is necessary to reduce the resistance. Therefore, for example, A
A method of forming u in an upper layer has been proposed. However,
Since WSi and Au diffuse into each other during heat treatment and their properties deteriorate, a technique (Japanese Patent Laid-Open No. 181676/1983) has been proposed in which TiN is interposed as a diffusion barrier between WSi and Au. Figure 3).
しかし、ＴｉＮを用いると、ＷＳＬの他にＴｉのターゲ
ットが必要になり、作業性が悪いという欠点があった。However, when TiN is used, a Ti target is required in addition to the WSL, which has the drawback of poor workability.
また、製造工程の中断により膜間に剥離が発生し、形成
されたショットキ電極の信頼性、機械的強度が劣化する
という欠点があった。Further, there was a drawback that separation occurred between the films due to interruption of the manufacturing process, and the reliability and mechanical strength of the formed Schottky electrode deteriorated.
そこで本発明は、作業性が良く、信頼性及び機械的強度
の高いショットキ電極を作成できる形成方法を提供する
ことを目的とする。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method of forming a Schottky electrode with good workability, reliability, and mechanical strength.
上記課題を達成するため、この発明はＧａＡｓ半導体結
晶上にＷＳｉ層を形成する第１工程と、このＷＳｉ層上
にＷＳｉＮ層を形成する第２の工程と、このＷＳｉＮ層
上にＡｕ層を形成する第３の工程と含んで構成されるこ
とを特徴とする。In order to achieve the above object, the present invention includes a first step of forming a WSi layer on a GaAs semiconductor crystal, a second step of forming a WSiN layer on this WSi layer, and a second step of forming an Au layer on this WSiN layer. The method is characterized in that it includes a third step of doing so.
この発明は、以上のように構成されているので、同一タ
ーゲットを使用してショットキ電極が形成される。その
為、製造工程が少なく製造時間が短くなる。Since the present invention is configured as described above, Schottky electrodes are formed using the same target. Therefore, the number of manufacturing steps is small and the manufacturing time is shortened.
以下、この発明の一実施例に係るショットキ電極の形成
方法を添付図面に基づき説明する。なお、説明において
同一要素には同一符号を用い、重複する説明は省略する
。Hereinafter, a method for forming a Schottky electrode according to an embodiment of the present invention will be described with reference to the accompanying drawings. In the description, the same elements are denoted by the same reference numerals, and redundant description will be omitted.
第１図は、一実施例に係る形成方法によりＧａＡｓ基板
上に作成されたショットキ電極の構造を示す縦断面図で
ある。この形成方法は、基本的には３工程を含んで構成
されていぞ。第１の工程では、例えばスパッタ装置内を
Ａ「ガスで満たし、その中にＧａＡｓ基板１を設置し、
ＷＳｉ合金ターゲットをスパッタすることによりＧａＡ
ｓ基板１上にＷＳｉ層２を形成する。第２の工程では、
上記スパッタ装置内にＡｒガスの他にＮ２ガスを導入し
、連続してＷＳｉ合金ターゲットをスパッタする。この
工程により、Ｗ Ｓ ｉ Ｎ層３がＷＳｉＳｉ上２上成
される。第３の工程では、Ａｒガスをスパッタ装置内に
満たし、Ａｕターゲットをスパッタすることにより、Ｗ
ＳｉＮ層３上層Ａｕ層４が形成される。FIG. 1 is a longitudinal cross-sectional view showing the structure of a Schottky electrode formed on a GaAs substrate by a forming method according to an embodiment. This forming method basically includes three steps. In the first step, for example, the inside of the sputtering apparatus is filled with gas A, and the GaAs substrate 1 is placed therein.
GaA by sputtering WSi alloy target
A WSi layer 2 is formed on an s-substrate 1. In the second step,
In addition to Ar gas, N2 gas is introduced into the sputtering apparatus to continuously sputter a WSi alloy target. Through this step, the WSiN layer 3 is formed on the WSiSi. In the third step, by filling the sputtering device with Ar gas and sputtering the Au target, W
An Au layer 4 is formed on the SiN layer 3.
この実施例によると、スパッタを一時中断することなく
、連続的にＷＳｉ層２及びＷＳｉＮ層３を形成すること
ができるので、作業性が向上する。According to this embodiment, the WSi layer 2 and the WSiN layer 3 can be formed continuously without temporarily interrupting sputtering, so that workability is improved.
次に、この発明に係る実験結果を説明する。この実験で
は、ＧａＡｓ基板上にＷＳｉを２０００オングストロー
ム形成し、続けて、Ｗ Ｓ ｉ Ｎを１０００オングス
トローム形成し、さらに、Ａｕを２０００オングストロ
ーム形成し、最後に、この基板に８００℃で２０分間の
加熱処理を施した。Next, experimental results related to this invention will be explained. In this experiment, 2000 angstroms of WSi was formed on a GaAs substrate, followed by 1000 angstroms of WSiN, then 2000 angstroms of Au, and finally, the substrate was heated at 800°C for 20 minutes. Processed.
Ａｕを上層に形成することにより、シート抵抗は約３０
分の１に低減された。By forming Au on the upper layer, the sheet resistance is approximately 30
It was reduced to one-fold.
第２図は、このショットキ電極のＡＥＳｓＲさプロファ
イルを示すものである。このＡＥＳ深さプロファイルで
示されているように、Ａｕの内部拡散は見られないこと
が確認された。FIG. 2 shows the AESsR profile of this Schottky electrode. As shown in this AES depth profile, it was confirmed that no internal diffusion of Au was observed.
なお、この発明は上記実施例に限定されるものではない
。例えば、この実施例ではＧａＡｓ基板上に多層膜を形
成し、さらに、この多層膜に加熱処理を施してい”るが
、多層膜を形成する下地は基板でなくてもよく、また、
加熱処理しなくても十分に効果的である。下地部材とし
ては、基板上に形成された薄膜、厚膜でもよい。Note that this invention is not limited to the above embodiments. For example, in this example, a multilayer film is formed on a GaAs substrate, and this multilayer film is further subjected to heat treatment, but the base on which the multilayer film is formed does not have to be the substrate,
It is sufficiently effective even without heat treatment. The base member may be a thin film or a thick film formed on the substrate.
〔発明の効果コ
この発明は、以上説明したように構成されているので、
同一ターゲットを使用してショットキ電極が形成される
ので、製造工程が少なく、製造時間が短くなる。その為
、作業性が向上する。[Effects of the Invention] Since this invention is configured as explained above,
Since the Schottky electrodes are formed using the same target, there are fewer manufacturing steps and manufacturing time is shortened. Therefore, work efficiency is improved.
第１図は本発明に係る形成方法により作成されたショッ
トキ電極の構造を示す縦断面図、第２図は本発明に係る
形成方法により作成されたショットキ電極のＡＥＳ深さ
プロファイルを示す図、第３図は従来技術に係る形成方
法により作成されたショットキ電極の構造を示す縦断面
図である。
１ ＝・Ｇ ａ Ａ ｓ基板、２−ＷＳｉ層、３−ＷＳ
ｉＮ層、４・・・Ａｕ層。FIG. 1 is a longitudinal cross-sectional view showing the structure of a Schottky electrode created by the forming method according to the present invention, FIG. 2 is a diagram showing the AES depth profile of the Schottky electrode created by the forming method according to the present invention, FIG. 3 is a longitudinal cross-sectional view showing the structure of a Schottky electrode formed by a forming method according to the prior art. 1 =・GaAs substrate, 2-WSi layer, 3-WS
iN layer, 4...Au layer.
Claims (1)
、 このＷＳｉ層上にＷＳｉＮ層を形成する第２の工程と、 このＷＳｉＮ層上にＡｕ層を形成する第３の工程と含ん
で構成されることを特徴とするショットキ電極の形成方
法。[Claims] A first step of forming a WSi layer on a GaAs semiconductor crystal, a second step of forming a WSiN layer on this WSi layer, and a third step of forming an Au layer on this WSiN layer. 1. A method for forming a Schottky electrode, comprising a step of forming a Schottky electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1991990A JPH03224268A (en) | 1990-01-30 | 1990-01-30 | Formation of schottky electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1991990A JPH03224268A (en) | 1990-01-30 | 1990-01-30 | Formation of schottky electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03224268A true JPH03224268A (en) | 1991-10-03 |
Family
ID=12012629
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1991990A Pending JPH03224268A (en) | 1990-01-30 | 1990-01-30 | Formation of schottky electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03224268A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07161659A (en) * | 1993-12-07 | 1995-06-23 | Nec Corp | Semiconductor device and its manufacture |
-
1990
- 1990-01-30 JP JP1991990A patent/JPH03224268A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07161659A (en) * | 1993-12-07 | 1995-06-23 | Nec Corp | Semiconductor device and its manufacture |
| US5567647A (en) * | 1993-12-07 | 1996-10-22 | Nec Corporation | Method for fabricating a gate electrode structure of compound semiconductor device |
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