JPH03218662A - Manufacture of cmos semiconductor device - Google Patents

Abstract

PURPOSE:To increase a parasitic MOSFET in reverse voltage by a method wherein an oxidation-resistant film is selectively formed on an element region, and boron ions are implanted into all the surface of the isolating regions of a p well and an n well before the isolating region is selectively oxidized. CONSTITUTION:An n well 2 and a p well 3 are formed on a p-type semiconductor substrate 1 of low concentration, then a pad oxide film 4 and a silicon nitride 5 are formed on the whole face of a wafer, an element region is masked with a resist pattern 6, and the silicon nitride film 5 on a region other than the element region or on a field region is selectively removed. Then, boron ions 7 are implanted into the whose face of the field region using the resist pattern 6 as a mask. By this setup, a parasitic MOSFET can be enhanced enough in reverse voltage.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a CMOS semiconductor device.

[Conventional technology]

Generally, in a CMOS semiconductor device in which elements are isolated by the LOCOS method in both well structures, it is necessary to make the inversion voltage of a parasitic MOSFET using a field oxide film as a gate insulating film sufficiently high.

To deal with this, it is possible to increase the surface concentration of the well in the field region, but since the well concentration is optimized based on the source/drain junction capacitance and punch-through resistance, Generally, ion implantation is performed to increase the surface concentration.

An example of a conventional method of manufacturing a CMOS semiconductor device in which the surface concentration is selectively increased will be described with reference to FIGS. 8-8(0). First, as shown in FIG.
After forming an n-well 1o2 and a p-well 1o3 in 01, a pad oxide film 104 and a silicon nitride film 105 serving as an oxidation-resistant mask are formed on the entire surface, and then the element area is masked with a resist pattern 106 to mask the area other than the element area. That is, the silicon nitride film 105 in the field region is selectively removed. Next, as shown in FIG. 3 (■), the resist pattern 106 is removed to form a resist pattern 107 in the p-well 103SI region, and using this and the silicon nitride film 105 as a mask, the resist pattern 107 is selectively applied to the field region of the n-well 102. Ion implantation of phosphorus 108 is performed.

Next, as shown in FIG. 3(C), a resist pattern 10
A resist pattern 109 is formed in the n-well 102tii region, and boron 110 is selectively ion-implanted into the field elm of the p-well 103 using this resist pattern 109 and the silicon nitride film 105 as a mask. Next, as shown in FIG. 3(0), the field oxide film 1 is heat-treated in an oxidizing atmosphere.
11 is formed. Next, the silicon nitride film 105 is removed, and a CMOS semiconductor device is completed by a known method.

According to this manufacturing method, the surface concentration of the p-well and n-well can be increased only in the field region.
The inversion voltage of the parasitic MOSFET can be increased.

[Problem to be solved by the invention]

According to the conventional manufacturing method described above, it is possible to increase the inversion voltage of the parasitic MOSFET in a CMOS semiconductor device, but in the conventional manufacturing method, two additional photo steps are required for this purpose, which increases the number of man-hours. The problem was that it was increasing. Generally, for n-wells, if the thickness of the field oxide film and the concentration of the well are set relatively large, it is possible to omit ion implantation into the field region.
Regarding the p-well, since the segregation coefficient of boron, which is an impurity, in the oxide film is large, the surface concentration tends to decrease by the field oxidation process, and ion implantation into the field nodule region cannot be omitted. Therefore, parasitic MO
In order to increase the inversion voltage of SFET, at least 1
It required multiple photo processes.

The present invention has been made in order to solve the above-mentioned problems in the conventional manufacturing method of CMOS semiconductor devices. The purpose is to provide a method for manufacturing semiconductor devices. [Means and effects for solving the problem] In order to solve the above problems, the present invention provides a P-channel MOS on a semiconductor substrate.
It has an n-well that forms an FET and a p-well that forms an n-channel MOSFET, and an oxidation-resistant film is selectively formed in the element regions of the in-well and p-well, and the isolation region is selectively oxidized to form a field oxide film. In a method for manufacturing a CMOS semiconductor device in which an oxidation-resistant film is selectively formed in the element region, and before selective oxidation of the isolation region is performed, the entire surface of the isolation region of both the p-well and the n-well is coated. On the other hand, boron ions are implanted.

By implanting poron ions into the entire surface of the isolation region as shown in step 2, by setting appropriate ion implantation conditions and oxidation conditions for the M region for the n-well, impurities in the n-well during oxidation of the isolation region can be removed. The pile-up of the injected poron compensates for the injected poron and makes it possible to make the inversion voltage of the parasitic MOSFET sufficiently high.

〔Example〕

Next, an example will be described. 8 to [C] are manufacturing process diagrams for explaining one embodiment of the method for manufacturing a CMOS semiconductor device according to the present invention. First, as shown in FIG. 1, a p-type semiconductor substrate 1 with a surface concentration of 2
n-well 2 with phosphorus as an impurity in XIO”/cd,
A p-well 3 containing boron as an impurity with a surface concentration of IXIO''/cj is formed, and then a pad oxide film 4 with a thickness of 500 mm and a silicon nitride film 5 serving as an oxidation-resistant mask of 1000 mm are formed over the entire surface of the wafer. Then, the device edge region is masked with a resist pattern 6, and the silicon nitride film 5 in the region other than the device region, that is, the field region, is selectively removed.

Next, as shown in Figure 1), using the resist pattern 6 as a mask, boron 7 is ion-implanted into the entire field region at an acceleration voltage of 80 KeV. At this time, ions can be implanted using the silicon nitride film 5 as a mask after removing the resist pattern 6, but in this case, the implantation is performed at a relatively low acceleration voltage to prevent the implanted boron from entering the element region. There must be. If the implanted boron distribution is shallow, more boron will be incorporated into the oxide film by segregation during field oxidation, so it is desirable to implant boron ions to a slightly deeper depth using a thick resist pattern as a mask. Next, as shown in FIG. 1(C), the field region is selectively oxidized in a water vapor atmosphere at 900° C. to form a field oxide film with a thickness of 6,000 μm.
form. At this time, the surface of the n-well 2 has been made p-type by ion implantation of boron 7, which is a p-type impurity, before field oxidation, but this is compensated for by phosphorus pile-up due to field oxidation, and the parasitic MOSFET is inverted. You need to make sure the voltage is high enough. Pile-up of phosphorus becomes more noticeable during oxidation at low temperatures than at high temperatures, so as mentioned above, it is necessary to oxidize at a relatively low temperature of 900°C or less. After that, silicon nitride film 5
is removed and a CMOS semiconductor device is completed through normal steps.

Next, FIG. 2 shows the results of measuring the relationship between the inversion voltage of the parasitic MOSFET using the field oxide film as the gate insulating film and the boron ion implantation amount in this example.

In FIG. 2, curve a shows the characteristics of an n-well, and curve b shows the characteristics of a p-well. As can be seen from Fig. 2, the boron ion implantation amount is 4×lO'! /cd, the parasitic MOSF on the p-well and n-well
The inversion voltage of ET can be 12V or more. This inversion voltage can be said to be a sufficient value when considering the construction of a CMOS integrated circuit of about 5V.

〔Effect of the invention〕

As described above based on the embodiments, according to the present invention, a CMOS semiconductor device with a sufficiently high inversion voltage of a parasitic MOSFET can be easily manufactured without adding a photo process.

[Brief explanation of drawings]

1-8 (Cl is a manufacturing process diagram for explaining one embodiment of the method for manufacturing a CMOS semiconductor device according to the present invention, and FIG. 2 is a diagram showing the inversion voltage of a parasitic MOSFET and boron ion implantation. The diagram showing the relationship with the amount, Figure 3 8-fD) is
1 is a manufacturing process diagram showing a conventional method for manufacturing a CMOS semiconductor device. In the figure, l is a P-type semiconductor substrate, 2 is an n-well, 3 is a p-well, 4 is a pad oxide film, 5 is a silicon It film,
Reference numeral 6 indicates a resist pattern, 7 indicates a boron film, and 8 indicates a field oxide film.

Claims (1)

[Claims] 1. Forming a p-channel MOSFET on a semiconductor substrate
A CMOS comprising a p-well forming a well and an n-channel MOSFET, an oxidation-resistant film is selectively formed in the element regions of the n-well and p-well, and a field oxide film is formed by selectively oxidizing the isolation region. In a method for manufacturing a semiconductor device, after selectively forming an oxidation-resistant film in the element region and before selectively oxidizing the isolation region, boron is applied to the entire surface of the isolation region of both the p-well and the n-well. 1. A method for manufacturing a CMOS semiconductor device, comprising ion implantation. 2. The method of manufacturing a CMOS semiconductor device according to claim 1, wherein the selective oxidation of the isolation region is performed in a steam atmosphere at a temperature of 900° C. or lower. 3. The method of manufacturing a CMOS semiconductor device according to claim 1 or 2, wherein the boron ion implantation is performed using a resist pattern provided on the oxidation-resistant film as a mask.