JPH03215834A - Active matrix substrate - Google Patents

Abstract

PURPOSE:To decrease the signal delay on additive capacity wirings and to obtain the display device having a high image grade by electrically connecting the adjacent additive capacity wirings to each other and taking out leader wires from the junctures at both ends of the respective additive capacity wirings. CONSTITUTION:The additive capacity wirings 2 are formed between gate bus wirings 1a and 1b. The additive capacity wirings 2 adjacent to each other are connected on the side where leader wires 21a and 21b of the gate bus wirings 1a and 1b positioned therebetween are not provided. The leader wires 22 and 22b are led out of the junctures thereof and terminals 12a and 12b for the additive capacities of the width larger than the leader wires 22a and 22b are provided at the terminals thereof. The signals corresponding to the video signals impressed to picture element electrodes are supplied through common wirings 3a and 3b of the additive capacities from both ends of the additive capacity wirings 2 and, therefore, the signal delay wirings on the additive capacity wirings 2 are decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an active matrix substrate used in a display device using a liquid crystal or the like, and particularly to an active matrix substrate having additional capacitance.

(Prior Art) Conventionally, in liquid crystal display devices, EL display devices, plasma display devices, etc., picture element electrodes arranged in a matrix are selectively driven to form a display pattern on the screen.

A voltage is applied between a selected picture element electrode and a counter electrode facing the selected picture element electrode, and optical modulation of the display medium interposed therebetween is performed.

This optical modulation is visually recognized as a display pattern. As a method for driving picture element electrodes, an active matrix driving method is known in which individual picture element electrodes are arranged and a nonlinear element is connected to each of the picture element electrodes and driven. Nonlinear elements that selectively drive picture element electrodes include TPT (thin film transistor) elements and MI
M (metal-insulating layer-metal) elements, MoS transistor elements, diodes, varistors, etc. are generally known.

In an active matrix substrate using a TPT as a nonlinear element, gate bus wiring functioning as a scanning line and source bus wiring functioning as a signal line are provided to drive the TPT.

A gate-on signal is applied to the gate bus wiring, and a video signal is applied from the source bus wiring to the picture element electrode through the TPT. Further, in order to hold the video signal applied to the picture element electrode for one cycle until the next video signal is applied, an electrode for additional capacitance is often provided opposite the picture element electrode. Each additional capacitor electrode is connected to an additional capacitor wiring, and each additional capacitor wire is connected to an additional capacitor common wiring.

5 and 6 schematically show how gate bus wiring and additional capacitance wiring are provided in a conventional active matrix substrate using TPT as a nonlinear element. In the substrate shown in FIG. 5, gate bus lines 1 are provided in parallel, and additional capacitance lines 2 are provided in parallel between the gate bus lines 1.

A portion of the additional capacitance wiring 2 facing a picture element electrode (not shown) functions as an electrode for additional capacitance. The gate bus wiring 1 is drawn out in one of its extending directions, and a connection terminal 11 is provided at the end of the drawn line. The additional capacitance wiring 2 is drawn out to the opposite side from the gate bus wiring 1 and is electrically connected to the additional capacitance common wiring 3.

In the active matrix substrate of FIG. 6, the gate bus wiring 1 consists of a gate bus wiring 1a drawn out in one direction of its extension, and a gate bus wiring 1b drawn out in the other direction. Similarly, the additional capacitance wiring 2 has additional capacitance wiring 2a drawn out in one direction in its extension direction.
and an additional capacitance wiring 2b drawn out in the other direction. Picture element electrodes of additional capacitance wiring 2a and 2b (not shown)
The part facing -4- functions as an electrode for additional capacitance.

Gate bus wirings 1a and 1b are provided with connection terminals 11a and llb at their respective drawer-side ends.

Similarly, the additional capacitance wirings 2a and 2b are provided with additional capacitance terminals 12a and 12b at their respective ends in the drawing direction.

Therefore, in the substrate of FIG. 6, unlike the substrate of FIG. 5, the gate bus wiring 1 and the additional capacitance wiring 2 are drawn out from both sides of the substrate. Although not shown in FIGS. 5 and 6, source bus wiring and the like are further formed on these substrates.

(Problems to be Solved by the Invention) When an active matrix substrate provided with an additional capacitor in this manner is used in a display device, the aperture ratio of the display device is reduced because the additional capacitor wiring is made of a metal film. In order to reduce the reduction in aperture ratio, the additional capacitance wiring must be formed as thin as possible.

When the additional capacitance wiring becomes thinner, a delay is likely to occur in a signal sent onto the additional capacitance wiring in response to a video signal applied to the picture element electrode. Due to this signal delay, -5- when a display device is assembled using this substrate, the image quality of the display device will be degraded. Furthermore, when the additional capacitance wiring becomes thinner, disconnection defects are more likely to occur in the additional capacitance wiring during pattern formation of the additional capacitance wiring. If a disconnection failure occurs in the additional capacitor wiring, the video signal applied to the picture element electrode will not be held sufficiently, resulting in a decrease in the image quality of the display device.

Further, in order to ensure insulation between the additional capacitance wiring and the picture element electrode, an anodic oxide film obtained by anodizing the upper surface of the additional capacitance wiring is often provided on the additional capacitance wiring. When a break in the additional capacitance wiring occurs as described above, an anodic oxide film will not be formed on the portion of the additional capacitance wiring beyond the disconnection. In the portion of the additional capacitance wiring where the anodic oxide film is not formed, poor insulation is likely to occur between it and the picture element electrode.

Such insulation defects are also undesirable because they degrade the image quality of the display device.

Furthermore, in active matrix substrates used in display devices that perform high-definition displays, the number of gate bus lines and additional capacitance lines is enormous, and the spacing between terminals provided at the ends of the gate bus lines and additional capacitance lines is large. becomes very small. Therefore, when connecting these terminals on the substrate and the terminals on the film carrier, leakage current is likely to occur between the terminals other than the terminals to be connected.

The present invention solves the above-mentioned problems, and an object of the present invention is to provide an active matrix substrate that does not cause signal delay on additional capacitance wiring. Another object of the present invention is to provide an active matrix substrate in which image quality does not deteriorate when used in a display device even if a disconnection occurs in the additional capacitance wiring. Still another object of the present invention is to provide an active matrix substrate in which no leakage current occurs between terminals on a film carrier other than those to be connected.

(Means for Solving the Problems) An active matrix substrate of the present invention includes an insulating substrate,
comprising parallel scanning lines on the insulating substrate and additional capacitance wiring formed in parallel between each of the scanning lines,
The scanning lines in which the connection terminals are provided on one side in the extending direction of the scanning lines and the scanning lines in which the connection terminals are provided on the other side are provided alternately. Each of the additional capacitance wirings is electrically connected to each other on the opposite side of the connection terminal of the scanning line between the adjacent storage capacitance wirings, and a lead line drawn out from the connected portion, and a lead-out line drawn out from the connected portion. The wire has a terminal for additional capacitance provided at the end of the wire, thereby achieving the above object.

Further, an additional capacitance common wiring is formed which intersects the scanning line and the additional capacitance wiring and is electrically connected to each of the additional capacitance wiring, and the additional capacitance common wiring and the scanning line are connected to each other through an insulating film. It is also possible to have a configuration in which the two lines intersect.

Further, the additional capacitance terminal may be covered with an insulating film.

Further, a configuration may be adopted in which an anodic oxide film is formed on the additional capacitance wiring.

(Function) In the active matrix substrate of the present invention, the adjacent load capacitance wires are electrically connected to each other, and lead lines are provided from the connecting portions at both ends of each load capacitance wire. No signal delay occurs on wiring. Also,
Even if a disconnection failure occurs at one location on the additional capacitance wiring, this additional capacitance wiring can function normally. Further, even if a disconnection failure occurs at one location on the additional capacitance wiring during anodization, there will be no portion of the additional capacitance wiring where the anodic oxide film is not formed. Therefore, in a display device using this active matrix substrate, image quality does not deteriorate.

Further, in the active matrix substrate of the present invention, an additional capacitance common wiring connected to the additional capacitance wiring is provided. A signal supplied to the additional capacitance wiring in response to the video signal applied to the picture element electrode may be supplied by the additional capacitance common wiring. Further, an insulating film may be formed on the additional capacitor terminal provided at the end of the lead line of the additional capacitor wire. This configuration prevents leakage current from occurring between the terminal on the film carrier 9 corresponding to the connection terminal provided at the end of the gate bus wiring and the additional capacitance terminal.

(Example) The present invention will be described below with reference to an example. FIG. 1 shows a schematic diagram of an active matrix substrate of the present invention. In Figure 1, gate bus wiring 1a and lb, additional capacitance wiring 2
, and additional capacitance common wirings 3a and 3b are shown, and descriptions of picture element electrodes, source bus wiring, etc. are omitted. In the active matrix substrate of this embodiment, gate bus lines 1a and 1b are provided in parallel, a lead line 21a extends from one end of the gate bus line 1a, and a connection having a width larger than that of the lead line 21a is provided at the terminal end of the lead line 21a. A terminal 11a is provided. Similarly, a lead wire 2lb extends from one end of the gate bus wiring 1b, and a lead wire 2lb extends from one end of the gate bus wiring 1b.
A connecting terminal 1lb having a width larger than that of b is provided. The lead lines 21a and 2lb are drawn out from opposite sides.

Additional capacitance wiring 2 is provided between gate bus wiring 1a and 1b.
is formed. The additional capacitance-10 bulk wires 2 that are adjacent to each other are connected to each other on the sides of the gate bus wires 1a and 1b located between them, where the lead lines 21a and 2lb are not provided. Lead wires 22a and 22b are drawn out from the connection portion, and an additional capacitance terminal 12 having a width larger than that of the lead wires 22a and 22b is attached to the terminal end of the lead wires 22a and 22b.
a and 12b are provided. The lead wire 22a and the additional capacitor terminal 12a are provided on the same side of the gate bus wiring 1a as the lead wire 21a and the connection terminal 11a. Similarly, the lead wire 22b and the additional capacitor terminal 12b are connected to the lead wire 2l of the gate bus wiring 1b.
b and the connecting terminal 1lb are provided on the same side. Additional capacitor common wires 3a and 3b are formed perpendicularly to the gate bus wires 1a and 1b and the additional capacitor wire 2. The additional capacitance common wirings 3a and 3b are electrically connected to each of the additional capacitance wirings 2. Further, the additional capacitance common wiring 3as3b is connected to the gate bus wiring 1a, lb.
intersect with Ta205, SiNx film, aSi semiconductor layer, SiNx film, and n+ type a-St film, which will be described later, in between -11-.

2 to 4 show the manufacturing process of the active matrix substrate of FIG. 1. A Ta metal film was formed on the entire surface of the glass substrate by sputtering. This Ta metal film is formed by photolithography and etching to form gate bus wirings 1a, 1b, additional capacitance wiring 2, lead lines 21a, 2lb, 22a, 22b, and connection terminals 11a1 in the shapes shown in FIG.
11b1 and additional capacitance terminals 12a and 12b were patterned. Next, anodic oxidation was performed using the connection terminals 11a and llb and the additional capacitance terminals 12a and 12b. By this anodization, the gate bus lines 1a and 1b and the additional capacitance line 2 in the area A in FIG. , lb was formed with an anodic oxide film.

Since two additional capacitance terminals 12a and 12b are connected to each additional capacitance wiring 2, an anodic oxide film is formed on the additional capacitance wiring 2 even if a disconnection occurs at one place on the additional capacitance wiring 2. The parts that are not covered will not occur.

-12 First, in order to form a TPT (not shown), which is a nonlinear element, a SiNx film, an amorphous Si (hereinafter referred to as "a-SiJ") semiconductor layer, and an SiN.
It was deposited continuously over the entire surface of this substrate. Top SiN
．． The film was patterned, and an etching stopper was formed on the upper surface of the portion of the TPT that would become the semiconductor layer. Next, n+
A type a-Si film was deposited on the entire surface of this substrate, and the above-mentioned a-
The St semiconductor layer and this n+ type a-Si film were patterned to form a TPT semiconductor layer and a contact layer. Also, the contact layer is later divided into two parts below the source and drain electrodes of the TPT.

Next, the SIN. The membrane was removed. Next, a Ti metal layer is formed on the entire surface by sputtering, and additional capacitor common wirings 3a, 3
And source bus wirings 4a and 4b were patterned (FIG. 3).

The additional capacitance common wirings 3a and 3b are formed to be electrically connected to each additional capacitance wiring 2. Next, an ITo film was formed on the entire surface of this substrate and patterned to form picture element electrodes (not shown). Next, SiN which becomes the protective film 5
An x film was formed on the entire surface of this substrate. Gate bus wiring 1
on the connection terminals 11a and llb connected to the terminals a and lb, on the ends of the source bus wirings 4a and 4b, and on the additional capacitance common wiring 3
The protective film formed on the end portions a and 3b was removed to obtain the active matrix substrate shown in FIG. 4.

In the active matrix substrate of this embodiment, a signal corresponding to the video signal applied to the picture element electrode is supplied from both ends of the additional capacitor wiring 2 through the additional capacitor common wirings 3a and 3b. The above signal delay has been reduced. Furthermore, even if a disconnection failure occurs at one location on the additional capacitance wiring 2, the additional capacitance wiring 2 can function normally. Furthermore, since a protective film is formed on the additional capacitance terminals 12aS and 12b, when connecting the connection terminals 11a and llb connected to the gate bus wiring 1aslb and the terminals on the film carrier, the additional capacitance terminals 12aS and 12b are 12a,
12b and the terminals on the film carrier never come into contact with each other.

(Effects of the Invention) In the active matrix substrate of the present invention, signal delay on the additional capacitance wiring is reduced, so if this substrate is used in a display device, a display device with high image quality can be obtained. Furthermore, since the display device can function normally even if a disconnection occurs in the additional capacitance wiring, the yield of the display device is improved. Furthermore, since the connection terminals of the gate bus wiring and the terminals on the film carrier can be easily connected, the yield of the display device is also improved.

4.゛'s. Figure 1 is a schematic plan view of the active matrix substrate of the present invention, Figures 2 to 4 are diagrams showing the manufacturing process of the active matrix substrate of Figure 1, and Figures 5 and 6 are diagrams showing the manufacturing process of the active matrix substrate of the present invention. FIG. 3 is a diagram showing an active matrix substrate.

la, lb...Gate bus wiring, 2...Additional capacitance wiring, -15- 3a, 3b...Additional capacitance common wiring, 4a, 4. b...
・Source bus wiring, 5...protective film, lla, llb・
... Connection terminals, 1 2 a, 1 2 b ... Additional capacitance terminals, 21 a, 2 lb, 22 a, 22 b - lead wires.

Below Up

Claims (1)

[Claims] 1. An insulating substrate, parallel scanning lines on the insulating substrate, and additional capacitance wiring formed in parallel between each of the scanning lines, the scanning The scanning lines in which the connection terminals are provided on one side in the line extension direction and the scanning lines in which the connection terminals are provided on the other side are provided alternately, and each of the additional capacitance wirings is adjacent to each other. are electrically connected to each other on the opposite side of the connection terminal of the scanning line between the adjacent additional capacitor wirings, and a lead line drawn out from the connected portion and an end of the lead line An active matrix substrate having an additional capacitor terminal provided therein. 2. An additional capacitor common wiring is formed which intersects the scanning line and the additional capacitor wiring and is electrically connected to each of the additional capacitor wirings, and the additional capacitor common wiring and the scanning line are connected to each other through an insulating film. The active matrix substrate according to claim 1, wherein the active matrix substrates intersect with each other. 3. The active matrix substrate according to claim 2, wherein the additional capacitance terminal is covered with an insulating film. 4. The active matrix substrate according to claim 1, wherein an anodic oxide film is formed on the additional capacitance wiring.