JPH10221705A - Liquid crystal display element - Google Patents
Liquid crystal display elementInfo
- Publication number
- JPH10221705A JPH10221705A JP2530697A JP2530697A JPH10221705A JP H10221705 A JPH10221705 A JP H10221705A JP 2530697 A JP2530697 A JP 2530697A JP 2530697 A JP2530697 A JP 2530697A JP H10221705 A JPH10221705 A JP H10221705A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- insulating film
- liquid crystal
- gate
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】横電界モード（ＩＰＳ；イン
プレイン・スイッチングモード、とも言う）のＴＦＴ
（薄膜トランジスタ）マトリクス型の液晶表示素子に関
し、特に画素電極と共通電極との相対的位置ずれの防止
と、ゲート絶縁膜中に電荷が蓄積されることによる画面
の焼付の防止に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention TFT in an in-plane switching mode (IPS; also called in-plane switching mode)
(Thin Film Transistor) The present invention relates to a matrix type liquid crystal display device, and more particularly to prevention of relative displacement between a pixel electrode and a common electrode and prevention of screen burning due to accumulation of electric charges in a gate insulating film.
【０００２】[0002]
【従来の技術】従来のＴＦＴマトリクス型の液晶表示素
子（ＬＣＤと言う）は、ガラス基板の内面に画素電極及
びスイッチング素子としてのＴＦＴの形成されたＴＦＴ
アレイ基板と、ガラス基板の内面にほぼ一面に共通電極
の形成された対向基板とを近接対向させ、それらの間に
ＴＮ（ツイスト・ネマチック）形液晶などを封入して、
画素電極と共通電極との間に信号電圧を印加し、これに
より液晶に基板とほぼ直角な電界を印加して液晶分子を
動かし、光の透過を制御するのが最も一般的であった。2. Description of the Related Art A conventional TFT matrix type liquid crystal display device (referred to as LCD) is a TFT in which a pixel electrode and a TFT as a switching element are formed on an inner surface of a glass substrate.
An array substrate and an opposing substrate having a common electrode formed on the inner surface of a glass substrate are brought into close proximity to each other, and a TN (twisted nematic) liquid crystal or the like is sealed between them.
It is most common to apply a signal voltage between the pixel electrode and the common electrode, thereby applying an electric field substantially perpendicular to the substrate to the liquid crystal to move the liquid crystal molecules and control light transmission.
【０００３】これに対して、図７に示すようにＴＦＴア
レイ基板１に画素電極１２と共通電極８を噛み合うよう
に配置し、対向基板２には電極を形成しないで、両基板
間に液晶３を封入して、電極１２と８の間に信号電圧を
印加し、基板にほぼ平行な電界により液晶分子を動か
し、光の透過を制御するＩＰＳ（ｉｎ−ｐｌａｎｅ−ｓ
ｗｉｔｃｈｉｎｇ）モードが、視角特性に優れているこ
とから最近注目されている。On the other hand, as shown in FIG. 7, a pixel electrode 12 and a common electrode 8 are arranged on a TFT array substrate 1 so as to mesh with each other. Is applied, a signal voltage is applied between the electrodes 12 and 8, the liquid crystal molecules are moved by an electric field substantially parallel to the substrate, and IPS (in-plane-s) for controlling light transmission.
(Witching) mode has recently attracted attention because of its excellent viewing angle characteristics.
【０００４】図７に示す従来例では、ガラス基板６の内
面に第１層として金属より成るゲートバス７と、共通電
極８とが形成され、それらの上及び間に第２層としてゲ
ート絶縁膜９がほぼ一面に形成される。なおゲートバス
７、共通電極８はガラス基板６の周辺に延長され、外部
接続用端子（図示せず）が形成されるが、それら端子上
のゲート絶縁膜９はエッチングにより除去される。ゲー
ト絶縁膜９上にＴＦＴの半導体層（ａ−Ｓｉ）１０が形
成された後、第３層としてソース電極１１ａ、ソースバ
ス１１、ドレイン電極１２ａ、画素電極１２が形成され
る。画素電極１２は共通電極８の一部と重なるように形
成され、両者の間にゲート絶縁膜を誘電体とする蓄積容
量が形成される。それらソースバス１１、画素電極１２
等の形成されたガラス基板６の内面に第４層として絶縁
膜１３が一面に形成される。In the conventional example shown in FIG. 7, a gate bus 7 made of metal and a common electrode 8 are formed on the inner surface of a glass substrate 6 as a first layer, and a gate insulating film is formed as a second layer on and between them. 9 is formed on almost one surface. The gate bus 7 and the common electrode 8 extend around the glass substrate 6 to form external connection terminals (not shown). The gate insulating film 9 on these terminals is removed by etching. After the semiconductor layer (a-Si) 10 of the TFT is formed on the gate insulating film 9, a source electrode 11a, a source bus 11, a drain electrode 12a, and a pixel electrode 12 are formed as a third layer. The pixel electrode 12 is formed so as to overlap with a part of the common electrode 8, and a storage capacitor having a gate insulating film as a dielectric is formed between the two. The source bus 11 and the pixel electrode 12
An insulating film 13 is formed on the entire surface of the glass substrate 6 on which the insulating film 13 is formed as a fourth layer.
【０００５】対向基板２では、ガラス基板１４の内面に
ブラックマトリクス１５とカラーフィルタ１６が形成さ
れ、それらの上に一面に絶縁膜１７が形成される。なお
図７では、ゲート電極７ａ、ゲートバス７がソース電極
１１ａ、ドレイン電極１２ａ、半導体層１０の下側に配
されているので、ボトムゲート型のＴＦＴまたはＬＣＤ
と呼ばれる。更に図７ＡのＴＦＴ１９はチャネルエッチ
型で、図１０Ａに示すように半導体層１０の幅がソース
電極１１ａ、ドレイン電極１２ａの縁まで広がっている
場合もある。チャネルエッチ型の名はソース電極１１ａ
とドレイン電極１２ａの間の半導体層１０の導電性をも
つ表面層（ｎ+ ａ−Ｓｉより成るオーミックコンタクト
層）をエッチングして除去することから来ている。ボト
ムゲート型にはこの他に図１０Ｂに示すチャネル保護膜
型があり、広く用いられている。この場合は、半導体層
１０の表面層の上にＳｉＯ2 ，ＳｉＮｘなどのチャネル
保護膜２４が形成される。In the counter substrate 2, a black matrix 15 and a color filter 16 are formed on an inner surface of a glass substrate 14, and an insulating film 17 is formed on one surface of the black matrix 15 and the color filter 16. In FIG. 7, since the gate electrode 7a and the gate bus 7 are arranged below the source electrode 11a, the drain electrode 12a and the semiconductor layer 10, a bottom gate type TFT or LCD is used.
Called. Further, the TFT 19 in FIG. 7A is a channel-etch type, and the width of the semiconductor layer 10 may extend to the edges of the source electrode 11a and the drain electrode 12a as shown in FIG. 10A. The name of the channel etch type is the source electrode 11a.
This is because the conductive surface layer (an ohmic contact layer made of n + a-Si) of the semiconductor layer 10 between the gate electrode and the drain electrode 12a is removed by etching. In addition to the bottom gate type, there is a channel protective film type shown in FIG. 10B, which is widely used. In this case, a channel protection film 24 such as SiO 2 or SiNx is formed on the surface layer of the semiconductor layer 10.
【０００６】[0006]
【発明が解決しようとする課題】図７の従来例では、第
１層に共通電極８が、第３層に画素電極１２がそれぞれ
形成されている。即ち電極８と１２は別々の層で形成さ
れている。電極８及び１２それぞれの製造工程で使用す
るマスクパターン間で相対的な位置ずれが無ければ、図
８Ａに示すように両電極間の距離ａ，ｂは相等しいよう
にされている（ａ＝ｂ）。しかしながら、実際にはマス
クパターン間の位置ずれが存在し、例えば画素電極１２
が図において右側にずれるか、或いは共通電極８が左側
にずれて形成されると、上記電極間の距離がａ′，ｂ′
に変化し、ａ′＜ａ，ｂ′＞ｂとなる。そうすると、
ａ，ｂに対応する領域で両電極間に印加される電界強度
Ｅａ＝Ｅｂは、Ｅａ′＞Ｅｂ′となり、この液晶パネル
の輝度対印加電圧特性は、ａ′またはｂ′区間では、そ
れぞれ理想的な特性（ａ＝ｂ）を図において左側また
は右側にシフトしたようなまたはの特性となり、Ｌ
ＣＤの光学特性が変化する。そのため画面全体に表示む
らが発生する。In the conventional example of FIG. 7, a common electrode 8 is formed on a first layer, and a pixel electrode 12 is formed on a third layer. That is, the electrodes 8 and 12 are formed of different layers. If there is no relative displacement between the mask patterns used in the manufacturing processes of the electrodes 8 and 12, the distances a and b between the two electrodes are made equal as shown in FIG. 8A (a = b). ). However, actually, there is a misalignment between the mask patterns, for example, the pixel electrode 12
Is shifted to the right in the figure or the common electrode 8 is formed shifted to the left in the figure, the distance between the electrodes becomes a ', b'.
And a '<a, b'> b. Then,
The electric field intensity Ea = Eb applied between the electrodes in the regions corresponding to a and b is Ea '>Eb', and the luminance versus applied voltage characteristic of this liquid crystal panel is ideal in the a 'or b' section. Characteristic (a = b) is shifted to the left or right in the figure, or
The optical characteristics of the CD change. Therefore, display unevenness occurs on the entire screen.
【０００７】また、図７の従来例では画素領域のゲート
絶縁膜９及び絶縁膜１３中及び各膜との界面の蓄積電荷
によって液晶側の電気力線１８（電界に対応する）が影
響を受け、そのため画面の焼付け現象が発生する問題が
ある。また、絶縁膜中に蓄積電荷がない場合でも画素電
極１２と共通電極８との間の電界が絶縁膜により分極さ
れる。つまり、液晶層をスイッチングさせるために、高
い駆動電圧が必要となり、消費電力の増加になる。In the prior art shown in FIG. 7, electric lines of force 18 (corresponding to an electric field) on the liquid crystal side are affected by accumulated charges in the gate insulating film 9 and the insulating film 13 in the pixel region and at the interface with each film. Therefore, there is a problem that a screen burning phenomenon occurs. Further, even when there is no accumulated charge in the insulating film, the electric field between the pixel electrode 12 and the common electrode 8 is polarized by the insulating film. That is, in order to switch the liquid crystal layer, a high driving voltage is required, and power consumption increases.
【０００８】この発明は、画素電極１２と共通電極８と
の相対的な位置ずれのために生ずる表示むらと、絶縁膜
中の蓄積電荷による画面の焼付を防止することを目的と
している。An object of the present invention is to prevent display unevenness caused by a relative displacement between the pixel electrode 12 and the common electrode 8 and to prevent screen burn-in due to accumulated charges in the insulating film.
【０００９】[0009]
（１）請求項１の発明は、ガラス基板の内面にトップゲ
ート型ＴＦＴ（薄膜トランジスタ）、画素電極、共通電
極の形成されたＴＦＴアレイ基板と、対向基板とが液晶
層を挟んで近接対向され、それら基板とほぼ平行な電界
により液晶分子を動かして光の透過を制御するＩＰＳ
（イン・プレイン・スイッチング）モード・トップゲー
ト型・ＴＦＴマトリクス型の液晶表示素子に関する。請
求項１では、ＴＦＴのソース電極及びドレイン電極と、
それらソース電極及びドレイン電極にそれぞれ接続され
たソースバス及び画素電極と、共通電極とが、ガラス基
板の内面に同じ層として形成される。ソース電極とドレ
イン電極の間及びその近傍に半導体層が形成され、各種
の電極、バス及び半導体層の形成されたガラス基板の内
面に、ゲート絶縁膜が、各画素の表示領域を除いて形成
され、そのゲート絶縁膜上に、ゲートバスが半導体層と
重なるように形成される。ゲート絶縁膜上に、蓄積容量
用バスが画素電極の一部と重なるように形成される。 （２）請求項２の発明は、前記（１）における蓄積容量
用バスの代りに、隣接画素のゲートバスを利用したもの
であり、画素電極と隣接のゲートバスとの間にゲート絶
縁膜を誘電体とする蓄積容量が形成される。 （３）請求項３の発明もＩＰＳモード・トップゲート型
・ＴＦＴマトリクス型の液晶表示素子に関する。請求項
３では、ＴＦＴのソース電極及びドレイン電極と、その
ソース電極に接続されたソースバスとがガラス基板の内
面に同じ層として形成され、それらソース電極とドレイ
ン電極との間及びその近傍に半導体層が形成され、それ
ら各種電極、バス及び半導体層の形成されたガラス基板
の内面にゲート絶縁膜が一面に形成される。そのゲート
絶縁膜上に、ゲートバスと、画素電極及び共通電極とが
同じ層として形成され、画素電極は、ゲート絶縁膜に形
成されたコンタクトホールを通じてドレイン電極に接続
される。共通電極は、ドレイン電極の一部と重なるよう
に形成され、それら両電極の間に、ゲート絶縁膜を誘電
体とする蓄積容量が形成される。 （４）請求項４の発明は、ＩＰＳモード・ボトムゲート
型・ＴＦＴマトリクス型の液晶表示素子に関する。請求
項４では、ＴＦＴのゲートバスと、蓄積容量用バスと
が、ガラス基板の内面に同じ層として形成され、それら
ゲートバス及び蓄積容量用バスの形成されたガラス基板
の内面に、ゲート絶縁膜が一面に形成される。そのゲー
ト絶縁膜上に、ＴＦＴの半導体層または半導体層とその
上のチャネル保護膜とがゲートバスと重なるように形成
され、その半導体層または半導体層とチャネル保護膜の
形成されたゲート絶縁膜上に、ＴＦＴのソース電極及び
ドレイン電極と、それらソース電極及びドレイン電極に
それぞれ接続されたソースバス及び画素電極と、共通電
極とが同じ層として形成される。画素電極の一部が蓄積
容量用バスと重なるように形成される。 （５）請求項５の発明は、前記（１）における蓄積容量
用バスの代りに、隣接画素のゲートバスを使用したもの
であり、画素電極と隣接ゲートバスとの間にゲート絶縁
膜を誘電体とする蓄積容量が形成される。 （６）請求項６の発明も、ＩＰＳモード・ボトムゲート
型・ＴＦＴマトリクス型の液晶表示素子に関する。請求
項６では、ＴＦＴのゲートバスと、画素電極及び共通電
極とが、ガラス基板の内面に同じ層として形成される。
それら各種電極、バスの形成されたガラス基板の内面に
ゲート絶縁膜が、各画素の表示領域を除いて形成され、
そのゲート絶縁膜上に、ＴＦＴの半導体層または半導体
層とその上のチャネル保護膜とが形成され、その半導体
層または半導体層とチャネル保護膜の形成されたゲート
絶縁膜上に、ＴＦＴのソース電極及びドレイン電極と、
そのソース電極に接続されたソースバスとが同じ層とし
て形成される。ドレイン電極は、ゲート絶縁膜に形成さ
れたコンタクトホールを通じて画素電極に接続される。
ドレイン電極の一部が共通電極と重なるよう形成され、
それら両電極の間にゲート絶縁膜を誘電体とする蓄積容
量が形成される。(1) The invention according to claim 1 is that a TFT array substrate having a top gate type TFT (thin film transistor), a pixel electrode, and a common electrode formed on an inner surface of a glass substrate is closely opposed to a counter substrate with a liquid crystal layer interposed therebetween. An IPS that controls the transmission of light by moving liquid crystal molecules by an electric field that is almost parallel to those substrates
The present invention relates to a (in-plane switching) mode top gate type / TFT matrix type liquid crystal display device. According to claim 1, a source electrode and a drain electrode of the TFT,
The source bus and the pixel electrode connected to the source electrode and the drain electrode, respectively, and the common electrode are formed as the same layer on the inner surface of the glass substrate. A semiconductor layer is formed between and near the source electrode and the drain electrode, and a gate insulating film is formed on an inner surface of a glass substrate on which various electrodes, buses, and the semiconductor layer are formed, excluding a display region of each pixel. A gate bus is formed on the gate insulating film so as to overlap the semiconductor layer. The storage capacitor bus is formed on the gate insulating film so as to overlap a part of the pixel electrode. (2) According to a second aspect of the invention, a gate bus of an adjacent pixel is used instead of the storage capacitor bus in the above (1), and a gate insulating film is provided between the pixel electrode and the adjacent gate bus. A storage capacitor serving as a dielectric is formed. (3) The invention of claim 3 also relates to an IPS mode top gate type / TFT matrix type liquid crystal display device. According to the third aspect, the source electrode and the drain electrode of the TFT and the source bus connected to the source electrode are formed as the same layer on the inner surface of the glass substrate, and the semiconductor is provided between and near the source electrode and the drain electrode. A layer is formed, and a gate insulating film is formed all over the inner surface of the glass substrate on which the various electrodes, buses, and semiconductor layers are formed. A gate bus, a pixel electrode and a common electrode are formed as the same layer on the gate insulating film, and the pixel electrode is connected to a drain electrode through a contact hole formed in the gate insulating film. The common electrode is formed so as to overlap a part of the drain electrode, and a storage capacitor having a gate insulating film as a dielectric is formed between the two electrodes. (4) The invention of claim 4 relates to an IPS mode bottom gate type / TFT matrix type liquid crystal display device. According to claim 4, the gate bus of the TFT and the storage capacitor bus are formed as the same layer on the inner surface of the glass substrate, and the gate insulating film is formed on the inner surface of the glass substrate on which the gate bus and the storage capacitor bus are formed. Are formed on one surface. On the gate insulating film, a semiconductor layer or a semiconductor layer of the TFT and a channel protective film thereover are formed so as to overlap the gate bus, and on the gate insulating film on which the semiconductor layer or the semiconductor layer and the channel protective film are formed. Then, a source electrode and a drain electrode of the TFT, a source bus and a pixel electrode respectively connected to the source electrode and the drain electrode, and a common electrode are formed as the same layer. Part of the pixel electrode is formed so as to overlap the storage capacitor bus. (5) According to a fifth aspect of the present invention, a gate bus of an adjacent pixel is used in place of the storage capacitor bus in (1), and a gate insulating film is formed between the pixel electrode and the adjacent gate bus. A storage capacitor is formed as a body. (6) The invention of claim 6 also relates to an IPS mode bottom gate type / TFT matrix type liquid crystal display device. In claim 6, the gate bus of the TFT, the pixel electrode and the common electrode are formed as the same layer on the inner surface of the glass substrate.
A gate insulating film is formed on the inner surface of the glass substrate on which the various electrodes and buses are formed, excluding the display area of each pixel.
A semiconductor layer or a semiconductor layer of the TFT and a channel protective film thereon are formed on the gate insulating film, and a source electrode of the TFT is formed on the gate insulating film on which the semiconductor layer or the semiconductor layer and the channel protective film are formed. And a drain electrode;
The source bus connected to the source electrode is formed as the same layer. The drain electrode is connected to the pixel electrode through a contact hole formed in the gate insulating film.
A part of the drain electrode is formed to overlap the common electrode,
A storage capacitor having a gate insulating film as a dielectric is formed between the two electrodes.
【００１０】[0010]
（実施例１）請求項１の発明の実施例を図１に、図７と
対応する部分に同じ符号を付けて示す。図１ではトップ
ゲート型のＴＦＴ１９のソース電極１１ａ及びドレイン
電極１２ａと、それらソース電極１１ａ及びドレイン電
極１２ａにそれぞれ接続されたソースバス１１及び画素
電極１２と、共通電極８とが、ガラス基板６の内面に同
じ層として（この例では第１層として）形成される。ソ
ース電極１１ａとドレイン電極１２ａの間及びその近傍
にａ−Ｓｉなどの半導体層１０が形成される。前記各種
の電極、バス及び半導体層１０の形成されたガラス基板
６の内面に、ゲート絶縁膜９が、各画素の表示領域を除
いて形成される。(Embodiment 1) FIG. 1 shows an embodiment of the first aspect of the present invention, in which parts corresponding to those in FIG. In FIG. 1, the source electrode 11a and the drain electrode 12a of the top gate type TFT 19, the source bus 11 and the pixel electrode 12 connected to the source electrode 11a and the drain electrode 12a, respectively, and the common electrode 8 The same layer (in this example, the first layer) is formed on the inner surface. A semiconductor layer 10 of a-Si or the like is formed between the source electrode 11a and the drain electrode 12a and in the vicinity thereof. A gate insulating film 9 is formed on the inner surface of the glass substrate 6 on which the various electrodes, buses, and the semiconductor layer 10 are formed, except for the display area of each pixel.
【００１１】ゲート絶縁膜９上に、ゲートバス７が半導
体層１０と重なるように形成される。また、ゲート絶縁
膜９上に、蓄積容量用バス２０が画素電極１２の一部と
重なるように形成され、両者の間にゲート絶縁膜９を誘
電体とする蓄積容量Ｃｓが形成される。ソースバス１
１、共通電極８よりガラス基板６の周辺に延長された端
末部に外部接続用の端子が形成され、その端子上のゲー
ト絶縁膜９をエッチングにより除去する必要があるが、
その時同時に、各画素の表示領域のゲート絶縁膜９も除
去される。従って、工程数は増加しない。A gate bus 7 is formed on gate insulating film 9 so as to overlap with semiconductor layer 10. Further, a storage capacitor bus 20 is formed on the gate insulating film 9 so as to overlap a part of the pixel electrode 12, and a storage capacitor Cs having the gate insulating film 9 as a dielectric is formed therebetween. Source bus 1
1. A terminal for external connection is formed at a terminal portion extending from the common electrode 8 to the periphery of the glass substrate 6, and the gate insulating film 9 on the terminal needs to be removed by etching.
At the same time, the gate insulating film 9 in the display area of each pixel is also removed. Therefore, the number of steps does not increase.
【００１２】請求項１の発明では、画素電極１２と共通
電極８とを同じ層に形成するので同じ工程で同一のマス
クパターンを使用して同時に形成できる。従って、両電
極間の相対的な位置ずれは生じない。従って、従来例で
述べたような表示むらは発生しない。また各画素の表示
領域ではゲート絶縁膜９は除去されているので、画素電
極１２と共通電極８との間の電界に対応する電気力線１
８が従来例のようにゲート絶縁膜９等の蓄積電荷による
ＤＣ成分が液晶層に印加されるのを抑制できるため、画
面の焼付き現象は起きない。 （実施例２）実施例１の蓄積容量バス２０を設けない
で、図２に示すように隣接する一方の画素の画素電極１
２と他方の画素のゲートバス７とを一部重なるように配
置し、両者の間にゲート絶縁膜９を誘電体とする蓄積容
量Ｃｓを形成したのが請求項２の発明であり、実施例１
と同じ効果が得られる。 （実施例３）請求項３の発明では、図３に示すようにト
ップゲート型ＴＦＴのソース電極１１ａ及びドレイン電
極１２ａと、そのソース電極１２ａに接続されたソース
バス１１とがガラス基板６の内面に同じ層として形成さ
れる。ソース電極１１ａとドレイン電極１２ａとの間及
びその近傍にａ−Ｓｉなどの半導体層１０が形成され
る。それら各種電極、バス及び半導体層の形成されたガ
ラス基板６の内面にゲート絶縁膜９が一面に形成され
る。ゲート絶縁膜９上に、ゲートバス７及びゲート電極
７ａと、画素電極１２及び共通電極８とが同じ層として
形成される。According to the first aspect of the present invention, since the pixel electrode 12 and the common electrode 8 are formed in the same layer, they can be formed simultaneously in the same step using the same mask pattern. Therefore, there is no relative displacement between the two electrodes. Therefore, display unevenness as described in the conventional example does not occur. Further, since the gate insulating film 9 is removed in the display region of each pixel, the electric flux lines 1 corresponding to the electric field between the pixel electrode 12 and the common electrode 8 are removed.
8 prevents the DC component due to the accumulated charges in the gate insulating film 9 and the like from being applied to the liquid crystal layer as in the conventional example, so that the screen burn-in phenomenon does not occur. (Embodiment 2) Without providing the storage capacitor bus 20 of Embodiment 1, as shown in FIG.
3. The invention according to claim 2, wherein the storage capacitor Cs having the gate insulating film 9 as a dielectric is formed between the two and the gate bus 7 of the other pixel so as to partially overlap each other. 1
The same effect can be obtained. (Embodiment 3) In the invention of claim 3, as shown in FIG. 3, the source electrode 11a and the drain electrode 12a of the top gate type TFT and the source bus 11 connected to the source electrode 12a are formed on the inner surface of the glass substrate 6. Formed as the same layer. A semiconductor layer 10 of a-Si or the like is formed between the source electrode 11a and the drain electrode 12a and in the vicinity thereof. A gate insulating film 9 is formed on the entire inner surface of the glass substrate 6 on which the various electrodes, buses, and semiconductor layers are formed. On the gate insulating film 9, the gate bus 7 and the gate electrode 7a, and the pixel electrode 12 and the common electrode 8 are formed as the same layer.
【００１３】画素電極１２はゲート絶縁膜９に形成され
たコンタクトホール２２を通じてドレイン電極１２ａに
接続される。共通電極８はドレイン電極１２ａの一部と
重なるように形成され、両電極間にゲート絶縁膜９を誘
電体とする蓄積容量Ｃｓが形成される。図３において
も、画素電極１２と共通電極８とは同じ層に形成される
ので相対位置のずれはない。また、画素電極１２と共通
電極８との間及び上方にはゲート絶縁膜９はないので、
両電極の間の液晶側の電気力線１８（電界と対応する）
は、従来例のように絶縁膜１３やゲート絶縁膜９中の蓄
積電荷による影響を受けることはない。従って図３の場
合も、従来例のような画面の焼付は起らない。 （実施例４）請求項４の発明は、図４に示すようにＩＰ
Ｓモード・ボトムゲート型・ＴＦＴマトリクス型の液晶
表示素子に関する。図４では、ＴＦＴ１９のゲートバス
７と、蓄積容量用バス２０が、ガラス基板６の内面に同
じ層として形成される。ゲートバス７及び蓄積容量用バ
ス２０の形成されたガラス基板６の内面に、ゲート絶縁
膜９が一面に形成される。ゲート絶縁膜９上に、ＴＦＴ
の半導体層１０がゲートバス７と重なるように形成さ
れ、その半導体層１０の形成されたゲート絶縁膜９上
に、ＴＦＴのソース電極１１ａ及びドレイン電極１２ａ
と、それらソース電極１１ａ及びドレイン電極１２ａに
それぞれ接続されたソースバス１１及び画素電極１２
と、共通電極８とが同じ層として形成される。The pixel electrode 12 is connected to a drain electrode 12a through a contact hole 22 formed in the gate insulating film 9. The common electrode 8 is formed so as to overlap a part of the drain electrode 12a, and a storage capacitor Cs having the gate insulating film 9 as a dielectric is formed between the two electrodes. Also in FIG. 3, since the pixel electrode 12 and the common electrode 8 are formed on the same layer, there is no relative position shift. Since there is no gate insulating film 9 between and above the pixel electrode 12 and the common electrode 8,
Electric field lines 18 on the liquid crystal side between both electrodes (corresponding to the electric field)
Is not affected by the charges accumulated in the insulating film 13 and the gate insulating film 9 unlike the conventional example. Therefore, also in the case of FIG. 3, the screen burn-in unlike the conventional example does not occur. (Embodiment 4) As shown in FIG.
The present invention relates to an S mode, bottom gate type, TFT matrix type liquid crystal display element. In FIG. 4, the gate bus 7 of the TFT 19 and the storage capacitor bus 20 are formed as the same layer on the inner surface of the glass substrate 6. A gate insulating film 9 is formed on the entire inner surface of the glass substrate 6 on which the gate bus 7 and the storage capacitor bus 20 are formed. TFT on the gate insulating film 9
Is formed so as to overlap the gate bus 7, and the source electrode 11 a and the drain electrode 12 a of the TFT are formed on the gate insulating film 9 on which the semiconductor layer 10 is formed.
And a source bus 11 and a pixel electrode 12 connected to the source electrode 11a and the drain electrode 12a, respectively.
And the common electrode 8 are formed as the same layer.
【００１４】また、画素電極１２の一部が蓄積容量用バ
ス２０と重なるように形成され、両者の間にゲート絶縁
膜９を誘電体とする蓄積容量Ｃｓが形成される。図４の
場合もこれまでの例と同様の効果が得られる。図４では
ＴＦＴ１９としてチャネルエッチ型を示したが、チャネ
ル保護型（図１０Ｂ）を用いてもよい。 （実施例５）請求項５の発明は、図５に示すように図４
の蓄積容量（Ｃｓ）用バス２０の代りに隣接のゲートバ
ス７を用いた場合であり、同じ効果が得られる。なお、
図５のＴＦＴ１９をチャネル保護型（図１０Ｂ）に代え
てもよい。 （実施例６）請求項６の発明も、図６に示すように、Ｉ
ＰＳモード・ボトムゲート型・ＴＦＴマトリクス型の液
晶表示素子に関する。図６では、ＴＦＴ１９のゲートバ
ス７と、画素電極１２及び共通電極８とが、ガラス基板
６の内面に同じ層として形成される。それら各種電極、
バスの形成されたガラス基板６の内面に、ゲート絶縁膜
９が、各画素の表示領域を除いて形成される。A part of the pixel electrode 12 is formed so as to overlap with the storage capacitor bus 20, and a storage capacitor Cs having the gate insulating film 9 as a dielectric is formed between the two. In the case of FIG. 4 as well, the same effects as in the previous examples can be obtained. FIG. 4 shows a channel etch type as the TFT 19, but a channel protection type (FIG. 10B) may be used. (Embodiment 5) As shown in FIG.
This is the case where the adjacent gate bus 7 is used instead of the storage capacitor (Cs) bus 20 of FIG. In addition,
The TFT 19 in FIG. 5 may be replaced with a channel protection type (FIG. 10B). (Embodiment 6) As shown in FIG.
The present invention relates to a liquid crystal display element of a PS mode / bottom gate type / TFT matrix type. 6, the gate bus 7 of the TFT 19, the pixel electrode 12 and the common electrode 8 are formed on the inner surface of the glass substrate 6 as the same layer. Those various electrodes,
On the inner surface of the glass substrate 6 on which the bus is formed, a gate insulating film 9 is formed excluding the display area of each pixel.
【００１５】ゲート絶縁膜９上に、ＴＦＴの半導体層１
０が形成され、半導体層１０の形成されたゲート絶縁膜
９上に、ＴＦＴのソース電極１１ａ及びドレイン電極１
２ａと、そのソース電極１１ａに接続されたソースバス
１１とが、同じ層として形成される。ドレイン電極１２
ａは、ゲート絶縁膜９に形成されたコンタクトホール２
２を通じて画素電極１２に接続される。ドレイン電極１
２ａの一部が共通電極８と重なるよう形成され、それら
両電極の間にゲート絶縁膜９を誘電体とする蓄積容量Ｃ
ｓが形成される。図６の場合も図１〜図５の場合と同じ
効果が得られることは明らかである。また、図６のＴＦ
Ｔ１９をチャネル保護型（図１０Ｂ）に代えてもよい。 （その他）これまでの説明では、ＩＰＳモード・ＴＦＴ
マトリクス型ＬＣＤの場合を述べたが、この発明はＴＦ
Ｔを用いない従来の単純マトリクス型（ＸＹマトリクス
型）のようなパッシブ型のＩＰＳモード・ＬＣＤにも応
用できる。その場合、ソースバス１１に相当するバスを
例えば信号電極とし、共通電極８に相当するバスを走査
電極とすればよい。On the gate insulating film 9, the semiconductor layer 1 of the TFT is formed.
0 is formed and the source electrode 11a and the drain electrode 1 of the TFT are formed on the gate insulating film 9 on which the semiconductor layer 10 is formed.
2a and the source bus 11 connected to the source electrode 11a are formed as the same layer. Drain electrode 12
a is a contact hole 2 formed in the gate insulating film 9;
2 to the pixel electrode 12. Drain electrode 1
2a is formed so as to overlap with the common electrode 8, and a storage capacitor C having a gate insulating film 9 as a dielectric between the two electrodes.
s is formed. It is clear that the same effect as in FIGS. 1 to 5 can be obtained in the case of FIG. Also, the TF of FIG.
T19 may be replaced with a channel protection type (FIG. 10B). (Other) In the description so far, IPS mode TFT
Although the case of a matrix type LCD has been described, the present invention relates to a TF
It can be applied to a passive IPS mode LCD such as a conventional simple matrix type (XY matrix type) that does not use T. In this case, a bus corresponding to the source bus 11 may be used as a signal electrode, for example, and a bus corresponding to the common electrode 8 may be used as a scan electrode.
【００１６】[0016]
【発明の効果】 この発明では、画素電極１２と共通電極８は同じ層
として形成されるので、同一工程で、同じマスクを用い
て同時に作製できる。よって、両者の間の相対的な位置
ずれは生じないので、従来のような位置ずれによる表示
むらは生じない。 各画素の表示領域において、画素電極１２及び共通
電極８の上方（液晶側）にはゲート絶縁膜９などの絶縁
膜は存在しないので、従来のように絶縁膜内の蓄積電荷
により、液晶側の電気力線１８が影響を受けることがな
く、よって画面の焼付現象は起らない。 この発明は、従来技術に比べて製造工程数を増やす
ことなく行える。 この発明はＴＦＴを用いないパッシブ型のＩＰＳモ
ードＬＣＤにも応用できる。According to the present invention, since the pixel electrode 12 and the common electrode 8 are formed as the same layer, they can be simultaneously manufactured in the same step using the same mask. Therefore, since there is no relative displacement between the two, there is no display unevenness due to the conventional displacement. In the display area of each pixel, there is no insulating film such as the gate insulating film 9 above the pixel electrode 12 and the common electrode 8 (on the liquid crystal side). The lines of electric force 18 are not affected, so that a screen burning phenomenon does not occur. The present invention can be performed without increasing the number of manufacturing steps as compared with the related art. The present invention can be applied to a passive IPS mode LCD that does not use a TFT.
【図１】請求項１の実施例を示す図で、ＡはＢのａ−
ａ′断面図、Ｂは平面図。FIG. 1 is a diagram showing an embodiment of claim 1, wherein A is a- of B;
a ′ sectional view, B is a plan view.
【図２】請求項２の実施例を示す図で、ＡはＢのａ−
ａ′断面図、Ｂは平面図。FIG. 2 is a diagram showing an embodiment of claim 2, wherein A is a- of B;
a ′ sectional view, B is a plan view.
【図３】請求項３の実施例を示す図で、ＡはＢのａ−
ａ′断面図、Ｂは平面図。FIG. 3 is a view showing an embodiment of claim 3, wherein A is a- of B;
a ′ sectional view, B is a plan view.
【図４】請求項４の実施例を示す図で、ＡはＢのａ−
ａ′断面図、Ｂは平面図。FIG. 4 is a view showing an embodiment of claim 4, wherein A is a- of B;
a ′ sectional view, B is a plan view.
【図５】請求項５の実施例を示す図で、ＡはＢのａ−
ａ′断面図、Ｂは平面図。FIG. 5 is a view showing an embodiment of claim 5, wherein A is a- of B;
a ′ sectional view, B is a plan view.
【図６】請求項６の実施例を示す図で、ＡはＢのａ−
ａ′断面図、Ｂは平面図。FIG. 6 is a view showing an embodiment of claim 6, wherein A is a- of B;
a ′ sectional view, B is a plan view.
【図７】従来のＩＰＳモード・ボトムゲート型・ＴＦＴ
マトリクスＬＣＤを示す図で、ＡはＢのａ−ａ′断面
図、Ｂは平面図。FIG. 7: Conventional IPS mode bottom gate type TFT
FIG. 3 is a view showing a matrix LCD, wherein A is a sectional view taken along line aa ′ of B and B is a plan view.
【図８】図７の画素電極１２と共通電極８との相対位置
を示す原理的な平面図。8 is a principle plan view showing a relative position between a pixel electrode 12 and a common electrode 8 in FIG. 7;
【図９】図８の各表示領域におけるパネルの輝度対印加
電圧特性を示す図。FIG. 9 is a diagram showing the luminance versus applied voltage characteristics of the panel in each display area of FIG. 8;
【図１０】ボトムゲート型ＴＦＴの断面図で、Ａはチャ
ネルエッチ型、Ｂはチャネル保護膜型を示す。FIGS. 10A and 10B are cross-sectional views of a bottom gate type TFT, wherein A denotes a channel etch type, and B denotes a channel protective film type.
Claims (6)
Ｔ（薄膜トランジスタ）、画素電極、共通電極の形成さ
れたＴＦＴアレイ基板と、対向基板とが液晶層を挟んで
近接対向され、それら基板とほぼ平行な電界により液晶
分子を動かして光の透過を制御するＩＰＳ（イン・プレ
イン・スイッチング）モード・トップゲート型・ＴＦＴ
マトリクス型の液晶表示素子において、 前記ＴＦＴのソース電極及びドレイン電極と、それらソ
ース電極及びドレイン電極にそれぞれ接続されたソース
バス及び前記画素電極と、前記共通電極とが、前記ガラ
ス基板の内面に同じ層として形成され、 前記ソース電極とドレイン電極の間及びその近傍に半導
体層が形成され、 前記各種の電極、バス及び半導体層の形成された前記ガ
ラス基板の内面に、ゲート絶縁膜が、各画素の表示領域
を除いて形成され、 そのゲート絶縁膜上に、ゲートバスが前記半導体層と重
なるように形成され、 前記ゲート絶縁膜上に、蓄積容量用バスが前記画素電極
の一部と重なるように形成されていることを特徴とする
液晶表示素子。1. A top gate type TF is provided on an inner surface of a glass substrate.
The TFT array substrate on which the T (thin film transistor), pixel electrode, and common electrode are formed is opposed to the opposing substrate with the liquid crystal layer interposed therebetween, and the liquid crystal molecules are moved by an electric field substantially parallel to the substrates to control light transmission. IPS (in-plane switching) mode top gate type TFT
In a matrix-type liquid crystal display element, a source electrode and a drain electrode of the TFT, a source bus connected to the source electrode and a drain electrode connected to the drain electrode, and the common electrode are the same on the inner surface of the glass substrate. A semiconductor layer is formed between and near the source electrode and the drain electrode, and a gate insulating film is formed on an inner surface of the glass substrate on which the various electrodes, buses, and semiconductor layers are formed. A gate bus is formed on the gate insulating film so as to overlap the semiconductor layer, and a storage capacitor bus overlaps a part of the pixel electrode on the gate insulating film. A liquid crystal display device characterized by being formed in a liquid crystal display device.
Ｔ、画素電極、共通電極の形成されたＴＦＴアレイ基板
と、対向基板とが液晶層を挟んで近接対向され、それら
基板とほぼ平行な電界により液晶分子を動かして光の透
過を制御するＩＰＳモード・トップゲート型・ＴＦＴマ
トリクス型の液晶表示素子において、 前記ＴＦＴのソース電極及びドレイン電極と、それらソ
ース電極及びドレイン電極にそれぞれ接続されたソース
バス及び前記画素電極と、前記共通電極とが、前記ガラ
ス基板の内面の同じ層に形成され、 前記ソース電極とドレイン電極の間及びその近傍に半導
体層が形成され、 前記各種の電極、バス及び半導体層の形成された前記ガ
ラス基板の内面に、ゲート絶縁膜が、各画素の表示領域
を除いて形成され、 そのゲート絶縁膜上に、ゲートバスが前記半導体層及び
隣接画素の画素電極の一部と重なるように形成され、 隣接する一方の画素の画素電極と他方の画素のゲートバ
スとの間に前記ゲート絶縁膜を誘電体とする蓄積容量が
形成されていることを特徴とする液晶表示素子。2. A top gate type TF is formed on an inner surface of a glass substrate.
An IPS mode in which a TFT array substrate on which T, pixel electrodes, and common electrodes are formed is opposed to a counter substrate with a liquid crystal layer interposed therebetween, and the liquid crystal molecules are moved by an electric field substantially parallel to the substrates to control light transmission. In a liquid crystal display device of a top gate type and a TFT matrix type, the source electrode and the drain electrode of the TFT, the source bus and the pixel electrode connected to the source electrode and the drain electrode, respectively, and the common electrode, A semiconductor layer is formed on the same layer on the inner surface of the glass substrate, a semiconductor layer is formed between and near the source electrode and the drain electrode, and a gate is formed on the inner surface of the glass substrate on which the various electrodes, buses and semiconductor layers are formed An insulating film is formed excluding a display area of each pixel, and a gate bus is formed on the semiconductor layer and the pixel of an adjacent pixel on the gate insulating film. A storage capacitor is formed so as to overlap with a part of the electrode, and a storage capacitor having the gate insulating film as a dielectric is formed between a pixel electrode of one adjacent pixel and a gate bus of the other pixel. Liquid crystal display device.
Ｔ、画素電極、共通電極の形成されたＴＦＴアレイ基板
と、対向基板とが液晶層を挟んで近傍対向され、それら
基板とほぼ平行な電界により液晶分子を動かして光の透
過を制御するＩＰＳモード・トップゲート型・ＴＦＴマ
トリクス型の液晶表示素子において、 前記ＴＦＴのソース電極及びドレイン電極と、そのソー
ス電極に接続されたソースバスとが前記ガラス基板の内
面に同じ層として形成され、 それらソース電極とドレイン電極との間及びその近傍に
半導体層が形成され、 それら各種電極、バス及び半導体層の形成された前記ガ
ラス基板の内面にゲート絶縁膜が一面に形成され、 そのゲート絶縁膜上に、ゲートバスと、前記画素電極及
び共通電極とが同じ層として形成され、 前記画素電極は、前記ゲート絶縁膜に形成されたコンタ
クトホールを通じて前記ドレイン電極に接続され、 前記共通電極は、前記ドレイン電極の一部と重なるよう
に形成され、それら両電極の間に、前記ゲート絶縁膜を
誘電体とする蓄積容量が形成されていることを特徴とす
る液晶表示素子。3. A top gate type TF on an inner surface of a glass substrate.
An IPS mode in which a TFT array substrate on which a T, a pixel electrode, and a common electrode are formed and a counter substrate are opposed to each other with a liquid crystal layer interposed therebetween, and liquid crystal molecules are moved by an electric field substantially parallel to the substrates to control light transmission. In a top gate type / TFT matrix type liquid crystal display device, a source electrode and a drain electrode of the TFT and a source bus connected to the source electrode are formed as the same layer on the inner surface of the glass substrate, and the source electrode A semiconductor layer is formed between and in the vicinity of the drain electrode, and a gate insulating film is formed on the entire inner surface of the glass substrate on which the various electrodes, buses, and semiconductor layers are formed, and on the gate insulating film, A gate bus, the pixel electrode and the common electrode are formed as the same layer, and the pixel electrode is formed of a contour formed on the gate insulating film. The common electrode is formed so as to overlap a part of the drain electrode, and a storage capacitor having the gate insulating film as a dielectric is formed between the two electrodes. A liquid crystal display device characterized by the above-mentioned.
Ｔ、画素電極、共通電極の形成されたＴＦＴアレイ基板
と、対向基板とが液晶層を挟んで近接対向され、それら
基板とほぼ平行な電界により液晶分子を動かして光の透
過を制御するＩＰＳモード・ボトムゲート型・ＴＦＴマ
トリクス型の液晶表示素子において、 前記ＴＦＴのゲートバスと、蓄積容量用バスとが、前記
ガラス基板の内面に同じ層として形成され、 それらゲートバス及び蓄積容量用バスの形成された前記
ガラス基板の内面に、ゲート絶縁膜が一面に形成され、 そのゲート絶縁膜上に、前記ＴＦＴの半導体層または半
導体層とその上のチャネル保護膜とが前記ゲートバスと
重なるように形成され、 その半導体層または半導体層とチャネル保護膜の形成さ
れたゲート絶縁膜上に、前記ＴＦＴのソース電極及びド
レイン電極と、それらソース電極及びドレイン電極にそ
れぞれ接続されたソースバス及び前記画素電極と、前記
共通電極とが同じ層として形成され、 前記画素電極の一部が前記蓄積容量用バスと重なるよう
に形成されていることを特徴とする液晶表示素子。4. A bottom gate type TF is provided on an inner surface of a glass substrate.
An IPS mode in which a TFT array substrate on which T, pixel electrodes, and common electrodes are formed is opposed to a counter substrate with a liquid crystal layer interposed therebetween, and the liquid crystal molecules are moved by an electric field substantially parallel to the substrates to control light transmission. In the bottom gate type TFT matrix type liquid crystal display element, the gate bus of the TFT and the bus for the storage capacitor are formed as the same layer on the inner surface of the glass substrate, and the formation of the gate bus and the bus for the storage capacitor is performed. A gate insulating film is formed on the entire inner surface of the glass substrate, and a semiconductor layer or a semiconductor layer of the TFT and a channel protective film thereover are formed on the gate insulating film so as to overlap the gate bus. Forming a source electrode and a drain electrode of the TFT on the gate insulating film on which the semiconductor layer or the semiconductor layer and the channel protective film are formed; A source bus connected to the source electrode and the drain electrode, the pixel electrode, and the common electrode are formed as the same layer, and a part of the pixel electrode is formed so as to overlap the storage capacitor bus. A liquid crystal display device characterized by the above-mentioned.
Ｔ、画素電極、共通電極の形成されたＴＦＴアレイ基板
と、対向基板とが液晶層を挟んで近接対向され、それら
基板とほぼ平行な電界により液晶分子を動かして光の透
過を制御するＩＰＳモード・ボトムゲート型・ＴＦＴマ
トリクス型の液晶表示素子において、 前記ＴＦＴのゲートバスが前記ガラス基板の内面に形成
され、 そのゲートバスの形成された前記ガラス基板の内面にゲ
ート絶縁膜が一面に形成され、 そのゲート絶縁膜上に、前記ＴＦＴの半導体層または半
導体層とその上のチャネル保護膜とが前記ゲートバスと
重なるように形成され、 その半導体層または半導体層とチャネル保護膜の形成さ
れたゲート絶縁膜上に、前記ＴＦＴのソース電極及びド
レイン電極と、それらソース電極及びドレイン電極にそ
れぞれ接続されたソースバス及び画素電極と、前記共通
電極とが同じ層として形成され、 前記画素電極の一部が隣接画素のゲートバスと重なるよ
うに形成され、両者の間にゲート絶縁膜を誘電体とする
蓄積容量が形成されていることを特徴とする液晶表示素
子。5. A bottom gate type TF is provided on an inner surface of a glass substrate.
An IPS mode in which a TFT array substrate on which T, pixel electrodes, and common electrodes are formed is opposed to a counter substrate with a liquid crystal layer interposed therebetween, and the liquid crystal molecules are moved by an electric field substantially parallel to the substrates to control light transmission. In a bottom gate type / TFT matrix type liquid crystal display element, a gate bus of the TFT is formed on an inner surface of the glass substrate, and a gate insulating film is formed on an entire surface of the glass substrate on which the gate bus is formed. A semiconductor layer or a semiconductor layer of the TFT and a channel protective film thereover formed on the gate insulating film so as to overlap the gate bus, and a gate on which the semiconductor layer or the semiconductor layer and the channel protective film are formed; On the insulating film, a source electrode and a drain electrode of the TFT and a source bar connected to the source electrode and the drain electrode, respectively. And the common electrode are formed as the same layer, a part of the pixel electrode is formed so as to overlap a gate bus of an adjacent pixel, and a storage capacitor having a gate insulating film as a dielectric therebetween. A liquid crystal display element characterized by having a pattern formed thereon.
Ｔ、画素電極、共通電極の形成されたＴＦＴアレイ基板
と、対向基板とが液晶層を挟んで近接対向され、それら
基板とほぼ平行な電界により液晶分子を動かして光の透
過を制御するＩＰＳモード・ボトムゲート型・ＴＦＴマ
トリクス型の液晶表示素子において、 前記ＴＦＴのゲートバスと、前記画素電極及び共通電極
とが、前記ガラス基板の内面に同じ層として形成され、 それら各種電極、バスの形成されたガラス基板の内面に
ゲート絶縁膜が、各画素の表示領域を除いて形成され、 そのゲート絶縁膜上に、前記ＴＦＴの半導体層または半
導体層とその上のチャネル保護膜とが形成され、 その半導体層または半導体層とチャネル保護膜の形成さ
れたゲート絶縁膜上に、前記ＴＦＴのソース電極及びド
レイン電極と、そのソース電極に接続されたソースバス
とが同じ層として形成され、 前記ドレイン電極は、前記ゲート絶縁膜に形成されたコ
ンタクトホールを通じて前記画素電極に接続され、 前記ドレイン電極の一部が前記共通電極と重なるよう形
成され、それら両電極の間に前記ゲート絶縁膜を誘電体
とする蓄積容量が形成されていることを特徴とする液晶
表示素子。6. A bottom gate type TF is provided on an inner surface of a glass substrate.
An IPS mode in which a TFT array substrate on which T, pixel electrodes, and common electrodes are formed is opposed to a counter substrate with a liquid crystal layer interposed therebetween, and the liquid crystal molecules are moved by an electric field substantially parallel to the substrates to control light transmission. In the bottom gate type TFT matrix type liquid crystal display element, the gate bus of the TFT, the pixel electrode and the common electrode are formed as the same layer on the inner surface of the glass substrate, and the various electrodes and buses are formed. A gate insulating film is formed on the inner surface of the glass substrate except for a display region of each pixel, and a semiconductor layer or a semiconductor layer of the TFT and a channel protective film thereon are formed on the gate insulating film. A source electrode and a drain electrode of the TFT and a source electrode connected to the source electrode and the drain electrode are formed on the semiconductor layer or the gate insulating film on which the semiconductor layer and the channel protective film are formed. The drain bus is formed as the same layer, the drain electrode is connected to the pixel electrode through a contact hole formed in the gate insulating film, and a part of the drain electrode is formed to overlap the common electrode. And a storage capacitor having the gate insulating film as a dielectric is formed between the two electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2530697A JPH10221705A (en) | 1997-02-07 | 1997-02-07 | Liquid crystal display element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2530697A JPH10221705A (en) | 1997-02-07 | 1997-02-07 | Liquid crystal display element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10221705A true JPH10221705A (en) | 1998-08-21 |
Family
ID=12162339
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2530697A Withdrawn JPH10221705A (en) | 1997-02-07 | 1997-02-07 | Liquid crystal display element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10221705A (en) |
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