KR100621533B1 - Array substrate for Liquid crystal display and method for fabricating thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a liquid crystal display device, and in particular, in order to prevent disconnection or short circuit of the wiring due to static electricity generated during the manufacturing process of the array substrate, each of the wirings is divided into odd-numbered and even-numbered lines and connected to each other. The present invention relates to an array substrate for a liquid crystal display device, the array substrate having a structure for preventing disconnection of the wiring due to a chemical electrical reaction occurring between the short circuit and the pixel electrode used to connect the respective wirings. A liquid crystal display device free of defects can be manufactured.

Description

Array substrate for liquid crystal display device and manufacturing method thereof             

1 is an exploded perspective view illustrating a general liquid crystal display device;

2 is a plan view showing some pixels of a conventional array substrate for a liquid crystal display device;

3A to 3E are cross-sectional views of the process of cutting through III-III, IV-IV and V-V of FIG.

4 is a plan view showing some pixels of the array substrate for a liquid crystal display device according to the present invention;

5A through 5D are cross-sectional views illustrating the process of cutting VI-VI, VIII-VIII, VIII-VIII in FIG.

<Explanation of symbols for the main parts of the drawings>

113: gate wiring 115: data wiring

133: First Data Short Circuit Wiring 135: Gate Short Circuit Wiring

137: second data short-circuit wiring 138: gate pad                 

139: data pad terminal 140: data pad

141: gate pad terminal 153: data pad contact hole

155: gate pad contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device. In particular, a short circuit wiring connected to a data wiring and a gate wiring by an external environment during a manufacturing process of an array substrate for a liquid crystal display, and a transparent wiring electrically connecting the short circuit and the two wirings, respectively. The present invention relates to a method of manufacturing an array substrate for a liquid crystal display device capable of preventing an electrical reaction occurring between pixel electrodes and preventing disconnection of wiring, and a structure of the array substrate by the method.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, the active matrix liquid crystal display (AM-LCD) in which the aforementioned thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner is attracting the most attention because of its excellent resolution and ability to implement video.

In general, the structure of a liquid crystal panel, which is a basic component of a liquid crystal display, will be described.

1 is an exploded perspective view schematically illustrating a general liquid crystal display device.

As shown in the drawing, a general liquid crystal display includes a color filter 7 including a black matrix 6 and a sub-color filter (red, green, blue) 8 and an upper portion on which a transparent common electrode 18 is formed on the color filter. And a lower substrate 22 having an array wiring including a substrate 5, a pixel region P and a pixel electrode 17 formed on the pixel region, and a switching element T. The upper substrate 5 and The liquid crystal 14 is filled between the lower substrates 22.

The lower substrate 22 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 13 and the data wiring 15 passing through the plurality of thin film transistors cross each other. Is formed.

The pixel area P is an area defined by the gate line 13 and the data line 15 intersecting each other. The pixel electrode 17 formed on the pixel region P uses a transparent conductive metal having relatively high light transmittance, such as indium-tin-oxide (ITO).

In the liquid crystal display device configured as described above, the liquid crystal layer 14 disposed on the pixel electrode 17 is oriented by a signal applied from the thin film transistor T, and the liquid crystal layer is aligned according to the degree of alignment of the liquid crystal layer. The image can be represented by controlling the amount of light that passes through layer 14.

The gate wiring 13 transfers a pulse voltage driving a gate electrode, which is a first electrode of the thin film transistor T, and the data wiring 15 receives a source electrode, which is a second electrode of the thin film transistor T. It is a means for transmitting the driving signal voltage.

FIG. 2 is an enlarged plan view showing a part of a conventional array substrate for a liquid crystal display device manufactured by a four mask process.

As shown, the array substrate 22 is composed of a plurality of pixels P, and the pixels are thin film transistors T and pixel electrodes 17 which are switching elements. It consists of a storage capacitor (C).

The thin film transistor T includes a gate electrode 26, a source electrode 28, a drain electrode 30, and an active layer 33, and the source electrode 28 includes a data line 15. The gate electrode 26 is connected to the gate line 13 crossing the data line 15 to define the pixel area P.

A gate pad 38 extending to a predetermined area is formed at an end of the gate wiring 13, and a data pad 40 extending to a predetermined area is formed at an end of the data wiring 15.

At the same time, the gate wiring 13 and the data wiring 15 are configured to be electrically connected to a short circuit formed around the substrate.

In detail, the gate pad 38 and the data pad 40 are divided into an odd number and an even number, and the even number of the respective wires is the gate first short circuit 31 and the data first short circuit 33. The odd-numbered lines of the respective wirings are connected to the gate second short circuit 35 and the data second short circuit 37, respectively.

The short-circuit wiring is configured to prevent the disconnection and short-circuit of each wiring against the static electricity generated locally during the fabrication of the array substrate 22. The short-circuit wiring is made to be in an equipotential state to prevent static electricity during the array substrate manufacturing process. It can prevent the disconnection and short circuit of wiring.

In this case, the data line 15 is connected to each of the first short circuit lines 33 and the second short circuit lines 35 and 37 by a data transparent electrode terminal 41.

In this structure, when the array substrate fabrication process is finished and the process of testing for disconnection and short circuit of the wiring is completed, the A portion is cut to remove each short circuit.

At this time, the cut portion has a structure in which both the transparent electrode terminals 39 and 41 and the metal wirings 13 and 15 at the lower portion thereof are exposed in cross section. In the environment, electrolysis occurs due to a battery reaction between the transparent electrode and the wiring, and a defect occurs in the metal wiring.

Hereinafter, a method of manufacturing a conventional array substrate for a liquid crystal display device will be described with reference to FIGS. 3A to 3E. (The four mask process will be described as an example.)

3A through 3E are cross-sectional views illustrating the process sequence of cutting III-III, IV-IV, and V-V of FIG. 2.                         

FIG. 3A illustrates a first mask process step, in which a first conductive metal is deposited and patterned to form a gate wiring 13, a gay electrode 26, and a gate pad 38 extending to a predetermined area from an end of the gate wiring. .

At the same time, the first data short circuit line 33 and the second data short circuit line (37 in FIG. 2) are formed on one side of the substrate in parallel with the gate line 13, and the two data short line lines are formed. The first gate short circuit 31 and the second gate short circuit 35 are formed on both sides that are not parallel to each other.

Next, as shown in FIG. 3B, the insulating layer 43, the amorphous silicon layer 45 ′, and the amorphous silicon layer 47 ′ containing impurities are formed on the substrate 22 on which the gate wiring 13 and the like are formed. ) And the second conductive metal layer 28 'are laminated.

3C illustrates a second mask process step, in which the second conductive metal layer 28 ′ is patterned to expose the active channel 43 on the gate electrode 26, and at the same time, the gate pad 38 and the first, A portion of the second conductive metal layer of the portion of the upper portion of the second data short-circuit wiring 33 (37 of FIG. 2) where the contact hole is to be formed is etched.

Next, a protective layer 51 is formed by depositing or applying an insulating material on the substrate 22 on which the conductive second metal layer 28 ′ is patterned.

FIG. 3D illustrates a third mask process step, wherein the protective layer 51 and the amorphous silicon layer 45 ′ in FIG. 3B are simultaneously patterned to form the source electrode 28, the drain electrode 30, and the gate wiring ( 13 and a data pad 40 defining a pixel region (P in FIG. 2) and a data pad 40 extending a predetermined area from an end of the data wiring.                         

In this case, the data pad 40 includes a portion of the data pad, a protective layer thereon, and an amorphous silicon layer below the data pad contact hole 53, and a gate pad contact hole 55 above the gate pad 38. ) And a data contact hole 57 is formed on the data short-circuit wiring 33.

Next, FIG. 3E illustrates a fourth mask process step, in which a transparent conductive metal is deposited and patterned on the entire surface of the substrate 22 on which the protective layer 51 is patterned, and in side contact with the drain electrode 30. A pixel electrode 17 formed on an area (P in FIG. 2), a gate pad terminal electrode 41 filled in the gate pad contact hole 55 and electrically connected to the gate pad, and the data pad contact hole 53. ) And the data contact hole 57 are simultaneously formed to form a data pad terminal electrode 39 connecting the data line 15 and the data short circuit line 31.

After fabricating the array substrate for the liquid crystal display device in such a process, in order to remove the short-circuit wiring from each wiring, portions B and C, which are ends of the pads, are cut.

As described above, the B and C portions are portions of the data pad 40 and the gate pad 38. As shown in the side view of the cross section, the data pad 40 and the gate pad 38 are each transparent electrode terminals. It consists of (39, 41) and the gate insulating film 43 interposed.

As such, since the separation distance L between the transparent electrode terminals 39 and 41 and the electrode wirings 40 and 38 is too narrow, when the array substrate is driven in a high temperature and high humidity environment, Undesired battery reaction between the electrode wirings can lead to electrical wiring, which can cause wiring defects.

The array substrate for a liquid crystal display device according to the present invention for solving the above problems is manufactured in a structure in which the gate wiring and the data wiring do not overlap with the transparent electrode in a plane at the cutting portion for removing the short circuit. An object of the present invention is to fabricate an array substrate for a liquid crystal display device which does not generate an electrical defect due to a battery reaction caused by a chemical reaction between the transparent electrode and the wiring.

According to an aspect of the present invention, an array substrate for a liquid crystal display device includes: a transparent substrate defined as a display area and a non-display area; A gate line and a data line formed in the display area and crossing each other to define a pixel area; A switching element formed at a point where the gate wiring and the data wiring cross each other; A first data short circuit connected to one side of the substrate, which is a non-display area, by a predetermined interval, connected to an odd data line, a second data short circuit connected to the even data line, and parallel to the data short circuit A first gate short circuit formed on one side of an unsubstantiated substrate and connecting all odd-numbered gate lines; A transparent data pad electrode electrically connecting the first and second data short circuit lines and the data lines; It includes a transparent gate pad electrode connected to the gate pad.

An end of the data pad overlapping the transparent data pad electrode and the gate pad overlapping the transparent gate pad electrode may be bent to the left or the right so as not to overlap the transparent pad electrode. .

The first conductive metal layer and the second conductive metal layer is one selected from the group of conductive metals including aluminum, aluminum alloy, molybdenum, tungsten and the like.

The gate insulating layer and the protective layer may be selected from an inorganic insulating material group including silicon nitride and silicon oxide, and an organic insulating material group including benzocyclobutene and acrylic resin.

The pixel electrode may be one selected from a group of transparent conductive metals including ITO and IZO.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

An embodiment of the present invention proposes an array substrate configured so that the wiring and the transparent electrode terminal do not overlap at a portion of cutting the substrate to remove the short circuit.

4 is a diagram illustrating some pixels of an array substrate for a liquid crystal display according to the present invention.

As shown, the array substrate for a liquid crystal display according to the present invention is configured to cross the gate wiring 113 and the data wiring 115, and constitute a thin film transistor (T) as a switching element at the intersection of the two wirings. do.

A gate pad 138 extending at a predetermined area at the end of the gate wiring 113 and a data pad 140 extending at a predetermined area at the end of the data wiring 115 are formed.

In addition, as described above, the first data short circuit 133 and the second data short circuit 137 for data wiring are disposed around the substrate in order to prevent disconnection of the wiring by static electricity during the fabrication process of the array substrate. And a first gate short circuit (not shown) and a second gate short circuit 135 for the gate wiring 113.

In this case, the first data short circuit 133 and the second data short circuit 137 are formed of the same material on the same layer as the gate electrode 126.

Accordingly, the data pad electrode terminal 139 connected to the data pad 140 through the data pad contact hole 153 to transmit a signal applied from the outside to the data wiring 115 is connected to the data pad 140. The first or second short circuit lines 133 and 137 are formed to be connected at the same time.

In addition, a gate pad electrode terminal 141 connected to the gate pad 138 and the contact hole 155 is connected to the gate pad 138 and receives the gate signal applied from the outside to the gate pad 113. Form.

At this time, the ends extending from the data pads and the gate pads adjacent to the first short circuit and the second short circuit are patterned in a shape of a slight left or right bent so as not to overlap the respective pad electrode terminals.

In this configuration, a portion cut in the process of removing the short circuits 133, 135, and 137 may have a cross-sectional structure in which the pad electrode terminals, which are transparent electrodes, and the wirings thereunder are slightly spaced apart with a protective layer therebetween.

Such a structure can prevent the corrosion of the wiring by preventing the battery reaction between the transparent electrode and the metal wiring by increasing the separation distance between the transparent electrode and each wiring more sufficiently.

Hereinafter, a structure and a manufacturing method of an array substrate for a liquid crystal display device according to the present invention will be described with reference to FIGS. 5A to 5D.

5A through 5D are cross-sectional views illustrating a process sequence of cutting VI-VI, VIII-VIII, VIII-VIII in FIG. 4.

FIG. 5A illustrates a first mask process step of depositing and patterning a first conductive metal selected from a group of conductive metals including aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), and the like. A gate pad 138 extending from the gate wiring 113, the gate electrode 126, and the end of the gate wiring 113 by a predetermined area is formed.

At the same time, the first data shorting line 133 and the second data shorting line (137 of FIG. 4) are formed on one side of the substrate in parallel with the gate line 113, and the two data shorting lines are formed. The first gate short circuit (not shown) and the second gate short circuit 135 may be formed on both sides that are not parallel to each other.                     

Next, as a second mask process step in FIG. 6B, an amorphous silicon layer containing an insulating layer 143, an amorphous silicon layer 145 ′ and impurities on the substrate 122 on which the gate wiring 113 and the like are formed ( 147 ') and the second conductive metal layer 128' are laminated.

Next, the second conductive metal layer 128 ′ is patterned to expose the active channel 145 ′ over the gate electrode 126, and at the same time, the gate pad 138 and the first and second data short circuit lines ( 133 and 137 of FIG. 4 and the first and second gate short circuits 131 and 133 of FIG. 4 are later etched.

FIG. 5C illustrates a third mask process, in which a protective layer 151 is formed by depositing or applying an insulating material on the substrate 122 on which the conductive second metal layer 128 ′ is patterned.

The protective layer 151 and the amorphous silicon layer (145 ′ in FIG. 4) are patterned at the same time to cross the source electrode 128, the drain electrode 130, and the gate wiring 113 to cross the pixel region (FIG. 2). A data line 115 defining P) and a data pad 140 extending from the end of the data line 115 by a predetermined area.

In this case, a portion of the data pad, an amorphous silicon layer and a protective layer thereof are etched to form a data pad contact hole 153, and a gate pad contact hole 155 on the gate pad 138. ) And a data contact hole 157 on the data short circuit line 133.

In this case, the extension lines of the data pads or gate pads that are patterned in the process of patterning the protective layer may be formed in a shape bent to the left or right rather than being formed at a position in line with the contact contact holes formed on the respective short circuit lines.                     

Next, FIG. 5D is a fourth mask process step, indium tin oxide (ITO) and indium zinc oxide (ITO) on the entire surface of the substrate 122 on which the protective layer 151 is patterned. and depositing and patterning a transparent conductive metal such as indium-zinc-oxide (ITO) to form a side contact with the drain electrode 130 and the pixel electrode 117 formed on the pixel region (P in FIG. 4) and the gate. A data pad terminal electrode formed by simultaneously charging the gate pad terminal electrode 141 connected to the gate pad 138 through the pad contact hole 155, and the data pad contact hole 153 and the data contact hole 157. 139).

After fabricating the array substrate for the liquid crystal display device in such a process, in order to remove the short-circuit wiring from the respective wirings, C and D portions, which are ends of the pads, are cut.

As described above, the C and D portions are ends of the data pad 140 and the gate pad 138, and the data pad electrode, the gate pad electrode, and the insulating layer 143 are shown in a side view of the cross section. It is configured to be spaced apart by a predetermined distance l + α with a cross-sectional area therebetween.

Such a configuration makes it possible to secure a sufficient distance such that a battery reaction between the metal wire exposed to the cut portion and the transparent electrode does not occur.

In the present embodiment, a method of manufacturing an array substrate for a liquid crystal display device manufactured by using four masks has been described as an example. However, these embodiments can be applied to the configuration of an array substrate manufactured by a similar method.

In the same manner as described above, an array substrate for a liquid crystal display device according to the present invention can be manufactured.

Therefore, the present invention prevents battery reaction between the transparent electrode and the metal wiring, so that an array substrate without wiring defects can be manufactured, thereby improving the product yield of the liquid crystal display device.

Claims (4)

A transparent substrate defined as a display area and a non-display area; A gate line and a data line formed in the display area and crossing each other to define a pixel area; A switching element formed at a point where the gate wiring and the data wiring cross each other; A first data short circuit connected to one side of the substrate, which is a non-display area, by a predetermined interval, connected to an odd data line, a second data short circuit connected to the even data line, and parallel to the data short circuit A first gate short circuit formed on one side of the substrate, the second gate short circuit interconnecting all of the odd-numbered gate wirings, and a second gate short circuit interconnection connecting all of the even-numbered gate wirings; A transparent data pad electrode electrically connecting the first and second data short circuit lines and the data lines; A transparent gate pad electrode connected to the gate pad In the array substrate comprising: An end of the data pad overlapping with the transparent data pad electrode and an end of the gate pad overlapping with the transparent gate pad electrode are bent left or right so as not to overlap each of the transparent pad electrodes. Array substrate. The method of claim 1, And the first conductive metal layer and the second conductive metal layer are one selected from a group of conductive metals including aluminum, aluminum alloy, molybdenum, tungsten, and the like. The method of claim 1, And the gate insulating layer and the protective layer are selected from an inorganic insulating material group including silicon nitride and silicon oxide, and an organic insulating material group including benzocyclobutene and acrylic resin. The method of claim 1, And the pixel electrode is one selected from a group of transparent conductive metals including ITO and IZO.

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